Semiconductor structure and method for forming semiconductor structure

Abstract

The embodiment of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure comprises: a substrate, including an array region and a peripheral region, a first isolation structure in the peripheral region, a second isolation structure in the array region, the top opening area of ​​the first isolation structure being larger than the top opening area of ​​the second isolation structure; a first groove in the first isolation structure, and a first insulating structure for filling the first groove; the first insulating structure comprises at least a top insulating layer, the top surface of the top insulating layer is flush with the top surface of the substrate, and the top insulating layer comprises at least a low dielectric constant material. The embodiment of the present invention fills the first groove in the first isolation structure with the first insulating structure in the peripheral region, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral region, thereby improving the yield of the final device formed, and preventing the performance loss of the shallow trench isolation structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] In the process of manufacturing semiconductor devices, an isolation structure is usually used to isolate a plurality of materials disposed on a substrate. The isolation structure is usually a shallow trench isolation (STI) structure.

[0003] The trench of the shallow trench isolation structure occupies a small area and can better adapt to semiconductor devices with smaller critical dimensions. At the same time, the performance of the shallow trench isolation structure is crucial to the performance and yield of the final semiconductor device.

[0004] However, when the critical dimensions of semiconductor devices are reduced to the 28nm node and below, the profile of the shallow trench isolation structure becomes increasingly difficult to control. For example, when the buried word line structure is subsequently formed, the traditional dry cleaning and wet cleaning will damage the shallow trench isolation structure, which may cause the height of the shallow trench isolation structure to be lower than the substrate, resulting in defects such as leakage at the edge of the shallow trench isolation structure, reducing the reliability of the semiconductor device, and further resulting in the loss of yield and performance of the final device. Summary of the invention

[0005] The embodiments of the present invention provide a semiconductor structure and a method for forming the semiconductor structure, which improves the yield of a final device formed by filling a damaged shallow trench isolation structure and prevents performance loss of the shallow trench isolation structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including an array area and a peripheral area, a first isolation structure in the peripheral area, a second isolation structure in the array area, the top opening area of ​​the first isolation structure is larger than the top opening area of ​​the second isolation structure; the first isolation structure has a first groove, and a first insulating structure for filling the first groove; the first insulating structure includes at least a top isolation layer, the top surface of the top isolation layer is flush with the top surface of the substrate, and the top isolation layer includes at least a low dielectric constant material.

[0007] Compared with the related art, the first groove in the first isolation structure is filled with the first insulating structure in the peripheral area, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral area; in addition, the top isolation layer of the shallow trench isolation structure in the peripheral area includes a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral area.

[0008] In addition, the material of the top isolation layer includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. The top isolation layer is formed by a low dielectric constant material with strong corrosion resistance to prevent the shallow trench isolation structure in the peripheral area from being damaged in subsequent processes.

[0009] In addition, the peripheral region includes an isolation groove, the first isolation structure is used to fill the isolation groove, and the first isolation structure includes a first oxide layer, a barrier layer, and a second oxide layer sequentially arranged on the sidewall of the isolation groove; the height of the top surface of the first oxide layer and the second oxide layer is lower than the height of the top surface of the barrier layer; the first oxide layer, the barrier layer, and the substrate surround a first opening; the barrier layer and the second oxide layer surround a second opening; the first opening and the second opening together constitute a first groove. The specific structure of the first isolation structure provided in this embodiment is that the shallow trench isolation structure has a multi-layer interface layer, which is conducive to improving the dielectric performance of the shallow trench isolation structure in the peripheral region.

[0010] In addition, the first insulating structure further includes a bottom isolation layer, which is located on the top surface of the first groove and on the bottom surface of the top isolation layer. The first insulating structure is a multi-layer structure, and the interface layer of the shallow trench isolation structure in the peripheral area is further increased through the multi-layer structure, which is conducive to improving the dielectric performance of the shallow trench isolation structure in the peripheral area.

[0011] In addition, the bottom isolation layer and the top isolation layer are made of different materials, and there is a first air gap between the top isolation layer and the bottom isolation layer. The first isolation structure has the first air gap, which further improves the dielectric performance of the shallow trench isolation structure in the peripheral area.

[0012] In addition, the second isolation structure has a second groove and a second insulating structure for filling the second groove; the second insulating structure at least includes a top insulating layer, the top surface of the top insulating layer is flush with the top surface of the substrate, and the top insulating layer at least includes a low dielectric constant material. The top insulating layer is formed by the low dielectric constant material to improve the dielectric performance of the shallow trench isolation structure in the array area.

[0013] In addition, the second insulating structure also includes a bottom insulating layer, which is located on the top surface of the second groove and on the bottom surface of the top insulating layer. The multi-layer structure further increases the interface layer of the shallow trench isolation structure in the array area, which is beneficial to improving the dielectric performance of the shallow trench isolation structure in the peripheral area.

[0014] In addition, the bottom insulating layer and the top insulating layer are made of different materials, and there is a second air gap between the top insulating layer and the bottom insulating layer. The second air gap further improves the dielectric performance of the shallow trench isolation structure in the array area, and the second air gap is also used to reduce the parasitic capacitance between the word line structures.

[0015] An embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, the top opening area of ​​the first isolation structure being larger than the top opening area of ​​the second isolation structure; removing a portion of the thickness of the first isolation structure to form a first groove in the peripheral region; forming a first insulating structure filling the first groove, the first insulating structure comprising at least a top isolation layer, the top surface of the top isolation layer being flush with the top surface of the substrate, and the top isolation layer comprising at least a low dielectric constant material.

[0016] In addition, forming a first groove and a first insulating structure includes: forming a bottom isolation layer covering the sidewalls and bottom of the first groove; forming a top isolation layer filling the first groove, the top isolation layer and the bottom isolation layer together constitute the first insulating structure, and the materials of the top isolation layer and the bottom isolation layer are different.

[0017] In addition, forming a top isolation layer filling the first groove includes: performing a first sealing process on the first groove to form the top isolation layer; after the first sealing process, a first air gap is formed between the top isolation layer and the bottom isolation layer.

[0018] In addition, the method for manufacturing the semiconductor structure also includes: removing a portion of the thickness of the second isolation structure to form a second groove in the array area; forming a second insulating structure to fill the second groove, the second insulating structure at least includes a top insulating layer, the top surface of the top insulating layer is flush with the top surface of the substrate, and the top insulating layer at least includes a low dielectric constant material.

[0019] In addition, forming a second groove and a second insulating structure includes: forming a bottom insulating layer covering the second groove and the bottom; forming a top insulating layer filling the second groove, the top insulating layer and the bottom insulating layer together constitute the second insulating structure, and the materials of the top insulating layer and the bottom insulating layer are different.

[0020] In addition, forming a top insulating layer filling the second groove includes: performing a second sealing process on the second groove to form a top insulating layer; after the second sealing process, a second air gap is formed between the top insulating layer and the bottom insulating layer.

[0021] In addition, the steps of removing a portion of the thickness of the second isolation structure and forming a second groove in the array region and the step of removing a portion of the thickness of the first isolation structure and forming a first groove in the peripheral region are performed simultaneously. By simultaneously forming the first groove and the second groove, and subsequently simultaneously forming the first insulation structure and the second insulation structure, the formation efficiency of the shallow trench isolation structure is improved.

[0022] Compared with the related art, a first insulating structure is formed in the peripheral area to fill the first groove in the first isolation structure, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral area. In addition, a top isolation layer of the shallow trench isolation structure in the peripheral area is formed by a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by pictures in the corresponding drawings. Unless otherwise stated, the pictures in the drawings are not limited to scale.

[0024] Figure 1 and Figure 2 A schematic structural diagram of a substrate provided in accordance with a first embodiment of the present invention;

[0025] Figure 3 A first structural schematic diagram of a semiconductor structure provided by the first embodiment of the present invention;

[0026] Figure 4 A second structural schematic diagram of the semiconductor structure provided by the first embodiment of the present invention;

[0027] Figure 5 A third structural schematic diagram of the semiconductor structure provided by the first embodiment of the present invention;

[0028] Figure 6 and Figure 7 A schematic structural diagram of a substrate provided in accordance with a second embodiment of the present invention;

[0029] Figure 8 A schematic diagram of a first structure of a semiconductor structure provided by a second embodiment of the present invention;

[0030] Fig. 9 A second structural schematic diagram of a semiconductor structure provided for the second embodiment of the present invention;

[0031] Fig.10 A third structural schematic diagram of the semiconductor structure provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0032] When the critical dimensions of semiconductor devices are reduced to the 28nm node and below, the profile of the shallow trench isolation structure becomes increasingly difficult to control. For example, when the buried word line structure is subsequently formed, the traditional dry cleaning and wet cleaning will damage the shallow trench isolation structure, which may cause the height of the shallow trench isolation structure to be lower than the substrate, resulting in defects such as leakage at the edge of the shallow trench isolation structure, reducing the reliability of the semiconductor device, and further resulting in the loss of yield and performance of the final device.

[0033] To solve the above problems, a first embodiment of the present invention provides a semiconductor structure, including: a substrate, including an array area and a peripheral area, a first isolation structure in the peripheral area, a second isolation structure in the array area, the top opening area of ​​the first isolation structure is larger than the top opening area of ​​the second isolation structure; the first isolation structure has a first groove, and a first insulating structure for filling the first groove; the first insulating structure at least includes a top isolation layer, the top surface of the top isolation layer is flush with the top surface of the substrate, and the top isolation layer at least includes a low dielectric constant material.

[0034] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and quoted from each other without contradiction.

[0035] Figure 1 to Figure 5 This is a schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present invention. The semiconductor structure of this embodiment is specifically described below.

[0036] refer to Figure 1 , providing a substrate 100, including an array area 101 and a peripheral area 102, the peripheral area 102 has a first isolation structure 201, the array area 101 has a second isolation structure 202, and the top opening area of ​​the first isolation structure 201 is larger than the top opening area of ​​the second isolation structure 202.

[0037] The material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.; in the present embodiment, the substrate 100 is made of silicon material. Those skilled in the art will appreciate that the present embodiment uses silicon material as the substrate 100 to facilitate the understanding of the semiconductor structure provided by the present embodiment by those skilled in the art, and does not constitute a limitation on the present embodiment. In actual application, a suitable substrate material may be selected as required.

[0038] In this embodiment, the first isolation structure 201 and the second isolation structure 202 are single-layer structures, and the materials of the first isolation structure 201 and the second isolation structure 202 are silicon oxide. In other embodiments, the materials of the first isolation structure and the second isolation structure are insulating materials, such as silicon nitride, silicon oxynitride, or silicon carbide; in addition, in other embodiments, the first isolation structure and the second isolation structure can be multi-layer structures.

[0039] Specifically, the array region 101 includes a first array region 111 and a second array region 121 . The second isolation structure 202 and the buried word line structure 203 in the first array region 111 are separated from each other; the buried word line structure 203 in the second array region 121 is buried in the second isolation structure 202 .

[0040] The buried word line structure 203 separated from the second isolation structure 202 includes a buried barrier layer 213 , a word line 223 and a word line isolation layer 233 .

[0041] In this embodiment, the material of the word line isolation layer 223 is the same as that of the first isolation layer 201 and the second isolation layer 202; in other embodiments, the material of the word line isolation layer can be an insulating material different from that of the first isolation structure and the second isolation structure, such as insulating materials such as silicon nitride, silicon oxynitride or silicon carbide.

[0042] The word line 223 is used to connect the gates of the transistors formed in the array region 101 . In the present embodiment, the material of the word line 223 is tungsten or a tungsten compound.

[0043] The buried barrier layer 213 is used to bury the word line 223 in the substrate 100. In this embodiment, the material of the buried barrier layer 213 is silicon nitride. In other embodiments, the buried barrier layer can be made of other insulating materials, such as silicon oxide, silicon oxynitride or silicon carbide. In addition, the buried word line structure 203 formed in the second isolation structure 202 uses the second isolation structure 202 as the above-mentioned word line isolation layer.

[0044] It should be noted that in addition to the above-mentioned structure, the substrate 100 also includes other structures to ensure that the subsequently formed memory can operate normally. Those skilled in the art will understand that the above-mentioned schematic structure is intended to facilitate their understanding of the semiconductor structure provided in this embodiment, and does not mean that the substrate 100 only includes the above-mentioned structure.

[0045] refer to Figure 2 , the first isolation structure 201 has a first groove 301 therein.

[0046] Specifically, in a direction perpendicular to the surface of the substrate 100, the depth of the first groove 301 is 40 nm to 90 nm. In one example, the depth of the first groove 301 may be 50 nm, 60 nm, 70 nm or 80 nm.

[0047] refer to Figure 3 to Figure 5 , the first insulating structure 401 is used to fill the first groove 301 .

[0048] The first insulating structure 401 at least comprises a top isolation layer 411, the top surface of which is flush with the top surface of the substrate 100, and the top isolation layer 411 at least comprises a low dielectric constant material. The top isolation layer 411 is made of a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral region 102.

[0049] In addition, the material of the top isolation layer 411 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. Silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride have strong corrosion resistance. The top isolation layer 411 is formed by a low dielectric constant material with strong corrosion resistance to prevent the first insulating structure 401 formed from being damaged in subsequent processes.

[0050] This embodiment provides two specific structures of the first insulating structure 401 . The two different first insulating structures 401 are described in detail below with reference to the accompanying drawings.

[0051] The first one: reference Figure 3 , the first insulating structure 401 is a single-layer structure, that is, the top isolation layer 411 fills the first groove 301 to form the first insulating structure 401 .

[0052] The second type: reference Figure 4 and Figure 5 The first insulating structure 401 further includes a bottom isolation layer 421 , which is located on a top surface of the first groove 301 and on a bottom surface of the top isolation layer 411 .

[0053] Specifically, the bottom isolation layer 421 is located on the sidewall and top surface of the first groove 301 , and the top isolation layer 411 is used to fill the remaining first groove 301 covered by the bottom isolation layer 421 .

[0054] The material of the bottom isolation layer 421 can be the same as the material of the top isolation layer 411, or the material of the bottom isolation layer 421 can be different from the material of the top isolation layer 411. In the present embodiment, the material of the bottom isolation layer 421 is different from the material of the top isolation layer 411, and the interface layer of the shallow trench isolation structure in the peripheral area 102 is further increased through the multi-layer structure, which is beneficial to improving the dielectric properties of the shallow trench isolation structure in the peripheral area 102.

[0055] Specifically, the material of the bottom isolation layer 421 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. In this embodiment, the thickness of the bottom isolation layer 421 is 3nm to 5nm, specifically 3.5nm, 4.0nm or 4.5nm.

[0056] It should be noted that, in other embodiments, the thickness of the bottom isolation layer can be appropriately increased to increase the aspect ratio of the first groove. The groove with a larger aspect ratio is easier to seal. A first air gap exists between the top isolation layer and the bottom isolation layer formed by the sealing process. The dielectric performance of the shallow trench isolation structure in the peripheral area can be further improved by the first insulating structure having the first air gap.

[0057] refer to Figure 2 In this embodiment, the second isolation structure 202 has a second groove 302 therein.

[0058] Specifically, in a direction perpendicular to the surface of the substrate 100, the depth of the second groove 302 is 30 nm to 70 nm. In one example, the depth of the second groove 302 may be 40 nm, 50 nm or 60 nm.

[0059] refer to Figure 3 to Figure 5 In this embodiment, a second insulating structure 402 for filling the second groove 302 is also included.

[0060] The second insulating structure 402 at least comprises a top insulating layer 412, the top surface of which is flush with the top surface of the substrate 100, and the top insulating layer 412 at least comprises a low dielectric constant material. The top insulating layer 412 is made of a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the array region 101.

[0061] In addition, the material of the top insulating layer 412 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon nitride carbide. Silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon nitride carbide have strong corrosion resistance. The top insulating layer 412 is formed by a low dielectric constant material with strong corrosion resistance to prevent the formed second insulating structure 402 from being damaged in subsequent processes. In this embodiment, the material of the top insulating layer 412 is the same as that of the top isolation layer 411.

[0062] This embodiment provides three specific structures of the second insulating structure 402 . The three different second insulating structures 402 are described in detail below with reference to the accompanying drawings.

[0063] The first one: reference Figure 3 , the second insulating structure 402 is a single-layer structure, that is, the top insulating layer 412 fills the second groove 302 to form the second insulating structure 402 .

[0064] The second type: reference Figure 4 The second insulating structure 402 further includes a bottom insulating layer 422 , which is located on a top surface of the second groove 302 and on a bottom surface of the top insulating layer 412 .

[0065] Specifically, the bottom insulating layer 422 is located on the sidewalls and the top surface of the second groove 302 , and the top insulating layer 412 is used to fill the remaining second groove 302 covered by the bottom insulating layer 422 .

[0066] The material of the bottom insulating layer 422 may be the same as that of the top insulating layer 412, or may be different from that of the top insulating layer 412. In this embodiment, the material of the bottom insulating layer 422 is different from that of the top insulating layer 412. Further increasing the interface layer of the shallow trench isolation structure in the array region 101 through the multi-layer structure is beneficial to improving the dielectric properties of the shallow trench isolation structure in the array region 101, and in this embodiment, the material of the bottom insulating layer 422 is the same as that of the bottom isolation layer 421.

[0067] Specifically, the material of the bottom insulating layer 422 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. In this embodiment, the thickness of the bottom insulating layer 422 is 3nm to 5nm, specifically 3.5nm, 4.0nm or 4.5nm.

[0068] The third type: reference Figure 5 Since the top opening area of ​​the first isolation structure 201 is larger than the top opening area of ​​the second isolation structure 202, it can be seen that the aspect ratio of the second groove 302 is larger than the aspect ratio of the first groove 301. The groove with a larger aspect ratio is easier to seal. A second air gap 502 is formed between the top insulating layer 412 and the bottom insulating layer 422 formed by the sealing process. The second insulating structure 402 with the second air gap 502 further improves the dielectric performance of the shallow trench isolation structure in the array area 101.

[0069] Compared with the related art, the first groove in the first isolation structure is filled with the first insulating structure in the peripheral area, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral area; in addition, the top isolation layer of the shallow trench isolation structure in the peripheral area includes a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral area.

[0070] The second embodiment of the present invention relates to a semiconductor structure. Different from the first embodiment, the second embodiment provides a specific structure of a shallow trench isolation structure and a corresponding first insulating structure and a second insulating structure; the dielectric capacity of the shallow trench isolation structure can be further improved by using a shallow trench isolation structure with a multi-layer interface layer.

[0071] Figure 6 to Figure 10 This is a schematic diagram of the structure of a semiconductor structure provided in an embodiment of the present invention. The semiconductor structure of this embodiment is specifically described below.

[0072] The method for forming a semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, and parts that are the same as or corresponding to the first embodiment will not be described in detail below.

[0073] refer to Figure 6 The peripheral region 102 includes an isolation groove, the first isolation structure 201 is used to fill the isolation groove, and the first isolation structure 201 includes a first oxide layer 212, a barrier layer 222 and a second oxide layer 232 sequentially arranged on the sidewall of the isolation groove.

[0074] Specifically, the first oxide layer 212 is located at the sidewalls and bottom of the isolation groove, the barrier layer 222 is located at the sidewalls and bottom of the first oxide layer 212, and the second oxide layer 232 is located at the sidewalls and bottom of the barrier layer 222, wherein the first oxide layer 212 and the second oxide layer 232 are located on opposite sides of the barrier layer 2223.

[0075] In this embodiment, the material of the first oxide layer 212 is the same as the material of the third oxide layer 232, the material of the first oxide layer 212 and the third oxide layer 232 is silicon oxide, and the material of the barrier layer 222 is silicon nitride. The shallow trench isolation structure of the peripheral area 102 formed by the multi-layer insulating layer has a multi-layer interface layer, which is conducive to improving the dielectric performance of the shallow trench isolation structure of the peripheral area 102.

[0076] refer to Figure 7 The top surfaces of the first oxide layer 212 and the second oxide layer 232 are lower than the top surface height of the barrier layer 222 . The first oxide layer 212 , the barrier layer 222 and the substrate 100 form a first opening 311 . The barrier layer 222 and the second oxide layer 232 form a second opening 321 . The first opening 311 and the second opening together constitute a first groove 301 .

[0077] refer to Figure 8 to Figure 10 , the first insulating structure 401 is used to fill the first groove 301 .

[0078] The first insulating structure 401 at least comprises a top isolation layer 411, the top surface of which is flush with the top surface of the substrate 100, and the top isolation layer 411 at least comprises a low dielectric constant material. The top isolation layer 411 is made of a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral region 102.

[0079] In addition, the material of the top isolation layer 411 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. Silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride have strong corrosion resistance. The top isolation layer 411 is formed by a low dielectric constant material with strong corrosion resistance to prevent the first insulating structure 401 formed from being damaged in subsequent processes.

[0080] This embodiment provides three specific structures of the first insulating structure 401 . The three different first insulating structures 401 are described in detail below with reference to the accompanying drawings.

[0081] The first one: reference Figure 8 , the first insulating structure 401 is a single-layer structure, that is, the top isolation layer 411 fills the first groove 301 to form the first insulating structure 401 .

[0082] The second type: reference Fig. 9 The first insulating structure 401 further includes a bottom isolation layer 421 , which is located on a top surface of the first groove 301 and on a bottom surface of the top isolation layer 411 .

[0083] Specifically, the bottom isolation layer 421 is located on the sidewall and top surface of the first groove 301 , and the top isolation layer 411 is used to fill the remaining first groove 301 covered by the bottom isolation layer 421 .

[0084] The material of the bottom isolation layer 421 may be the same as that of the top isolation layer 411, or the material of the bottom isolation layer 421 may be different from that of the top isolation layer 411; in this embodiment, the material of the bottom isolation layer 421 is different from that of the top isolation layer 411. Further increasing the interface layer of the shallow trench isolation structure in the peripheral region 102 through the multi-layer structure is beneficial to improving the dielectric performance of the shallow trench isolation structure in the peripheral region 102.

[0085] Specifically, the material of the bottom isolation layer 421 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. In this embodiment, the thickness of the bottom isolation layer 421 is 3nm to 5nm, specifically 3.5nm, 4.0nm or 4.5nm.

[0086] The third type: reference Fig.10 The first groove 301 is divided into a first opening 311 and a second opening 321, resulting in a larger depth-to-width ratio of the first opening. In the first opening 311, a first air gap 501 exists between the top isolation layer 411 and the bottom isolation layer 421. The first insulating structure 401 having the first air gap 501 further improves the dielectric performance of the shallow trench isolation structure in the peripheral region 102.

[0087] This embodiment provides three specific structures of the second insulating structure 402 . The three different second insulating structures 402 are described in detail below with reference to the accompanying drawings.

[0088] The first one: reference Figure 8 , the second insulating structure 402 is a single-layer structure, that is, the top insulating layer 412 fills the second groove 302 to form the second insulating structure 402 .

[0089] The second type: reference Fig. 9 The second insulating structure 402 further includes a bottom insulating layer 422 , which is located on a top surface of the second groove 302 and on a bottom surface of the top insulating layer 412 .

[0090] Specifically, the bottom insulating layer 422 is located on the sidewalls and the top surface of the second groove 302 , and the top insulating layer 412 is used to fill the remaining second groove 302 covered by the bottom insulating layer 422 .

[0091] The material of the bottom insulating layer 422 can be the same as the material of the top insulating layer 412, or the material of the bottom insulating layer 422 can be different from the material of the top insulating layer 412; in this embodiment, the material of the bottom insulating layer 422 is different from the material of the top insulating layer 412. Further increasing the interface layer of the shallow trench isolation structure in the array area 101 through the multi-layer structure is beneficial to improving the dielectric properties of the shallow trench isolation structure in the array area 101. In this embodiment, the material of the bottom insulating layer 422 is the same as the material of the bottom isolation layer 421.

[0092] Specifically, the material of the bottom insulating layer 422 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. In this embodiment, the thickness of the bottom insulating layer 422 is 3nm to 5nm, specifically 3.5nm, 4.0nm or 4.5nm.

[0093] The third type: reference Fig.10 Since the top opening area of ​​the first isolation structure 201 is larger than the top opening area of ​​the second isolation structure 202, it can be known that the aspect ratio of the second groove 302 is larger than the aspect ratio of the first groove 301. The groove with a larger aspect ratio is easier to seal. A second air gap 502 is formed between the top insulating layer 412 and the bottom insulating layer 422 formed by the sealing process. The second insulating structure 402 with the second air gap 502 further improves the dielectric performance of the shallow trench isolation structure in the array area 101.

[0094] Compared with the related art, the first groove in the first isolation structure is filled with the first insulating structure in the peripheral area, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral area; in addition, the top isolation layer of the shallow trench isolation structure in the peripheral area includes a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral area.

[0095] Since the first embodiment corresponds to this embodiment, this embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0096] A third embodiment of the present invention relates to a method for forming a semiconductor structure.

[0097] The method for forming a semiconductor structure comprises: providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, the top opening area of ​​the first isolation structure being larger than the top opening area of ​​the second isolation structure; removing a portion of the thickness of the first isolation structure to form a first groove in the peripheral region; forming a first insulating structure filling the first groove, the first insulating structure comprising at least a top isolation layer, the top surface of the top isolation layer being flush with the top surface of the substrate, and the top isolation layer comprising at least a low dielectric constant material.

[0098] It should be noted that in this embodiment, the step of removing a portion of the thickness of the second isolation structure to form the second groove in the array area and the step of removing a portion of the thickness of the first isolation structure to form the first groove in the peripheral area are performed simultaneously; by forming the first insulating structure and the second insulating structure at the same time, the formation efficiency of the shallow trench isolation structure is improved. In other embodiments, the first insulating structure and the second insulating structure can also be formed by different steps, and this embodiment does not limit the order of forming the first insulating structure and the second insulating structure.

[0099] refer to Figure 6 to Figure 10 The method for forming the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to the first embodiment and the second embodiment will not be described in detail below.

[0100] refer to Figure 6 , providing a substrate 100, the substrate 100 includes an array area 101 and a peripheral area 102, the peripheral area 102 has a first isolation structure 201, the array area 101 has a second isolation structure 202, and the top opening area of ​​the first isolation structure 201 is larger than the top opening area of ​​the second isolation structure 202.

[0101] The material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.; in the present embodiment, the substrate 100 is made of silicon material. Those skilled in the art will appreciate that the present embodiment uses silicon material as the substrate 100 to facilitate the understanding of the semiconductor structure provided by the present embodiment by those skilled in the art, and does not constitute a limitation on the present embodiment. In actual application, a suitable substrate material may be selected as required.

[0102] Specifically, the peripheral region 102 includes an isolation groove, the first isolation structure 201 is used to fill the isolation groove, and the first isolation structure 201 includes a first oxide layer 212, a barrier layer 222 and a second oxide layer 232 sequentially arranged on the sidewall of the isolation groove.

[0103] The first oxide layer 212 is located at the sidewall and bottom of the isolation groove, the barrier layer 222 is located at the sidewall and bottom of the first oxide layer 212 , and the second oxide layer 232 is located at the sidewall and bottom of the barrier layer 222 , wherein the first oxide layer 212 and the second oxide layer 232 are located on opposite sides of the barrier layer 2223 .

[0104] The material of the first oxide layer 212 is the same as that of the third oxide layer 232. The materials of the first oxide layer 212 and the third oxide layer 232 are silicon oxide, and the material of the barrier layer 222 is silicon nitride. The shallow trench isolation structure of the peripheral area 102 formed by the multi-layer isolation layer has a multi-layer interface layer, which is conducive to improving the dielectric performance of the shallow trench isolation structure of the peripheral area 102.

[0105] refer to Figure 7 , partially removing the thickness of the first isolation structure 201 to form a first groove 301 in the peripheral area 102 , and simultaneously partially removing the thickness of the second isolation structure 202 to form a second groove 302 in the array area 101 .

[0106] Specifically, wet etching is used to remove a portion of the first oxide layer 212, the second oxide layer 232, and a portion of the second isolation structure 202, respectively forming a first groove 301 located in the peripheral area 102 and a second groove 302 located in the array area 101. In this embodiment, the etching solution used in the wet etching is a hydrogen fluoride solution, and the concentration ratio of hydrogen fluoride to water in the hydrogen fluoride solution is 1:50 to 1:150, such as 1:75, 1:100 or 1:125; the etching time of the wet etching is 30s to 100s, such as 40s, 50s, 60s, 70s, 80s or 90s.

[0107] The depth of the formed first groove 301 is 40 nm to 90 nm, for example, 50 nm, 60 nm, 70 nm or 80 nm; the depth of the formed second groove 302 is 30 nm to 70 nm, for example, 40 nm, 50 nm or 60 nm.

[0108] refer to Figure 8 to Figure 10 , forming a first insulating structure 401 filling the first groove 301, the first insulating structure 401 at least includes a top insulating layer 411, the top surface of the top insulating layer 411 is flush with the top surface of the substrate 100, and the top insulating layer 411 at least includes a low dielectric constant material; at the same time, forming a second insulating structure 402 filling the second groove 302, the second insulating structure 402 at least includes a top insulating layer 412, the top surface of the top insulating layer 412 is flush with the top surface of the substrate 100, and the top insulating layer 412 at least includes a low dielectric constant material.

[0109] Specifically, this embodiment provides three methods for forming the first insulating structure 401 and the second insulating structure 402. The three methods for forming the first insulating structure 401 and the second insulating structure 402 provided in this embodiment are described in detail below in conjunction with the accompanying drawings.

[0110] The first one: reference Figure 8 , forming a first filling opening 301 (refer to Figure 7 ) and the second opening 302 (reference Figure 7 ) and a top dielectric film (not shown) covering the substrate 100, the material of the top dielectric film (not shown) at least includes one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon nitride carbide. Silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon nitride carbide have strong corrosion resistance. The top dielectric film (not shown) is formed by a low dielectric constant material with strong corrosion resistance to prevent the first insulating structure 401 and the second insulating structure 402 from being damaged in subsequent processes.

[0111] The top dielectric film (not shown) is etched until the surface of the substrate 100 is exposed, thereby forming a top isolation layer 411 in the peripheral region 102 and a top insulating layer 412 in the array region 101 .

[0112] In one example, the top dielectric film (not shown) is etched by chemical mechanical polishing, and the top dielectric film (not shown) is polished by chemical mechanical polishing to form a top isolation layer 411 located in the peripheral area 102 and a top insulating layer 412 located in the array area 101. The chemical mechanical polishing method has a higher removal rate than the etching process, which is beneficial to shortening the process cycle.

[0113] The top insulating layer 411 fills up the first groove 301 to form the first isolation structure 201 , and the top insulating layer 412 fills up the second groove 302 to form the second isolation structure 202 .

[0114] The second type: reference Fig. 9, forming a bottom dielectric film (not shown) covering the sidewalls and bottom of the first groove 301, the sidewalls and bottom of the second groove 302 and the top surface of the substrate 100, and forming a top dielectric film (not shown) filling the first groove 301 and the second groove 302 and covering the bottom dielectric film (not shown). Etching and removing the bottom dielectric film (not shown) and the top dielectric film (not shown) higher than the top surface of the substrate 100, forming a bottom isolation layer 421 covering the sidewalls and bottom of the first groove 301, forming a top isolation layer 411 filling the first groove 301, and forming a bottom insulating layer 422 covering the sidewalls and bottom of the second groove 302, and a top insulating layer 412 filling the second groove 302. Further increasing the interface layer of the shallow trench isolation structure of the array area 101 and the peripheral area 102 through the multi-layer structure is conducive to improving the dielectric properties of the shallow trench isolation structure of the array area 101 and the peripheral area 102.

[0115] In one example, the bottom dielectric film (not shown) and the top dielectric film (not shown) are etched by chemical mechanical polishing. The bottom dielectric film (not shown) and the top dielectric film (not shown) are polished by chemical mechanical polishing. The chemical mechanical polishing method has a higher removal rate than the etching process, which is beneficial for shortening the process cycle.

[0116] The material of the bottom insulating layer 422 may be the same as that of the top insulating layer 412 , or may be different from that of the top insulating layer 412 . In the present embodiment, the material of the bottom insulating layer 422 is different from that of the top insulating layer 412 .

[0117] Specifically, the material of the bottom insulating layer 422 includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boronitride, silicon oxyboronitride or silicon carbide nitride. In this embodiment, the thickness of the bottom insulating layer 422 is 3nm to 5nm, specifically 3.5nm, 4.0nm or 4.5nm.

[0118] The third type: reference Fig.10Based on the second method, since the bottom isolation layer 421 and the bottom insulating layer 422 are formed to increase the aspect ratio of the first groove 301 and the second groove 302, the groove with a larger aspect ratio is easier to seal. The first sealing treatment is performed on the first groove 301 through a top dielectric film (not shown), and the second sealing treatment is performed on the second groove 302 to form a top isolation layer 411 and a top insulating layer 412. After the top isolation layer 411 and the top insulating layer 412 are formed, a first air gap 501 exists between the top isolation layer 411 and the bottom isolation layer 421 located in the first opening 311, and a second air gap 502 exists between the top insulating layer 412 and the bottom insulating layer 422. By forming the first insulating structure 401 having the first air gap 501 and the second insulating structure 402 having the second air gap 502, the dielectric properties of the shallow trench isolation structure in the array area 101 and the peripheral area are further improved.

[0119] Compared with the related art, a first insulating structure is formed in the peripheral area to fill the first groove in the first isolation structure, thereby preventing defects such as edge leakage from occurring in the shallow trench isolation structure in the peripheral area. In addition, a top isolation layer of the shallow trench isolation structure in the peripheral area is formed by a low dielectric constant material to improve the isolation effect of the shallow trench isolation structure in the peripheral area.

[0120] Since the first embodiment and the second embodiment correspond to each other with the present embodiment, the present embodiment can be implemented in conjunction with the first embodiment and the second embodiment. The relevant technical details mentioned in the first embodiment and the second embodiment are still valid in the present embodiment, and the technical effects that can be achieved in the first embodiment and the second embodiment can also be achieved in the present embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in the present embodiment can also be applied in the first embodiment and the second embodiment.

[0121] The above-mentioned various steps are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this patent. Adding insignificant modifications to the process or introducing insignificant designs that do not change the core design of the process are all within the protection scope of this patent.

[0122] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising an array region and a peripheral region, wherein the peripheral region has a first isolation structure, and the array region has a second isolation structure, wherein a top opening area of ​​the first isolation structure is greater than a top opening area of ​​the second isolation structure; The first isolation structure has a first groove therein, and a first insulating structure for filling the first groove; The first insulating structure at least comprises a top insulating layer, a top surface of the top insulating layer is flush with a top surface of the substrate, and the top insulating layer at least comprises a low dielectric constant material; Wherein, the peripheral region includes an isolation groove, the first isolation structure is used to fill the isolation groove, and the first isolation structure includes a first oxide layer, a barrier layer and a second oxide layer sequentially arranged on the sidewall of the isolation groove; The heights of the top surfaces of the first oxide layer and the second oxide layer are lower than the height of the top surface of the barrier layer; The first oxide layer, the barrier layer and the substrate form a first opening; The barrier layer and the second oxide layer form a second opening; The first opening and the second opening together form the first groove.

2. The semiconductor structure according to claim 1, characterized in that: The material of the top isolation layer includes at least one or more of silicon oxynitride, silicon oxycarbon nitride, silicon boron nitride, silicon oxyboron nitride or silicon carbide nitride.

3. The semiconductor structure according to any one of claims 1 to 2, characterized in that: The first insulating structure further includes a bottom isolation layer, wherein the bottom isolation layer is located on a top surface of the first groove and on a bottom surface of the top isolation layer.

4. The semiconductor structure according to claim 3, characterized in that: The bottom isolation layer and the top isolation layer are made of different materials, and a first air gap exists between the top isolation layer and the bottom isolation layer.

5. The semiconductor structure according to claim 1, characterized in that: The second isolation structure has a second groove therein, and a second insulating structure for filling the second groove; The second insulating structure at least includes a top insulating layer, a top surface of the top insulating layer is flush with a top surface of the substrate, and the top insulating layer at least includes a low dielectric constant material.

6. The semiconductor structure according to claim 5, characterized in that: The second insulating structure further includes a bottom insulating layer, wherein the bottom insulating layer is located on a top surface of the second groove and on a bottom surface of the top insulating layer.

7. The semiconductor structure according to claim 6, characterized in that: The bottom insulating layer and the top insulating layer are made of different materials, and a second air gap exists between the top insulating layer and the bottom insulating layer.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, the top opening area of ​​the first isolation structure being larger than the top opening area of ​​the second isolation structure; Removing a portion of the thickness of the first isolation structure to form a first groove in the peripheral area; forming a first insulating structure filling the first groove, wherein the first insulating structure comprises at least a top insulating layer, a top surface of the top insulating layer is flush with a top surface of the substrate, and the top insulating layer comprises at least a low dielectric constant material; Wherein, the peripheral region includes an isolation groove, the first isolation structure is used to fill the isolation groove, and the first isolation structure includes a first oxide layer, a barrier layer and a second oxide layer sequentially arranged on the sidewall of the isolation groove; The heights of the top surfaces of the first oxide layer and the second oxide layer are lower than the height of the top surface of the barrier layer; The first oxide layer, the barrier layer and the substrate form a first opening; The barrier layer and the second oxide layer form a second opening; The first opening and the second opening together form the first groove.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The forming of filling the first groove and the first insulating structure comprises: forming a bottom isolation layer covering the sidewalls and the bottom of the first groove; A top isolation layer filling the first groove is formed, wherein the top isolation layer and the bottom isolation layer together constitute the first insulating structure, and the top isolation layer and the bottom isolation layer are made of different materials.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The forming of a top isolation layer filling the first groove comprises: Performing a first sealing process on the first groove to form the top isolation layer; After the first sealing process is performed, a first air gap is formed between the top isolation layer and the bottom isolation layer.

11. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Also includes: Removing a portion of the thickness of the second isolation structure to form a second groove in the array area; A second insulating structure filling the second groove is formed, wherein the second insulating structure at least comprises a top insulating layer, a top surface of the top insulating layer is flush with a top surface of the substrate, and the top insulating layer at least comprises a low dielectric constant material.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The forming of filling the second groove and the second insulating structure comprises: forming a bottom insulating layer covering the second groove and the bottom; A top insulating layer filling the second groove is formed, wherein the top insulating layer and the bottom insulating layer together constitute the second insulating structure, and the top insulating layer and the bottom insulating layer are made of different materials.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The forming of a top insulating layer filling the second groove comprises: Performing a second sealing process on the second groove to form the top insulating layer; After the second sealing process is performed, a second air gap is formed between the top insulating layer and the bottom insulating layer.

14. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The step of removing a portion of the thickness of the second isolation structure to form a second groove in the array region and the step of removing a portion of the thickness of the first isolation structure to form a first groove in the peripheral region are performed simultaneously.

Images