Semiconductor device and switching power supply

Abstract

The application discloses a semiconductor device and a switching power supply. The semiconductor device comprises a first buried layer located in a first region of a substrate; a body region, a first well region, a drift region, and a second well region located on the first buried layer, the drift region being located between the first well region and the body region and being in contact with the body region, the second well region being a ring-shaped region and forming an isolation region with the first buried layer to surround the body region, the first well region, and the drift region; a third well region located in a second region of the substrate; and an isolation structure located in the second region of the substrate and between the second well region and the third well region, a part of the surface of the isolation structure being exposed outside the substrate and being suspended to block a leakage loop in the semiconductor device. The application uses the suspended isolation structure to achieve the purpose of blocking the leakage loop in the semiconductor device and improves the isolation effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and more particularly, to a semiconductor device and a switching power supply. BACKGROUND

[0002] Switching power supplies are widely used in various industries due to their high efficiency, low power consumption, high stability, wide voltage stabilization range, small size, and other advantages. Among them, the Buck (step-down)-boost (step-up) structure is often used in DC-DC (direct current to direct current) power supply chips because of its wider output voltage range. The output voltage of the Buck-boost switching power supply can be greater than the input voltage, or less than the input voltage and the output voltage and the input voltage are opposite in polarity.

[0003] In the dead time of the Buck-boost switching power supply, the transistor involved in the inductance discharge in the switching power supply will have a large current leakage, which is not conducive to the stability and reliability of the switching power supply. SUMMARY

[0004] The present application provides a semiconductor device and a switching power supply, which solves the problem of large current leakage of the semiconductor device and improves the stability and reliability of the switching power supply.

[0005] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0006] a substrate comprising a first region and a second region;

[0007] a first buried layer located in the first region of the substrate;

[0008] a body region, a first well region, a drift region, and a second well region located in the first region of the substrate and on the first buried layer, wherein the drift region is located between the first well region and the body region and is in contact with the body region, and the second well region is an annular region and forms an isolation region with the first buried layer to surround the body region, the first well region, and the drift region;

[0009] a third well region located in the second region of the substrate; and

[0010] an isolation structure located in the second region of the substrate and between the second well region and the third well region,

[0011] wherein part of the surface of the isolation structure is exposed outside the substrate and is suspended to block the leakage loop in the semiconductor device.

[0012] Optionally, the isolation structure is an annular region.

[0013] Optionally, the isolation structure comprises:

[0014] a fourth well region between the second well region and the third well region; and

[0015] a fifth well region between the fourth well region and the third well region, wherein the fourth well region is of a first doping type, the fifth well region is of a second doping type, and a first parasitic resistance is formed between the third well region and the fourth well region.

[0016] Optionally, further comprising:

[0017] a second buried layer in the substrate, and the fifth well region is on a surface of the second buried layer.

[0018] Optionally, further comprising:

[0019] a first doped region in the first well region, at least a part of a surface of the first doped region is exposed outside the substrate to contact a metal layer as a substrate terminal;

[0020] a second doped region in the second well region, at least a part of a surface of the second doped region is exposed outside the substrate, and the second doped region is grounded;

[0021] a third doped region in the third well region, at least a part of a surface of the third doped region is exposed outside the substrate, and the third doped region is grounded;

[0022] a drain region in the drift region, and at least a part of a surface of the drain region is exposed outside the substrate to contact a metal layer as a drain terminal;

[0023] a source region in the body region, and at least a part of a surface of the source region is exposed outside the substrate to contact a metal layer as a source terminal;

[0024] a gate region on a surface of the substrate and contacting a metal layer as a gate terminal, wherein a gate oxide layer is provided between the substrate and the gate region, and the gate region is on surfaces of the body region and the drift region,

[0025] wherein a first parasitic diode is formed between the fourth well region and the second well region, a second parasitic diode is formed between the second well region and the first well region, a third parasitic diode is formed between the first well region and the drift region, a first parasitic triode is formed between the fourth well region, the second well region and the first well region, a second parasitic triode is formed between the second well region, the first well region and the drain region, and a third parasitic triode is formed between the drain region, the body region and the source region,

[0026] The first well region, the third well region, the substrate and the body region are of a first doping type, and the drift region and the second well region are of a second doping type.

[0027] Optionally, the first well region has a width greater than that of the first doped region, and the second well region has a width greater than that of the second doped region, the width being in a direction towards the gate region.

[0028] Optionally, the semiconductor device further comprises:

[0029] The fourth doped region is located in the fourth well region, and at least part of a surface of the fourth doped region is exposed outside the substrate.

[0030] The fifth doped region is located in the fifth well region, and at least part of a surface of the fifth doped region is exposed outside the substrate, and the fifth doped region is short-circuited with the fourth doped region by a metal layer.

[0031] Optionally, the drain end is connected to the substrate end.

[0032] Optionally, the third well region is a ring-shaped region.

[0033] According to another aspect of the present application, a switching power supply is provided, comprising:

[0034] An inductor;

[0035] A capacitor connected between an output voltage and a ground end;

[0036] A main switch tube, which, when turned on, charges the inductor;

[0037] A synchronous switch tube, which, when turned on, discharges the inductor,

[0038] The synchronous switch tube is the semiconductor device described above.

[0039] The semiconductor device and the switching power supply provided by the present application use the suspended isolation structure to achieve the purpose of blocking the leakage loop in the semiconductor device, and improve the isolation effect of the semiconductor device. Further, through the parasitic resistance formed between the fourth well region and the third well region in the isolation structure, the parasitic thyristor circuit structure in the semiconductor device can be destroyed, thereby avoiding the thyristor from entering the latching state to form a leakage loop. In addition, when the above semiconductor device is used as a synchronous switch tube in the switching power supply, the parasitic thyristor in the synchronous switch tube will not enter the latching state in the dead time, thereby improving the stability and reliability of the switching power supply.

[0040] It should be noted that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A circuit schematic of a switching power supply is shown.

[0042] Figure 2 A cross-sectional schematic of a semiconductor device is shown.

[0043] Figure 3a A cross-sectional schematic of a semiconductor device is shown. Figure 2 A circuit schematic of a first leakage circuit of a semiconductor device is shown.

[0044] Figure 3b A circuit schematic of a second leakage circuit of a semiconductor device is shown. Figure 2 A circuit schematic of a second leakage circuit of a semiconductor device is shown.

[0045] Figure 4 A cross-sectional schematic of a semiconductor device is shown.

[0046] Figure 5a A cross-sectional schematic of a semiconductor device is shown. Figure 4 A circuit schematic of a first leakage circuit of a semiconductor device is shown.

[0047] Figure 5b A circuit schematic of a second leakage circuit of a semiconductor device is shown. Figure 4 A circuit schematic of a second leakage circuit of a semiconductor device is shown. DETAILED DESCRIPTION

[0048] For the purposes of this disclosure, reference will be made to the accompanying drawings which form a part of the disclosure. The drawings are schematic and schematic representations of preferred embodiments of the present disclosure, and are not limiting of the present disclosure. The present disclosure will be described with the understanding that the features of the present disclosure can be combined in any and all combinations, to provide numerous implementations of the present disclosure.

[0049] It should be understood that when a layer, region or element is referred to as being "on" or "above" another layer, region, or element, it can be directly on or above the other layer, region or element or intervening layers or regions can also be present. In addition, it should be understood that when a layer, region or element is referred to as being "under" or "below" another layer, region or element, it can be directly under or below the other layer, region or element or intervening layers or regions can also be present. Furthermore, relative terms such as "upwardly", "downwardly", "top", "bottom", "above", "below", "horizontal", "vertical", "left", "right", "forward", "backward", "clockwise", "counter clockwise" and the like are used herein for ease of description to describe the orientations of the devices or elements as shown in the figures. These relative terms are intended to encompass different orientations of the devices or elements in their operation or use.

[0050] Figure 1 A circuit schematic of a switching power supply is shown. Figure 2 A cross-sectional schematic of a semiconductor device is shown. Figure 3a A cross-sectional schematic of a semiconductor device is shown. Figure 2 A circuit schematic of a first leakage circuit of a semiconductor device is shown. Figure 3b A circuit schematic of a second leakage circuit of a semiconductor device is shown. Figure 2 A circuit schematic of a second leakage circuit of a semiconductor device is shown.

[0051] Referring toFigure 1 The switching power supply 100 comprises a main switch M1, a synchronous switch M2, an inductor L, and a capacitor C. The first end of the main switch M1 is connected to the positive end of a voltage source U to receive an input voltage VIN, the second end of the main switch M1 is connected to a first node LX, the first end of the inductor L is connected to the first node, and the second end of the inductor L is connected to the negative end of the voltage source U and a ground end. The second end of the synchronous switch M2 is connected to the first node LX, the first end of the synchronous switch M2 provides an output voltage VOUT and is connected to the first end of the capacitor C, and the second end of the capacitor is connected to the ground end and the second end of the inductor L. Further, the switching power supply 100 further comprises a resistor R, wherein the resistor R is connected in parallel with the capacitor C.

[0052] The control end of the main switch M1 receives a first control signal, and the control end of the synchronous switch M2 receives a second control signal. The main switch M1 and the synchronous switch M2 are alternately turned on by the first control signal and the second control signal to provide a stable output voltage VOUT. When the main switch M1 is turned on, a charging path is formed to charge the inductor L, and the current of the inductor L increases. When the synchronous switch M2 is turned on, a discharging path is formed to discharge the inductor L to obtain an output voltage VOUT with opposite polarity.

[0053] In order to avoid the main switch M1 and the synchronous switch M2 in the switching power supply 100 being turned on at the same time, a dead time is generally introduced when the first control signal and the second control signal are provided, so that the performance of the switching power supply 100 is more stable. The dead time refers to a period of time after one switch is turned off and before the other switch is turned on, that is, in the dead time, the main switch M1 and the synchronous switch M2 in the switching power supply 100 are both turned off.

[0054] Referring to Figure 2Fig. 2 shows a partial cross-sectional view of a synchronous switch tube M2. The semiconductor device (synchronous switch tube M2) 200 comprises a substrate 210, a buried layer 220 in the substrate 210, a drift region 231 on the upper surface of the buried layer 220 and in the substrate 210, a body region 232, a first well region 233, a second well region 234, a third well region 235 in the substrate 210, a gate region 246 on the upper surface of the substrate 210 and covering at least part of the body region 232. Further, the drift region 231 is in contact with the body region 232, and the drift region 231, the first well region 243, the second well region 244, the third well region 245 are each separated by a field oxide region 251, part of which is in the substrate 210 and part of which is exposed outside the substrate 210. The gate region 246 is provided with a gate oxide layer 252 between the drift region 231 and the body region 232. Further, the semiconductor device 200 comprises a drain region 241 in the drift region 231 and at least partially exposed outside, a source region 242 in the body region 232 and at least partially exposed outside, a first doped region 243 in the first well region 233 and at least partially exposed outside, a second doped region 244 in the second well region 234 and at least partially exposed outside, and a third doped region 245 in the third well region 235 and at least partially exposed outside, wherein the source region 242 is not in contact with the drain region 241. The gate region 246 exposed outside is in contact with a metal layer as a gate terminal G of the semiconductor device 200, the source region 242 exposed outside is in contact with a metal layer as a source terminal S of the semiconductor device 200, the drain region 241 exposed outside is in contact with a metal layer as a gate terminal G of the semiconductor device 200, the first doped region 243 exposed outside is in contact with a metal layer as a substrate terminal B of the semiconductor device 200, and the second doped region 244 exposed outside and the third doped region 245 exposed outside are each grounded as a ground terminal.

[0055] wherein the substrate 210, the body region 232, the first well region 233, the third well region 235, the first doped region 243, the third doped region 245 are of a first doping type, and the drift region 231, the second well region 234, the drain region 241, the second doped region 244 are of a second doping type. The source region 242 contains dopants of the first doping type and dopants of the second doping type, in particular, the source region 242 is doped with dopants of the first doping type on the side close to the drain region 241 and doped with dopants of the second doping type on the side away from the drain region 241.

[0056] Further, the first parasitic diode D1 is formed between the second well region 234 and the third well region 235, the second parasitic diode D2 is formed between the second well region 234 and the first well region 233, and the third parasitic diode D3 is formed between the first well region 233 and the drift region 231. The first parasitic transistor Q1 is formed between the first well region 233, the second well region 234 and the third well region 235, the second parasitic transistor Q2 is formed between the first well region 233, the second well region 234 and the drain region 241 in the drift region 231, and the third parasitic transistor Q3 is formed between the drain region 241 in the drift region 231, the body region 232 and the source region 242.

[0057] In combination Figure 1 The source end S of the synchronous switch tube M2 is connected with the substrate end B. When the main switch tube M1 is turned on and the inductor L is charged (the synchronous switch tube M2 is turned off) and when the synchronous switch tube M2 is turned on and the inductor L is discharged (the main switch tube M1 is turned off), the three parasitic diodes in the semiconductor device 200 are all in the reverse phase off state, and thus the latch-up effect will not be generated. During the dead time, the main switch tube M1 and the synchronous switch tube M2 are both turned off, at this time, the output voltage VOUT is greater than the voltage at the first node LX, that is, the voltage at the source end S (the substrate end B) of the semiconductor device 200 is greater than the voltage at the drain end D, and the third parasitic diode D3 is forward biased and turned on. Further, the emitter junction of the second parasitic transistor Q2 is forward biased and turned on, and the collector of the first parasitic transistor Q1 (current gain β1) provides the base current for the second parasitic transistor Q2 (current gain β2), and the collector of the second parasitic transistor Q2 provides the base current for the first parasitic transistor Q1, that is, the first parasitic transistor Q1 is turned on.

[0058] In combination Figure 3a The first drain current loop is formed between the ground end GND and the drain end D via the first parasitic transistor Q1, the second parasitic transistor Q2, the parasitic resistance R1 in the second well region 234, the parasitic resistance R2 in the first well region 233 and the third parasitic diode D3. During the dead time, the first drain current loop is turned on to form a positive feedback, and the latch-up effect is generated, in which the loop gain is β1*β2. The first drain current loop is a SCR (Silicon Controlled Rectifier) circuit. Figure 3bThe second leakage loop between the ground terminal GND and the source terminal S is formed via the first parasitic transistor Q1, the third parasitic transistor Q3, the parasitic resistance R1 in the second well region 234, and the parasitic resistance R2 in the first well region 233. During the dead time, the first leakage loop is turned on to form positive feedback, which in turn turns on the second leakage loop, so as to trigger the thyristor in the PNPN structure composed of the active region (the source region 242 and the drain region 241), the first well region 243, the second well region 244, and the third well region 245 in the semiconductor device 200 to enter the latching state. Since the thyristor will be always turned on once it enters the latching state, this will cause the existence of an ampere level of leakage current between the ground terminal and the drain terminal D and between the ground terminal and the source terminal S in the semiconductor device 200.

[0059] Figure 4 A cross-sectional view of a semiconductor device according to an embodiment of the present application is shown. Figure 5a A cross-sectional view of a semiconductor device according to an embodiment of the present application is shown. Figure 4 A circuit schematic diagram of a first leakage loop in a semiconductor device is shown. Figure 5b A circuit schematic diagram of a second leakage loop in a semiconductor device is shown. Figure 4 A circuit schematic diagram of a second leakage loop in a semiconductor device is shown.

[0060] Referring to Figure 4 The semiconductor device 200 (synchronous switch tube M2) includes a substrate 310, wherein the substrate 310 includes a first region 301 and a second region 302, a first buried layer 320 located in the first region 301 of the substrate 310, a body region 332, a drift region 331, a first well region 333, and a second well region 334 located on the upper surface of the first buried layer 320, a third well region 335 located in the second region 302 of the substrate 310, and an isolation structure 350. The first region 301 of the substrate 310 is located in the central part, and the second region 302 is located in the edge part and surrounds the first region 301.

[0061] Further, the drift region 331 is located between the first well region 333 and the body region 332 and is in contact with the body region 332. The second well region 334 is, for example, a ring-shaped region and forms an isolation region with the first buried layer 320 to surround the body region 332, the first well region 333, and the drift region 331, thereby playing an isolation role. That is, the semiconductor device 200 is a fully isolated transistor. In this embodiment, the semiconductor device 200 is taken as an example of NMOS for illustration.

[0062] Further, the isolation structure 350 is located between the second well region 334 and the third well region 335. Part of the surface of the isolation structure 350 is exposed outside the substrate 310 and suspended, so as to block a leakage loop in the semiconductor device 200. The leakage loop includes a first leakage loop between the drain terminal D and the ground terminal GND in the semiconductor device 200, and a second leakage loop between the source terminal S and the ground terminal GND in the semiconductor device 200.

[0063] Further, the isolation structure 350 is a ring-shaped region. Further, the third well region 335 is a ring-shaped region. The ring-shaped isolation structure 350 makes the isolation effect of the semiconductor device 300 better.

[0064] Further, the isolation structure 350 includes a fourth well region 351 and a fifth well region 352. The fourth well region 351 is located between the second well region 334 and the third well region 335. The fifth well region 352 is located between the fourth well region 351 and the third well region 334. The fourth well region 351 is of the first doping type, the fifth well region 352 is of the second doping type, and the third well region 335 is of the first doping type, so that a first parasitic resistance R3 is formed between the third well region 335 and the fourth well region 351. Further, the isolation structure 350 also includes a second buried layer 360 located in the second region 302 of the substrate 310, and the fifth well region 352 is located on the upper surface of the second buried layer 360.

[0065] The semiconductor device 300 also includes a drain region 341, a source region 342, a first doped region 343, a second doped region 344, a third doped region 345, a gate region 348, a field oxide region 381, and a gate oxide layer 382. The first doped region 343 is located in the first well region 333, and at least part of the surface of the first doped region 343 is exposed outside the substrate 310 to contact a metal layer as the substrate terminal B. The second doped region 344 is located in the second well region 334, and at least part of the surface of the second doped region 344 is exposed outside the substrate 310. The third doped region 345 is located in the third well region 335, and at least part of the surface of the third doped region 345 is exposed outside the substrate 310. The third doped region 345 is connected to the second doped region 344 and serves as the ground terminal GND. The drain region 341 is located in the drift region 331, and at least part of the surface of the drain region 341 is exposed outside the substrate 310 to contact a metal layer as the drain terminal D. The source region 342 is located in the body region 332, and at least part of the surface of the source region 342 is exposed outside the substrate 310 to contact a metal layer as the source terminal S. The gate region 348 is located on the surface of the substrate 310 and contacts a metal layer as the gate terminal G. The substrate 310 and the gate region 348 are provided with the gate oxide layer 382, and the gate region 348 is located on part of the surface of the body region 332 and the drift region 331.

[0066] Further, the fourth doped region 346 is located in the fourth well region 351, and at least part of the surface of the fourth doped region 346 is exposed outside the substrate 310. The fifth doped region 347 is located in the fifth well region 352, and at least part of the surface of the fifth doped region 347 is exposed outside the substrate 310. The fifth doped region 347 is short-circuited with the fourth doped region 346 through a metal layer (shown in the figure as a metal line, and generally can be connected through a metal layer), and the built-in electric field is used to achieve the purpose of blocking injection, so that the semiconductor device 300 can achieve better isolation effect.

[0067] Further, the field oxide region 381 is located between the third doped region 345 and the fifth doped region 347, between the fifth doped region 347 and the fourth doped region 346, between the fourth doped region 346 and the second doped region 344, between the second doped region 344 and the first doped region 343, between the first doped region 343 and the drain region 341, and between the source region 342 and the second doped region 344.

[0068] Further, the first parasitic diode D1 is formed between the fourth well region 351 and the second well region 334, the second parasitic diode D2 is formed between the second well region 334 and the first well region 333, the third parasitic diode D3 is formed between the first well region 333 and the drift region 331, the first parasitic transistor Q1 is formed between the fourth well region 351, the second well region 334 and the first well region 333, the second parasitic transistor Q2 is formed between the second well region 334, the first well region 331 and the drain region 341, and the third parasitic transistor Q3 is formed between the drain region 341, the body region 332 and the source region 342. The first well region 333, the third well region 335, the substrate 310 and the body region 332 are of a first doped type, and the drift region 331 and the second well region 334 are of a second doped type. Further, the first doped region 343, the third doped region 345 and the fourth doped region 346 are of the first doped type, and the second doped region 344, the drain region 341 and the fifth doped region 347 are of the second doped type. The source region 342 contains, for example, the dopants of the first doped type and the dopants of the second doped type. Specifically, for example, the side of the source region 342 close to the drain region 341 is doped with the dopants of the first doped type, and the side of the source region 342 away from the drain region 341 is doped with the dopants of the second doped type.

[0069] Further, the width of the first well region 333 is greater than the width of the first doped region 343, and the width of the second well region 334 is greater than the width of the second doped region 344, so as to reduce the β value in the first parasitic transistor Q1 and the second parasitic transistor Q2. In addition, the parasitic diode R2 in the first well region 333 and the parasitic diode R1 in the second well region 334 are also reduced. The direction of the width is the direction towards the gate region 348.

[0070] Further, the connection between the substrate end B and the source end S in the semiconductor device 300 can also work normally.

[0071] Referring to Figure 5a , a first leakage current loop between the ground end GND and the drain end D is formed via the first parasitic resistance R3, the first parasitic diode D1, the first parasitic transistor Q1, the second parasitic transistor Q2, the parasitic resistance R1 in the second well region 334, the parasitic resistance R2 in the first well region 333, and the third parasitic diode D3. During the dead time, the first parasitic resistance R3 in the suspended isolation structure 350 effectively reduces the emitter current of the first parasitic transistor Q1 and the collector current of the second parasitic transistor Q2. In addition, by widening the size of the first well region 333 and the second well region 334, the β value of the first parasitic transistor Q1 and the second parasitic transistor Q2 can be effectively reduced, so that the gain in the first leakage current loop can be reduced, and thus the collector current generated in the first parasitic transistor Q1 and the second parasitic transistor Q2 can be reduced. That is, the leakage current of the first leakage current loop is reduced due to the increased parasitic resistance R3 and the reduced gain of the first parasitic transistor Q1 and the second parasitic transistor Q2. Referring to Figure 5b , the parasitic resistance R3 breaks the second leakage current loop, so that the thyristor in the semiconductor device 300, which is composed of the PNPN structure of the active region (the source region 342 and the drain region 341), the first well region 343, the second well region 344, and the third well region 345, cannot be triggered into a latching state. Further, when the semiconductor device 300 is used as the synchronous switch tube M2, the parasitic thyristor inside the synchronous switch tube M2 cannot be triggered into a latching state during the dead time, and thus the stability and reliability of the switch power supply 100 can be improved.

[0072] It should be noted that the first doping type is, for example, P-type, and the second doping type is, for example, N-type.

[0073] It should be noted that in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0074] It should be noted that the above-mentioned embodiments are merely given as an example to illustrate the disclosure and should not be regarded as limiting the disclosed concept. Based on the above description, those skilled in the art can further make other variations and changes of the embodiments. Here, it is not necessary or possible to enumerate all the embodiments. The obvious variations and changes derived therefrom are still within the protection scope of the disclosure.

[0075] It should also be understood that the terms and expressions used herein are used as terms of description and not of limitation. There is no restriction on the use of equivalent and / or similar features to what are described or illustrated. Various modifications, changes, and variations can be made to the embodiments without departing from the spirit of the disclosure. Other modifications, changes, and substitutions are also possible. Accordingly, the claims should be viewed as covering all such equivalents and modifications.

Claims

1. A semiconductor device, wherein, The semiconductor device comprises: a substrate comprising a first region and a second region; a first buried layer in the first region of the substrate; a body region, a first well region, a drift region, and a second well region in the first region of the substrate and on the first buried layer, wherein the drift region is between the first well region and the body region and contacts the body region, and the second well region is a ring-shaped region and forms an isolation region with the first buried layer to enclose the body region, the first well region, and the drift region; a third well region in the second region of the substrate; and an isolation structure in the second region of the substrate and between the second well region and the third well region, wherein a part of the surface of the isolation structure is exposed outside the substrate and suspended to block a leakage loop in the semiconductor device, the isolation structure comprises: a fourth well region between the second well region and the third well region; and a fifth well region between the fourth well region and the third well region, wherein the fourth well region is of a first doping type, the fifth well region is of a second doping type, and a first parasitic resistance is formed between the third well region and the fourth well region. The first well region, the third well region, the substrate, and the body region are of the first doping type, and the drift region and the second well region are of the second doping type.

2. The semiconductor device of claim 1, wherein, The isolation structure is a ring-shaped region.

3. The semiconductor device of claim 1, wherein, Further comprising: a second buried layer in the substrate, and the fifth well region is on the surface of the second buried layer.

4. The semiconductor device of claim 1, wherein, Further comprising: a first doped region in the first well region, at least a part of the surface of the first doped region is exposed outside the substrate to contact a metal layer as a substrate terminal; a second doped region in the second well region, at least a part of the surface of the second doped region is exposed outside the substrate, and the second doped region is grounded; a third doped region in the third well region, at least a part of the surface of the third doped region is exposed outside the substrate, and the third doped region is grounded; a drain region in the drift region, and at least a part of the surface of the drain region is exposed outside the substrate to contact a metal layer as a drain terminal; a source region in the body region, and at least a part of the surface of the source region is exposed outside the substrate to contact a metal layer as a source terminal; a gate region on the surface of the substrate and contacting a metal layer as a gate terminal, wherein a gate oxide layer is provided between the substrate and the gate region, and the gate region is on the surface of the body region and the drift region. The fourth well region and the second well region form a first parasitic diode, the second well region and the first well region form a second parasitic diode, the first well region and the drift region form a third parasitic diode, the fourth well region, the second well region, and the first well region form a first parasitic triode, the second well region, the first well region, and the drain region form a second parasitic triode, and the drain region, the body region, and the source region form a third parasitic triode.

5. The semiconductor device of claim 4, wherein, The width of the first well region is greater than the width of the first doped region, the width of the second well region is greater than the width of the second doped region, and the direction of the width is the direction towards the gate region.

6. The semiconductor device of claim 1, wherein, Further comprising: a fourth doped region in the fourth well region, at least part of the surface of the fourth doped region being exposed outside the substrate; a fifth doped region in the fifth well region, at least part of the surface of the fifth doped region being exposed outside the substrate, and the fifth doped region being short-circuited with the fourth doped region by a metal layer.

7. The semiconductor device of claim 4, wherein, The drain terminal is connected with the substrate terminal.

8. The semiconductor device of claim 2, wherein, The third well region is a ring-shaped region.

9. A switching power supply, wherein, Comprising: an inductor; a capacitor connected between an output voltage and a ground terminal; a main switch tube, when turned on, the inductor is charged; a synchronous switch tube, when turned on, the inductor is discharged, wherein the synchronous switch tube is the semiconductor device of any one of claims 1-8.

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