Semiconductor devices

Abstract

A semiconductor device is provided that suppresses the reduction of the reverse bias safe operation area. A transistor diode is formed on a common semiconductor substrate, the semiconductor substrate having a transistor region, a diode region, and a peripheral region surrounding the transistor region and the diode region, the transistor region is divided into a plurality of transistor unit cell regions by a plurality of strip-shaped gate electrodes, the diode region is divided into a plurality of diode unit cell regions by a plurality of gate electrodes, the plurality of transistor unit cell regions having a third semiconductor layer of a first conductivity type provided on the first main surface side of the semiconductor substrate, a fourth semiconductor layer and a fifth semiconductor layer of a second conductivity type selectively provided on the upper layer portion of the third semiconductor layer, the fifth semiconductor layer being provided so as to contact with a first conductivity type impurity layer provided in the peripheral region or to intrude into the impurity layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with reduced recovery loss. Background Art

[0002] Generally, power devices are required to have the ability to withstand voltage and to ensure a safe operating area to prevent the device from being damaged during operation, one of which is to reduce losses. Reducing the loss of power devices has the effects of miniaturization and weight reduction of devices, and in a broad sense, has an effect related to the preservation of the global environment brought about by reduced energy consumption. In addition, power devices that achieve these effects are required to be realized at the lowest possible cost.

[0003] As a means for satisfying the above-mentioned requirements, for example, as disclosed in Non-Patent Document 1, a reverse-conducting IGBT (RC-IGBT) has been proposed that achieves the characteristics of an IGBT (Insulated Gate Bipolar Transistor) and a freewheeling diode (FWD) in one structure.

[0004] There are several technical problems with this RC-IGBT, one of which is that the recovery loss during diode operation is large. + Type contact layer and n - The pn junction formed by the drift layer becomes forward biased, and holes flow into the n - However, if the p-type impurity concentration in the anode region is high and there are a large number of excess carriers, it is difficult for the carriers inside the device to be discharged, and the recovery loss increases.

[0005] Some structures that solve these problems are disclosed in Patent Document 1. Patent Document 1 improves the recovery tolerance of the diode during operation by separating the guard ring in the outer peripheral region from the cathode layer by a fixed distance or more.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-224685

[0007] Non-patent literature 1: Proceedings of International symposium on Power Semiconductor devices 2004 pp.133-136

[0008] Patent Document 1 discloses that no countermeasures are taken against hole inflow from the peripheral region which is generally a high-concentration and deep p-type diffusion layer, and countermeasures against reduction of the reverse bias safe operating area (RBSOA) are insufficient. Summary of the invention

[0009] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which a reduction in a reverse bias safe operation region is suppressed.

[0010] The semiconductor device of the present invention forms a transistor and a diode on a common semiconductor substrate. In the semiconductor device, the semiconductor substrate has: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and a peripheral region surrounding a unit region including the transistor region and the diode region, wherein the transistor region is divided into a plurality of transistor unit regions by a plurality of strip-shaped gate electrodes, and the diode region is divided into a plurality of diode unit regions by the plurality of gate electrodes, and the plurality of transistor unit regions have: a first semiconductor layer of a first conductivity type, which is arranged on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is arranged on the first semiconductor layer; a third semiconductor layer of a first conductivity type, which is arranged on the first main surface side of the semiconductor substrate compared with the second semiconductor layer; a fourth semiconductor layer of a second conductivity type, which is selectively arranged on the upper layer of the third semiconductor layer; and a fifth semiconductor layer of a first conductivity type, which is selectively arranged in a manner that the side surface of the fifth semiconductor layer is in contact with the fourth semiconductor layer. The present invention relates to a method for producing a semiconductor device for producing a light emitting diode (LED) unit cell region comprising: a sixth semiconductor layer of the second conductivity type, which is arranged on the second main surface side of the semiconductor substrate; the second semiconductor layer, which is arranged on the sixth semiconductor layer; a seventh semiconductor layer of the first conductivity type, which is arranged on the first main surface side of the semiconductor substrate compared with the second semiconductor layer; an eighth semiconductor layer of the first conductivity type, which is selectively arranged on the upper layer of the seventh semiconductor layer; the first electrode, which is electrically connected to the sixth semiconductor layer; and the second electrode, which is electrically connected to the seventh semiconductor layer and the eighth semiconductor layer via the contact hole, the fifth semiconductor layer of the transistor region is arranged to contact with the first conductivity type impurity layer arranged in the peripheral region and defining the boundary with the unit region, or to intrude into the impurity layer, and the contact hole is arranged to extend to the upper part of the impurity layer in the peripheral region.

[0011] Effects of the Invention

[0012] According to the semiconductor device of the present invention, since the fifth semiconductor layer is arranged to contact with the impurity layer arranged in the peripheral region or to penetrate into the impurity layer, the fourth semiconductor layer is not arranged near the diode region, so that a latch-up is difficult to perform, and even if the inflow of hole current increases, the potential is difficult to increase, the inflow of hole current into the fourth semiconductor layer is reduced, and the reduction of the reverse bias safe operation area can be minimized. In addition, since the contact hole extends to the upper part of the impurity layer in the peripheral region, holes can be effectively discharged even in the peripheral region near the transistor region, and the reduction of the reverse bias safe operation area can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a plan view showing the entire chip of the RC-IGBT according to the first embodiment.

[0014] Figure 2 This is a partial top view of the RC-IGBT according to the first embodiment.

[0015] Figure 3 This is a partial cross-sectional view of the RC-IGBT according to the first embodiment.

[0016] Figure 4 This is a partial cross-sectional view of the RC-IGBT according to the first embodiment.

[0017] Figure 5 This is a partial cross-sectional view of the RC-IGBT according to the first embodiment.

[0018] Figure 6 This is a partial cross-sectional view of the RC-IGBT according to the first embodiment.

[0019] Figure 7 It is a partial top view of the RC-IGBT according to the second embodiment.

[0020] Figure 8 It is a partial cross-sectional view of the RC-IGBT according to the second embodiment.

[0021] Fig. 9 It is a partial cross-sectional view of the RC-IGBT according to the second embodiment.

[0022] Fig.10 It is a partial cross-sectional view of the RC-IGBT according to the second embodiment.

[0023] Fig.11 It is a partial cross-sectional view of the RC-IGBT according to the second embodiment.

[0024] Fig.12 It is a partial top view of the RC-IGBT according to the third embodiment.

[0025] Fig.13 It is a partial cross-sectional view of the RC-IGBT according to the third embodiment.

[0026] Fig.14 It is a partial cross-sectional view of the RC-IGBT according to the third embodiment.

[0027] Fig.15 It is a partial cross-sectional view of the RC-IGBT according to the third embodiment.

[0028] Fig.16 It is a partial cross-sectional view of the RC-IGBT according to the third embodiment.

[0029] Fig.17 It is a partial top view of the RC-IGBT according to the fourth embodiment.

[0030] Fig.18 It is a partial cross-sectional view of the RC-IGBT according to the fourth embodiment.

[0031] Fig.19 It is a partial cross-sectional view of the RC-IGBT according to the fourth embodiment.

[0032] Fig. 20 It is a partial cross-sectional view of the RC-IGBT according to the fourth embodiment.

[0033] Fig.21 It is a partial cross-sectional view of the RC-IGBT according to the fourth embodiment.

[0034] Fig. 22 It is a partial top view of the RC-IGBT according to the fifth embodiment.

[0035] Fig.23 It is a partial cross-sectional view of the RC-IGBT according to the fifth embodiment.

[0036] Fig.24 It is a partial cross-sectional view of the RC-IGBT according to the fifth embodiment.

[0037] Fig.25 It is a partial cross-sectional view of the RC-IGBT according to the fifth embodiment.

[0038] Fig.26 It is a partial cross-sectional view of the RC-IGBT according to the fifth embodiment.

[0039] Fig. 27 It is a partial top view of the RC-IGBT according to the sixth embodiment.

[0040] Fig.28 It is a partial cross-sectional view of the RC-IGBT according to the sixth embodiment.

[0041] Fig.29 It is a partial cross-sectional view of the RC-IGBT according to the sixth embodiment.

[0042] Fig.30 It is a partial cross-sectional view of the RC-IGBT according to the sixth embodiment.

[0043] Fig.31 It is a partial cross-sectional view of the RC-IGBT according to the sixth embodiment.

[0044] Fig.32 It is a partial top view of the RC-IGBT according to the seventh embodiment.

[0045] Fig.33 It is a partial cross-sectional view of the RC-IGBT according to the seventh embodiment.

[0046] Fig.34 It is a partial cross-sectional view of the RC-IGBT according to the seventh embodiment.

[0047] Fig.35 It is a partial cross-sectional view of the RC-IGBT according to the seventh embodiment.

[0048] Fig.36 It is a partial cross-sectional view of the RC-IGBT according to the seventh embodiment.

[0049] Fig.37 It is a partial top view of the RC-IGBT according to the eighth embodiment.

[0050] Fig.38 It is a partial cross-sectional view of the RC-IGBT according to the eighth embodiment.

[0051] Fig.39 It is a partial cross-sectional view of the RC-IGBT according to the eighth embodiment.

[0052] Fig.40 It is a partial cross-sectional view of the RC-IGBT according to the eighth embodiment.

[0053] Fig.41 It is a partial cross-sectional view of the RC-IGBT according to the eighth embodiment.

[0054] Fig.42 It is a partial top view of the RC-IGBT according to the ninth embodiment.

[0055] Fig.43 It is a partial cross-sectional view of the RC-IGBT according to the ninth embodiment.

[0056] Fig.44 It is a partial cross-sectional view of the RC-IGBT according to the ninth embodiment.

[0057] Fig.45 It is a partial cross-sectional view of the RC-IGBT according to the ninth embodiment.

[0058] Fig.46 It is a partial cross-sectional view of the RC-IGBT according to the ninth embodiment.

[0059] Fig.47 It is a partial top view of the RC-IGBT involved in the tenth embodiment.

[0060] Fig.48 This is a partial cross-sectional view of the RC-IGBT according to the tenth embodiment.

[0061] Fig.49 This is a partial cross-sectional view of the RC-IGBT according to the tenth embodiment.

[0062] Fig.50 This is a partial cross-sectional view of the RC-IGBT according to the tenth embodiment.

[0063] Fig.51 This is a partial cross-sectional view of the RC-IGBT according to the tenth embodiment.

[0064] Fig.52 It is a partial top view of the RC-IGBT involved in the eleventh embodiment.

[0065] Fig.53 This is a partial cross-sectional view of the RC-IGBT according to the eleventh embodiment.

[0066] Fig.54 This is a partial cross-sectional view of the RC-IGBT according to the eleventh embodiment.

[0067] Fig.55 This is a partial cross-sectional view of the RC-IGBT according to the eleventh embodiment.

[0068] Fig.56 This is a partial cross-sectional view of the RC-IGBT according to the eleventh embodiment.

[0069] Fig.57 It is a partial cross-sectional view of the RC-IGBT according to the eleventh embodiment.

[0070] Fig.58 It is a partial top view of the RC-IGBT involved in the twelfth embodiment.

[0071] Fig.59 This is a partial cross-sectional view of the RC-IGBT according to the twelfth embodiment.

[0072] Fig.60 This is a partial cross-sectional view of the RC-IGBT according to the twelfth embodiment.

[0073] Fig.61 This is a partial cross-sectional view of the RC-IGBT according to the twelfth embodiment.

[0074] Fig.62 This is a partial cross-sectional view of the RC-IGBT according to the twelfth embodiment.

[0075] Fig.63 It is a top view showing another structure of the RC-IGBT.

[0076] Fig.64 It is a top view showing another structure of the RC-IGBT.

[0077] Fig.65 It is a partial top view showing another structure of the RC-IGBT.

[0078] Fig.66 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0079] Fig.67 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0080] Fig.68 It is a partial top view showing another structure of the RC-IGBT.

[0081] Fig.69 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0082] Fig.70 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0083] Fig.71 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0084] Fig.72 It is a partial cross-sectional view showing another structure of the RC-IGBT.

[0085] Fig.73 It is a partial cross-sectional view showing another structure of the RC-IGBT. DETAILED DESCRIPTION

[0086] <First>

[0087] In the following description, n-type and p-type represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type may be n-type and the second conductivity type may be p-type. - Type indicates that the impurity concentration is lower than that of n-type. + The n-type indicates a higher impurity concentration than the n-type.- Type means that the impurity concentration is lower than that of p-type. + Type indicates a concentration where the impurity concentration is higher than that of the p-type.

[0088] In addition, the drawings are only schematic representations, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily accurately recorded and can be appropriately changed. In addition, in the following description, the same structural elements are marked with the same reference numerals and illustrated, and their names and functions are also set to be the same. Therefore, their detailed description may be omitted in some cases.

[0089] In addition, in the following description, terms such as "up", "down", "side", "front" and "back" are sometimes used to indicate specific positions and directions. These terms are used for convenience only to facilitate understanding of the contents of the implementation method and have nothing to do with the direction during actual implementation.

[0090] <Implementation Method 1>

[0091] <Device Structure>

[0092] Figure 1 is a plan view showing the entire chip of the RC-IGBT 100 according to the first embodiment, Figure 2 Yes means Figure 1 A top view of the area X surrounded by the dotted line in FIG. Figure 1 The RC-IGBT 100 shown is configured such that an IGBT region 101 (transistor region) and a FWD region 102 (diode region) are arranged in a stripe shape, and is referred to as a “stripe type”.

[0093] like Figure 1 As shown, the peripheral region 103 is provided to surround the IGBT region 101 and the FWD region 102, and the gate pad region 104 is provided in part of the IGBT region 101. The same is true for the top views showing the entire chip in the RC-IGBTs 200 to 1200 of the second to twelfth embodiments described later.

[0094] like Figure 2 As shown, the IGBT region 101 is divided into a plurality of IGBT unit cell regions 105 (transistor unit cell regions) by a plurality of strip-shaped buried gate electrodes 8 having a trench structure. Similarly, the FWD region 102 is divided into a plurality of FWD unit cell regions 106 (diode unit cell regions) by the buried gate electrodes 8. In addition, the IGBT region 101 and the FWD region 102 are collectively referred to as a unit region.

[0095] The IGBT unit cell region 105 is arranged so as to sandwich the buried gate electrode 8, and is repeated in the X direction (horizontal direction) in which the buried gate electrode 8 is arranged, and a contact hole 15 is provided in each IGBT unit cell region 105. The contact hole 15 is provided not only to reach the IGBT unit cell region 105, but also to reach the p-type well layer 16 (impurity layer) of the peripheral region 103. This is referred to as the second feature of the first embodiment.

[0096] In the IGBT unit cell region 105, n+ type emitter layers 3 (fourth semiconductor layers) and p+ type emitter layers 3 (fourth semiconductor layers) are alternately formed in the Y direction (vertical direction) in which the buried gate electrode 8 extends. + Type contact layer 4 (fifth semiconductor layer).

[0097] In the IGBT unit cell region 105, a p-type well layer 16 is provided at the boundary with the p-type well layer 16 of the peripheral region 103. + Type contact layer 4 is constructed in a manner such that p + The p-type contact layer 4 is connected to the p-type well layer 16 .

[0098] The FWD unit cell region 106 is arranged to sandwich the buried gate electrode 8 and repeat in the X direction (horizontal direction) in which the buried gate electrode 8 is arranged. Each FWD unit cell region 106 has a p-type anode layer 5 (seventh semiconductor layer) and a strip-shaped p-type semiconductor layer extending in the Y direction. + Type contact layer 6 (eighth semiconductor layer), p + The type contact layer 6 is formed in a continuous line shape extending in parallel with the buried gate electrode 8. This is referred to as the fourth feature of the first embodiment.

[0099] In addition, in the entire FWD region 102, p + The p-type contact layer 6 is set to have a lower area ratio than the p-type anode layer 5. Here, the area ratio refers to the area ratio relative to the p + The area ratio of the total area of ​​the p-type contact layer 6 and the p-type anode layer 5 in a plan view is referred to as the fifth feature of the first embodiment.

[0100] In addition, the p in the FWD region 102 + The p-type contact layer 6 is set to have an area ratio greater than that of the p-type contact layer 6 in the IGBT region 101. + The type contact layer 4 is low. This is referred to as the sixth feature of the first embodiment.

[0101] In addition, a contact hole 15 is provided so as to straddle a plurality of FWD unit cell regions 106. + The p-type contact layer 6 is provided so that the end of the outer peripheral region 103 is adjacent to the p-type contact layer 6. +Compared with the end portion of the outer peripheral region 103 side of the type contact layer 4, it is located at a position away from the outer peripheral region 103. This is referred to as the third feature of the first embodiment.

[0102] Figure 3 Show Figure 2 The arrow-directed cross-sectional view at line AA is shown. Figure 4 The arrow-directed cross-sectional view at line BB is shown. Figure 5 The arrow-directed cross-sectional view at line CC is shown. Figure 6 A cross-sectional view in the direction of arrows at line DD is shown.

[0103] like Figure 3 to Figure 6 As shown, the RC-IGBT 100 has an n-type semiconductor substrate such as a silicon (Si) substrate. - Type drift layer 1 (second semiconductor layer). - The drift layer 1 has, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 .

[0104] The semiconductor substrate in the IGBT region 101 is formed from n + Type emitter layer 3 and p + The range from the p-type contact layer 4 to the p-type collector layer 11 (first semiconductor layer) in the FWD region 102 is from the p + Type contact layer 6 to n + The range extends to the type cathode layer 12 (sixth semiconductor layer).

[0105] exist Figure 3 to Figure 6 In the example, n of the IGBT region 101 is + Type emitter layer 3 and p + The upper end of the p-type contact layer 4 on the paper is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 11 on the paper is referred to as the second main surface of the semiconductor substrate. Figure 3 ~ Figure 6 In the FWD region 102, the p + The upper end of the paper surface of the type contact layer 6 is called the first main surface of the semiconductor substrate. + The lower end of the cathode layer 12 is called the second main surface of the semiconductor substrate. The first main surface of the FWD region 102 is the same as the first main surface of the IGBT region 101, and the second main surface of the FWD region 102 is the same as the second main surface of the IGBT region 101.

[0106] like Figure 3 to Figure 6 As shown, in the IGBT region 101, at n -A p-type channel doped layer 2 (third semiconductor layer) is provided on the first main surface side of the p-type drift layer 1. In the FWD region 102, the p-type channel doped layer 2 (third semiconductor layer) is provided on the first main surface side of the p-type drift layer 1. - A p-type anode layer 5 is provided on the first main surface side of the type drift layer 1. This is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 .

[0107] exist Figure 3 In the embodiment, an n-type channel doped layer 2 is provided on the first main surface side thereof so as to be in contact with the gate insulating film 7 in which the gate electrode 8 is buried. + Type emitter layer 3, in Figure 4 In the example, p is set + Type contact layer 4. + Type emitter layer 3 and p + The type contact layer 4 constitutes the first main surface of the semiconductor substrate.

[0108] n + The emitter layer 3 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 .

[0109] p + The contact layer 4 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 .

[0110] In addition, if Figure 3 to Figure 6 As shown, RC-IGBT 100 is - The second main surface of the type drift layer 1 is provided with an n-type impurity having a concentration ratio n - The n-type buffer layer 10 is provided to suppress the breakdown of the depletion layer extending from the p-type channel doping layer 2 to the second main surface when the RC-IGBT 100 is turned off. The n-type buffer layer 10 may be, for example, a layer of phosphorus (P) or protons (H + ) or by implanting phosphorus (P) or protons (H + ) are formed by the two. The concentration of n-type impurities in the n-type buffer layer 10 is 1.0×10 12 / cm 3~1.0×10 18 / cm 3 .

[0111] In addition, if Figure 3 to Figure 6 As shown in FIG. 1 , a collector electrode 14 (first electrode) is provided on the first main surface of the IGBT region 101 and the FWD region 102. The collector electrode 14 functions as a cathode electrode in the FWD region 102. On the collector electrode 14, a p-type collector layer 11 is provided in the IGBT region 101, and an n-type collector layer 12 is provided in the FWD region 102. + Type cathode layer 12.

[0112] The p-type collector layer 11 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 .

[0113] n + The cathode layer 12 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3 .

[0114] In addition, if Figure 5 As shown, in the peripheral area 103, at n - A p-type well layer 16 is provided on the first main surface side of the IGBT region 101 and the FWD region 102. The p-type well layer 16 is provided to surround the IGBT region 101 and the FWD region 102, and has, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and is in contact with the side surface of the p-type channel doping layer 2 of the IGBT region 101. + The p-type contact layer 4 is formed to intrude into the p-type well layer 16, and the p-type channel doping layer 2 and the n + The p-type emitter layer 3 does not intrude into the p-type well layer 16 . This is referred to as the first feature of Embodiment 1. The upper end of the p-type well layer 16 on paper is the first main surface of the semiconductor substrate, and an interlayer insulating film 9 is provided on the p-type well layer 16 .

[0115] Although not shown in the figure, an FLR (Field Limiting Ring) in which a cell region is surrounded by a p-type well layer (end well layer) or a VLD (Variation of Lateral Doping) in which a cell region is surrounded by a p-type well layer having a concentration gradient can be provided at the outer periphery of the p-type well layer 16. The number of annular p-type well layers used by the FLR and the concentration distribution of the p-type well layers used by the VLD can be appropriately selected according to the withstand voltage design of the RC-IGBT 100.

[0116] In addition, if Figure 3 and Figure 4 As shown, in the IGBT region 101, a channel doping layer is formed from the first main surface of the semiconductor substrate through the p-type channel doping layer 2 to the n-type channel doping layer 2. - The type drift layer 1 has a trench, and a buried gate electrode 8 is provided in the trench via a gate insulating film 7. The gate insulating film 7 and the buried gate electrode 8 are covered by an interlayer insulating film 9, and the buried gate electrode 8 is a structure that is not connected to the emitter electrode 13 (second electrode). In addition, the buried gate electrode 8 in the IGBT region 101 is formed inside the IGBT region 101, and is electrically connected to the gate pad region 104 via a gate wiring (not shown), and functions as an active trench gate.

[0117] In addition, if Figure 3 and Figure 4 As shown, in the FWD region 102, a channel doping layer is formed which penetrates the p-type channel doping layer 2 from the first main surface of the semiconductor substrate to the n-type channel doping layer 2. - A trench of the type drift layer 1 is formed, and a buried gate electrode 8 is provided in the trench via a gate insulating film 7. The gate insulating film 7 and the buried gate electrode 8 in the FWD region 102 are connected to the emitter electrode 13, and the buried gate electrode 8 functions as a dummy trench gate.

[0118] In addition, if Figure 3 to Figure 6 As shown in FIG. 1 , a barrier metal 18 is formed on the first main surface of the semiconductor substrate in an area where the interlayer insulating film 9 is not provided and on the interlayer insulating film 9. The barrier metal 18 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and Si. Figure 3 As shown, the barrier metal 18 and n + Type emitter layer 3, p + The type contact layer 6 and the buried gate electrode 8 in the FWD region 102 make ohmic contact with the n + Type emitter layer 3, p +The type contact layer 6 and the buried gate electrode 8 in the FWD region 102 are electrically connected. An emitter electrode 13 is provided on the barrier metal 18. The emitter electrode 13 may be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode composed of a multilayer metal film formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The plated film formed by chemical plating or electroplating may be, for example, a nickel (Ni) plated film.

[0119] Figure 1 The gate pad region 104 shown is connected to the gate wiring formed inside the IGBT region 101, and an oxide film is formed directly below the gate pad region 104, so that the gate pad region 104 and the emitter electrode 13 are electrically separated. In addition, directly below the oxide film, n - A p-type drift layer 1 may be provided as well as a p-type end well layer.

[0120] The manufacturing method of the RC-IGBT 100 of the first embodiment described above can be manufactured using a common IGBT manufacturing technology by changing the mask pattern during photolithography and the configuration pattern of the impurity layers in the IGBT region 101 and the FWD region 102 , so a detailed description is omitted.

[0121] <Action>

[0122] The operation of the RC-IGBT 100 will be described. First, the operation of the RC-IGBT 100 as an IGBT will be described. The on-state of the IGBT is achieved by applying a positive voltage to the buried gate electrode 8. - type drift layer 1, p-type channel doping layer 2, n + The n-channel MOSFET composed of the n-type emitter layer 3, the gate insulating film 7 and the buried gate electrode 8 is turned on. + The type emitter layer 3 injects electrons from the p + The holes flow into the collector layer 11, and the - The conductivity of the drift layer 1 is modulated, thereby reducing the voltage between the emitter and the collector, thereby realizing the on-state of the IGBT.

[0123] The off state of the IGBT is realized by applying a negative voltage to the buried gate electrode 8. That is, when the n-channel MOSFET is turned off, the voltage accumulated in the n-channel MOSFET is - The minority carriers of the drift layer 1 are discharged from the emitter electrode 13 and the collector electrode 14, n - The drift layer 1 is gradually depleted. By sharing the voltage in the depleted region, the voltage between the emitter and the collector increases, achieving the off state.

[0124] Next, the operation of the RC-IGBT 100 as a diode will be described. + Type contact layer 6, n - Type drift layer 1 and n + The p-type cathode layer 12 forms a diode structure. The on state during FWD operation is when the paired IGBT is in the off state. When a positive voltage is applied to the emitter electrode 13 relative to the collector electrode 14, the p-type anode layer 5 and the p-type cathode layer 12 form a diode structure. + The holes flow into the anode region formed by the n-type contact layer 6, + Electrons flow into the cathode region formed by the type cathode layer 12, causing conductivity modulation, and the diode enters the on state.

[0125] Next, when the paired IGBTs are turned on, a negative voltage is applied to the emitter electrode 13 relative to the collector electrode 14, and the p-type anode layer 5 and the p-type anode layer 5 are connected. + The type contact layer 6 releases n - The holes in the drift layer 1 are transferred from n + The p-type cathode layer 12 releases electrons to the collector electrode. However, the excess carriers near the anode region disappear, and the p-type anode layer 5 and the p-type cathode layer 12 release electrons to the collector electrode. + Type contact layer 6 and n - The current continues to flow until the pn junction formed by the type drift layer 1 becomes reverse biased.

[0126] Furthermore, if the excess carriers near the anode region are released, the p-type anode layer 5 and the p + Type contact layer 6 and n - The pn junction formed by the drift layer 1 becomes reverse biased, and the reverse recovery current begins to decrease. - When the excess carriers in the drift layer 1 are discharged, the recovery process is completed and the circuit breaker state is reached.

[0127] In the RC-IGBT 100, a FWD region 102 is formed adjacent to the IGBT region 101. When the IGBT is operating, holes diffuse from the p + The type collector layer 11 flows not only into the IGBT region 101 but also into the FWD region 102 . Therefore, when the IGBT is turned off during operation, holes that have flowed into a part of the FWD region 102 other than the IGBT region 101 are discharged from the emitter electrode 13 .

[0128] Therefore, the hole current is concentrated in the IGBT region 101 near the FWD region 102, and the potential of the p-type channel doping layer 2 becomes high. + Type emitter layer 3 and n +The p-type emitter layer 3 forms a pn junction. The p-type channel doping layer 2 applies a voltage to eliminate the built-in potential. + type emitter layer 3, p-type channel doping layer 2, n - Type drift layer 1 and p + The thyristor formed by the collector layer 11 is turned on, and the control by the gate electrode cannot be performed, which may cause the state device to be damaged in some cases. This situation is called a reduction in the reverse bias safe operating area (RBSOA). In addition, since the peripheral area 103 also contains hole components diffused to the peripheral part, it becomes a situation that may further cause a reduction in RBSOA.

[0129] However, in the RC-IGBT 100 , since it has the first feature, the second feature, and the third feature described above, it is possible to suppress a decrease in the reverse bias safe operation region during the operation of the IGBT.

[0130] The first feature is that the p of the IGBT region 101 + The p-type contact layer 4 is formed to intrude into the p-type well layer 16, and the p-type channel doping layer 2 and the n + The p-type emitter layer 3 does not intrude into the p-type well layer 16 .

[0131] Therefore, no n is configured near the FWD region 102. + The p-type emitter layer 3 is formed so as to be difficult to latch, and the p-type emitter layer 3 is formed so as to invade the p-type well layer 16. + Type contact layer 4, thus with n + The p-type emitter layer 3 forms a p-type impurity layer of a pn junction, in this case, a p-type well layer 16 and a p + The portion overlapping the n-type contact layer 4 has a low resistance. Therefore, even if the inflow of hole current increases, the potential is difficult to increase, and the hole current flows to the n-type contact layer 4. + The inflow of the type emitter layer 3 is reduced, and the reduction in the reverse bias safe operating area (RBSOA) can be minimized.

[0132] The second feature is that the contact hole 15 of the IGBT region 101 is provided not only to reach onto the IGBT unit cell region 105 but also to reach onto the p-type well layer 16 of the peripheral region 103 .

[0133] Therefore, holes can be effectively discharged also in the outer peripheral region 103 near the IGBT region 101 , and a decrease in RBSOA can be suppressed.

[0134] The third characteristic is that p + The end of the outer peripheral region 103 side of the type contact layer 6 is set to be connected to the p +Compared with the end portion of the type contact layer 4 on the outer peripheral region 103 side, it is located away from the outer peripheral region 103 .

[0135] Therefore, since the p-type impurity concentration at the boundary between the FWD region 102 and the peripheral region 103 is reduced, the hole discharge path is reduced, so that the reduction of RBSOA at the boundary between the IGBT region 101 and the FWD region 102 and the peripheral region 103 can be suppressed.

[0136] In addition, as the first feature, p + The structure in which the p-type contact layer 4 intrudes into the p-type well layer 16 is shown in FIG. + The effect of the first feature can also be obtained when the p-type contact layer 4 is in contact with the p-type well layer 16. In addition, since the third, fifth, and sixth features described above are provided, the recovery loss during the FWD operation can be reduced.

[0137] The third characteristic is that p + The end of the outer peripheral region 103 side of the type contact layer 6 is set to be connected to the p + By locating the end of the p-type contact layer 4 on the peripheral region 103 side at a position farther from the peripheral region 103 , the average concentration of p-type impurities in the anode region of the FWD region 102 can be reduced, thereby reducing recovery loss.

[0138] The fifth feature is that the p of the entire FWD region 102 is + The area ratio of the p-type contact layer 6 is set lower than the area ratio of the p-type anode layer 5 , thereby making it possible to further reduce the recovery loss.

[0139] The sixth feature is that the p in the FWD region 102 + The area ratio of the p-type contact layer 6 is set to be larger than that of the p-type contact layer 6 in the IGBT region 101. + The area ratio of the type contact layer 4 is low, thereby reducing the excess carrier concentration at the boundary with the IGBT region 101 and reducing the recovery loss during the FWD operation.

[0140] In addition, according to the fourth feature described above, by setting p + The p-type contact layer 6 is formed as a continuous line extending side by side with the buried gate electrode 8, so the pattern size becomes larger, the dimensional fluctuation during manufacturing can be suppressed, and the contact width is stabilized. As a result, the p-type impurity concentration in the anode region of the FWD region 102 can be stabilized, and the recovery characteristics can be stably improved.

[0141] <Implementation Method 2>

[0142] Next, use Figure 7 to Figure 10The RC-IGBT 200 according to the second embodiment will be described. Figure 1 same, Figure 7 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Figure 8 Show Figure 7 The arrow-directed cross-sectional view at line AA is shown. Fig. 9 The arrow-directed cross-sectional view at line BB is shown. Fig.10 The arrow-directed cross-sectional view at line CC is shown. Fig.11 The arrow direction cross-sectional view at line DD is shown. Figure 7 to Figure 10 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0143] like Figure 7 As shown, in the RC-IGBT 200, in the FWD unit cell region 106 which is a part of the FWD region 102, p + The p-type contact layer 6 is formed to have a length that is connected to the p-type well layer 16 in the peripheral region 103. Figure 7 As shown in FIG. 1 , the p of the FWD unit cell region 106 adjacent to the IGBT region 101 + The p-type contact layer 6 is formed larger than other p + The p-type contact layer 6 is long and the end thereof is connected to the p-type well layer 16, but the present invention is not limited thereto. In the plurality of FWD unit cell regions 106, the p + The p-type contact layer 6 may be formed to have a length sufficient to connect to the p-type well layer 16 in the outer peripheral region 103 .

[0144] In the case of a structure that supports low-speed operation with low carrier frequency, it is required to set the collector-emitter voltage drop (VCEsat) of the IGBT and the forward voltage drop (VF) of the diode relatively low. + The conductivity modulation in the on state is improved by increasing the impurity concentration of the p-type collector layer 11 and the p-type anode layer 5. In this case, as described in the first embodiment, when the IGBT is turned off during operation, the hole current tends to concentrate at the boundary between the IGBT region 101 and the FWD region 102 and the peripheral region 103.

[0145] On the other hand, in the RC-IGBT 200 of the second embodiment, the p of the FWD unit cell region 106 near the boundary between the IGBT region 101 and the peripheral region 103 is + The p-type contact layer 6 is in contact with the p-type well layer 16 of the peripheral region 103, and the contact hole 15 is formed from the p+ The p-type contact layer 6 is formed from the upper part to the upper part of the p-type well layer 16 in the peripheral region 103. Thus, the p-type well layer 16 and the p-type well layer 16 are configured. + The region of the type contact layer 6 has a low resistance, and even if the hole current increases, the potential is unlikely to increase, thereby suppressing a decrease in RBSOA.

[0146] <Implementation Method 3>

[0147] Next, use Figure 12 to Figure 16 The RC-IGBT 300 according to the third embodiment will be described. Figure 1 same, Fig.12 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.13 Show Fig.12 The arrow-directed cross-sectional view at line AA is shown. Fig.14 The arrow-directed cross-sectional view at line BB is shown. Fig.15 The arrow-directed cross-sectional view at line CC is shown. Fig.16 The arrow direction cross-sectional view at line DD is shown. Figure 12 to Figure 16 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0148] like Fig.12 As shown, in the RC-IGBT 300, as a first feature, the p + The contact layer 6 has a plurality of elongated rectangular shapes extending in the Y direction in plan view, and is arranged discontinuously at intervals so as to form a line in the longitudinal direction. The arrangement interval W1 is shorter than the length L1 in the longitudinal direction (L1>W1).

[0149] As a result, the pattern size becomes larger, the dimensional fluctuation during manufacturing can be suppressed, the contact width can be stabilized, the p-type impurity concentration in the anode region of the FWD region 102 can be stabilized, and the recovery characteristics can be stably improved.

[0150] In addition, as a second feature, the p of the entire FWD region 102 is + The area ratio of the p-type contact layer 6 is set to be lower than the area ratio of the p-type anode layer 5. This can further reduce the recovery loss.

[0151] <Implementation Method 4>

[0152] Next, use Figures 17 to 21The RC-IGBT 400 according to the fourth embodiment will be described. Figure 1 same, Fig.17 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.18 Show Fig.17 The arrow-directed cross-sectional view at line AA is shown. Fig.19 The arrow-directed cross-sectional view at line BB is shown. Fig. 20 The arrow-directed cross-sectional view at line CC is shown. Fig.21 The arrow direction cross-sectional view at line DD is shown. Figures 17 to 21 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0153] like Fig.17 As shown, in the RC-IGBT 400, as a first feature, the plurality of FWD unit cell regions 106 of the FWD region 102 are composed of p + The unit cell region (first diode unit cell region) in which the p-type contact layer 6 and the p-type anode layer 5 are alternately formed in the extending direction (Y direction) of the buried gate electrode 8, and the unit cell region (first diode unit cell region) in which the p-type contact layer 6 and the p-type anode layer 5 are alternately formed in the extending direction (Y direction) of the buried gate electrode 8. + The p-type contact layer 6 is provided and only the p-type anode layer 5 is present in the unit cell region (second diode unit cell region). + In the unit cell region of the type contact layer 6, p + The area ratio of the p-type contact layer 6 is the same in any unit cell region. + The structure is that unit cell regions including the p-type contact layer 6 and unit cell regions including only the p-type anode layer 5 are alternately arranged.

[0154] Therefore, in two adjacent unit cell regions, p + The area ratio of the p-type contact layer 6 to the p-type anode layer 5 is the same as that of the p-type contact layer 6 in the other two adjacent unit cell regions. + The area ratio of the p-type contact layer 6 to the p-type anode layer 5 is the same, so the p-type area of ​​the entire FWD region 102 is + The area ratio of the type contact layer 6 is the same, and the overall p-type contact layer of the FWD region 102 is + The area ratio of the p-type contact layer 6 is lower than that of the p-type anode layer 5, so that the p-type area of ​​the entire FWD region 102 can be reduced. + The total area of ​​the p-type contact layer 6 is set smaller than the total area of ​​the p-type anode layer 5, so that the recovery loss can be further reduced.

[0155] In addition, +The pattern size of the p-type contact layer 6 is increased, and the size fluctuation during manufacturing can be suppressed, the contact width can be stabilized, the p-type impurity concentration in the anode region of the FWD region 102 can be stabilized, and the recovery characteristics can be stably improved.

[0156] In addition, as the second feature, Fig.17 As shown, for a unit cell region having only a p-type anode layer 5 sandwiched therebetween, a p + For the two unit cell regions of the p-type contact layer 6, + The configuration positions of the p-type contact layers 6 are formed in a manner that is different from each other in the Y direction, forming a staggered configuration. + The uniformity of the two-dimensional arrangement of the type contact layer 6 is improved.

[0157] In addition, it is also possible not to have the second feature, and for the configuration with p + For the two unit cell regions of the p-type contact layer 6, + The type contact layer 6 is formed so that the arrangement position is the same in the Y direction.

[0158] <Implementation method 5>

[0159] Next, use Figure 22 to Figure 26 The RC-IGBT 500 according to the fifth embodiment will be described. Figure 1 same, Fig. 22 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.23 Show Fig. 22 The arrow-directed cross-sectional view at line AA is shown. Fig.24 The arrow-directed cross-sectional view at line BB is shown. Fig.25 The arrow-directed cross-sectional view at line CC is shown. Fig.26 The arrow direction cross-sectional view at line DD is shown. Figure 22 to Figure 26 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0160] like Fig. 22 As shown, in the RC-IGBT 500, in the FWD unit cell region 106 of the FWD region 102, p + The p-type contact layer 6 and the p-type anode layer 5 are alternately formed in the extending direction (Y direction) of the buried gate electrode 8, and the p-type anode layer 5 is alternately formed in the extending direction (Y direction) of the buried gate electrode 8. + The area ratio of the p-type contact layer 6 is lower than the area ratio of the p-type anode layer 5 .

[0161] Thus, the p of the entire FWD region 102 can be + The total area of ​​the p-type contact layer 6 is set smaller than the total area of ​​the p-type anode layer 5, so that the recovery loss can be further reduced.

[0162] In addition, + The pattern size of the p-type contact layer 6 is increased, and the size fluctuation during manufacturing can be suppressed, the contact width can be stabilized, the p-type impurity concentration in the anode region of the FWD region 102 can be stabilized, and the recovery characteristics can be stably improved.

[0163] <Implementation Method 6>

[0164] Next, use Figure 27 to Figure 31 The RC-IGBT 600 according to the sixth embodiment will be described. Figure 1 same, Fig. 27 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.28 Show Fig. 27 The arrow-directed cross-sectional view at line AA is shown. Fig.29 The arrow-directed cross-sectional view at line BB is shown. Fig.30 The arrow-directed cross-sectional view at line CC is shown. Fig.31 The arrow direction cross-sectional view at line DD is shown. Figure 27 to Figure 31 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0165] like Fig. 27 As shown in FIG. 1 , in the RC-IGBT 600, the FWD region 102 is divided into a plurality of rectangular FWD unit cell regions 107 by a grid-shaped buried gate electrode 81 having a trench structure. In the grid-shaped buried gate electrode 81, strip-shaped buried gate electrodes are arranged not only in the Y direction but also in the X direction to form a so-called matrix. The cross-sectional shape of the grid-shaped buried gate electrode 81 in the X direction and the Y direction is the same as that of the buried gate electrode 8, as shown in FIG. Fig.28 and Fig.31 As shown, the gate insulating film 71 is provided on the side surface and the bottom surface of the buried gate electrode 81 .

[0166] The FWD unit cell region 107 is provided with a rectangular p in the central part of the region. + The p-type contact layer 6 is provided around the p-type anode layer 5. The p-type contact layer 6 is provided around the p-type anode layer 5. + The area ratio of the p-type contact layer 6 is lower than the area ratio of the p-type anode layer 5 .

[0167] Thus, the p of the entire FWD region 102 can be + The total area of ​​the p-type contact layer 6 is set smaller than the total area of ​​the p-type anode layer 5, so that the recovery loss can be further reduced.

[0168] In addition, + The pattern size of the p-type contact layer 6 is increased, and the size fluctuation during manufacturing can be suppressed, the contact width can be stabilized, the p-type impurity concentration in the anode region of the FWD region 102 can be stabilized, and the recovery characteristics can be stably improved.

[0169] <Implementation Method 7>

[0170] Next, use Figure 32 to Figure 36 The RC-IGBT 700 according to the seventh embodiment will be described. Figure 1 same, Fig.32 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.33 Show Fig.32 The arrow-directed cross-sectional view at line AA is shown. Fig.34 The arrow-directed cross-sectional view at line BB is shown. Fig.35 The arrow-directed cross-sectional view at line CC is shown. Fig.36 The arrow direction cross-sectional view at line DD is shown. Figure 32 to Figure 36 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0171] like Fig.32 As shown, in the RC-IGBT 700, in the FWD unit cell region 106 of the FWD region 102, p + The p-type contact layers 6 and the p-type anode layers 5 are alternately formed in the extending direction (Y direction) of the buried gate electrode 8 .

[0172] Here, p in the FWD unit cell region 106 + The arrangement position of the type contact layer 6 is such that the buried gate electrode 8 is interposed between the n-type contact layer 6 and the IGBT unit cell region 105 when viewed from above. + The relative position of the emitter layer 3.

[0173] As a result, it becomes difficult for hole current to flow into the IGBT unit cell region 105 having n holes formed therein near the FWD unit cell region 106. + The structure of the p-type channel doped layer 2 and the p-type emitter layer 3 can suppress the reduction of the safe operation region during the operation of the IGBT.

[0174] In addition, the p of the FWD unit cell region 106 is formed. + The area ratio of the p-type contact layer 6 is lower than the area ratio of the p-type anode layer 5 .

[0175] Thus, the p of the entire FWD region 102 can be + The total area of ​​the p-type contact layer 6 is set smaller than the total area of ​​the p-type anode layer 5, so that the recovery loss can be further reduced.

[0176] <Implementation Method 8>

[0177] Next, use Figures 37 to 41 The RC-IGBT 800 according to the eighth embodiment will be described. Figure 1 same, Fig.37 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.38 Show Fig.37 The arrow-directed cross-sectional view at line AA is shown. Fig.39 The arrow-directed cross-sectional view at line BB is shown. Fig.40 The arrow-directed cross-sectional view at line CC is shown. Fig.41 The arrow direction cross-sectional view at line DD is shown. Figures 37 to 41 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0178] like Fig.37 As shown, in the RC-IGBT 800 , the arrangement interval of the buried gate electrodes 8 in the FWD region 102 is set wider than the arrangement interval of the buried gate electrodes 8 in the IGBT region 101 .

[0179] This is because it is desirable that the electric field is stronger directly under the buried gate electrode 8 in the FWD region 102 than directly under the buried gate electrode 8 in the IGBT region 101 when a voltage is applied between the emitter and the collector in the off state during IGBT operation.

[0180] As a result, avalanche breakdown can occur in the FWD region 102 rather than the IGBT region 101 during avalanche breakdown, and overvoltage damage can be suppressed.

[0181] Furthermore, the width (length in the X direction) of the FWD unit cell region 106 is also increased by the amount that the arrangement interval of the buried gate electrodes 8 in the FWD region 102 is increased, but the width is formed so that p + The area ratio of the p-type contact layer 6 is lower than the area ratio of the p-type anode layer 5 .

[0182] Thus, the p of the entire FWD region 102 can be + The total area of ​​the p-type contact layer 6 is set smaller than the total area of ​​the p-type anode layer 5, so that the recovery loss can be further reduced.

[0183] <Implementation Method 9>

[0184] Next, use Figures 42 to 46 The RC-IGBT 900 according to the ninth embodiment will be described. Figure 1 same, Fig.42 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.43 Show Fig.42 The arrow-directed cross-sectional view at line AA is shown. Fig.44 The arrow-directed cross-sectional view at line BB is shown. Fig.45 The arrow-directed cross-sectional view at line CC is shown. Fig.46 The arrow direction cross-sectional view at line DD is shown. Figures 42 to 46 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0185] like Fig.42 As shown, in the RC-IGBT 900, among the plurality of FWD unit cell regions 106 in the FWD region 102, in the FWD unit cell region 106 adjacent to the IGBT region 101, p + The width (length in the X direction) of the p-type contact layer 6 is larger than that of the other FWD unit cell regions 106. + The width of the p-type contact layer 6 is large. As a result, the p-type impurity concentration in the anode region is locally high.

[0186] Thus, in the RC-IGBT 900, since the p-type impurity concentration of the anode region near the IGBT region 101 is kept high, the anode region near the IGBT region 101 has a low resistance. Therefore, even if the hole current increases, the potential is unlikely to increase, and the reduction of RBSOA can be suppressed.

[0187] <Modification>

[0188] In addition, Fig.42 As shown in FIG. 1 , in the FWD unit cell region 106 adjacent to the IGBT region 101, p + The width of the p-type contact layer 6 is set wide, but it is not limited to this. It is also possible to set the p-type contact layer 6 to a large width in the plurality of FWD unit cell regions 106. +The width of the p-type contact layer 6 can be set wider. In addition, the p-type contact layer 6 of the FWD unit cell region 106 adjacent to the IGBT region 101 can also be set wider. + The width of the p-type contact layer 6 is set to be the widest, and the p-type contact layer 6 is set to be the widest in the direction away from the IGBT region 101 (X direction). + The width of the type contact layer 6 gradually becomes narrower.

[0189] If we expand p + The width of the p-type contact layer 6 leads to an increase in recovery loss. + The width of the type contact layer 6 can suppress the reduction of RBSOA. Therefore, the method of the above-mentioned modification example can be used to perform a design that takes into account the trade-off relationship between the increase in recovery loss and the suppression of the reduction of RBSOA.

[0190] <Implementation Method 10>

[0191] Next, use Figures 47 to 51 The RC-IGBT 1000 according to the tenth embodiment will be described. Figure 1 same, Fig.47 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.48 Show Fig.47 The arrow-directed cross-sectional view at line AA is shown. Fig.49 The arrow-directed cross-sectional view at line BB is shown. Fig.50 The arrow-directed cross-sectional view at line CC is shown. Fig.51 The arrow direction cross-sectional view at line DD is shown. Figures 47 to 51 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0192] like Fig.47 As shown, in the RC-IGBT 1000, among the plurality of FWD unit cell regions 106 in the FWD region 102, in the FWD unit cell region 106 adjacent to the IGBT region 101, p + The width (length in the X direction) of the p-type contact layer 6 is larger than that of the other FWD unit cell regions 106. + The width of the p-type contact layer 6 is narrow. As a result, the p-type impurity concentration in the anode region is locally low.

[0193] As described above, in the RC-IGBT 1000 , by reducing the average impurity concentration in the anode region near the IGBT region 101 , the recovery loss can be effectively reduced.

[0194] <Modification>

[0195] In addition, Fig.47 As shown in FIG. 1 , in the FWD unit cell region 106 adjacent to the IGBT region 101, p + The width of the p-type contact layer 6 is set narrow, but it is not limited to this. It is also possible to set the p-type contact layer 6 to a small width in the plurality of FWD unit cell regions 106. + The width of the p-type contact layer 6 is set narrow. Since the diode at the boundary with the IGBT region 101 is affected by the parasitic diode of the IGBT region 101, the distance from the boundary in the plane is about the thickness of the substrate to about 1.5 times the thickness of the substrate, by reducing the p-type contact layer 6 in this range, + The width of the p-type contact layer 6 is set to be larger than that of the p-type contact layer 6 outside this range. + The width of the type contact layer 6 is narrowed by about 10 to 30%, thereby reducing the influence from the parasitic diode.

[0196] Alternatively, the p of the FWD unit cell region 106 adjacent to the IGBT region 101 may be + The width of the p-type contact layer 6 is set to be the narrowest, and the p-type contact layer 6 is set to be the narrowest in the direction away from the IGBT region 101 (X direction). + The width of the type contact layer 6 gradually widens.

[0197] <Implementation Method 11>

[0198] Next, use Figure 52 to Figure 57 The RC-IGBT 1100 according to the eleventh embodiment will be described. Figure 1 same, Fig.52 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.53 Show Fig.52 The arrow-directed cross-sectional view at line AA is shown. Fig.54 The arrow-directed cross-sectional view at line BB is shown. Fig.55 The arrow-directed cross-sectional view at line CC is shown. Fig.56 The arrow-directed cross-sectional view at line DD is shown. Fig.57 The arrow direction cross-sectional view at line EE is shown. Figure 52 to Figure 57 In, for and use Figure 2 to Figure 6 The same components as those of the RC-IGBT 100 described above are denoted by the same reference numerals, and redundant description will be omitted.

[0199] like Fig.52 As shown, in the RC-IGBT 1100, among the plurality of IGBT unit cell regions 105 in the IGBT region 101, the IGBT unit cell region 105 adjacent to the FWD region 102 is composed of n+ Type emitter layer 3, p + type contact layer 4 and p-type channel doping layer 2.

[0200] That is, with n + Type emitter layer 3 is formed by p + The p-type contact layer 4 becomes the p-type channel doping layer 2 exposed to the p + The structure outside the p-type contact layer 4. As a result, the average concentration of p-type impurities in the IGBT region 101 near the FWD region 102 is reduced, and the hole diffusion in the IGBT region 101 in the on state during FWD operation is reduced, which can reduce the recovery loss.

[0201] <Modification>

[0202] In addition, Fig.52 FIG. 1 shows that the IGBT unit cell region 105 adjacent to the FWD region 102 is composed of n + Type emitter layer 3, p + The present invention is an example of the configuration of the p-type contact layer 4 and the p-type channel doping layer 2 , but the present invention is not limited thereto, and the same structure may be used in a plurality of IGBT unit cell regions 105 .

[0203] Furthermore, by setting the effective p-type impurity concentration to change gradually, it is possible to adjust the average impurity concentration of the IGBT unit cell region 105 near the FWD region 102 .

[0204] Specifically, if Fig.52 As shown, by increasing p + The configuration interval W of the p-type contact layer 4 increases the p-type channel doping layer 2 and reduces the p + The type contact layer 4 can thereby adjust the average impurity concentration of the IGBT unit cell region 105.

[0205] <Implementation Method 12>

[0206] Next, use Figures 58 to 62 The RC-IGBT 1200 according to the twelfth embodiment will be described. Figure 1 same, Fig.58 Yes means Figure 1 A top view of the region X surrounded by the dotted line in FIG. Fig.59 Show Fig.58 The arrow-directed cross-sectional view at line AA is shown. Fig.60 The arrow-directed cross-sectional view at line BB is shown. Fig.61 The arrow-directed cross-sectional view at line CC is shown. Fig.62 The arrow direction cross-sectional view at line DD is shown. Figures 58 to 62 In, the same reference numerals are assigned to the same structures as the RC-IGBT 100 described above, and repeated descriptions are omitted. Figure 2 to Figure 6 As shown in, the RC-IGBT 1200 has the following structure. That is, in the plurality of IGBT unit cell regions 105 of the IGBT region 101, the area ratio of the p-type contact layer 4 in the IGBT unit cell region 105 adjacent to the FWD region 102 is larger than that in other IGBT unit cell regions 105.

[0207] As Fig.58 shown, in the RC-IGBT 1200, the following structure is formed. That is, in the plurality of IGBT unit cell regions 105 of the IGBT region 101, the area of the p-type contact layer 4 in the IGBT unit cell region 105 adjacent to the FWD region 102 is made larger than that in other IGBT unit cell regions 105. + The area ratio of the p-type contact layer 4 is larger than that of other IGBT unit cell regions 105.

[0208] That is, the area of the p-type contact layer 4 in contact with the p-type well layer 16 of the peripheral region 103 is increased. Thereby, the average concentration of p-type impurities in the IGBT region 101 near the FWD region 102 is increased, and the effect of suppressing the reduction of RBSOA during IGBT operation can be improved. + The average concentration of p-type impurities in the IGBT region 101 near the FWD region 102 is increased, and the effect of suppressing the reduction of RBSOA during IGBT operation can be improved.

[0209] <Modified Example>

[0210] In addition, in Fig.58 , the area of the p-type contact layer 4 in contact with the p-type well layer 16 in the IGBT unit cell region 105 adjacent to the FWD region 102 is increased, but in the entire region of the IGBT unit cell region 105, the area of the n-type emitter layer 3 is reduced, and the area of the p-type contact layer 4 can also be increased. + The area of the p-type contact layer 4 in contact with the p-type well layer 16 in the IGBT unit cell region 105 adjacent to the FWD region 102 is increased, but in the entire region of the IGBT unit cell region 105, the area of the n-type emitter layer 3 is reduced, and the area of the p-type contact layer 4 can also be increased. + type emitter layer 3 is reduced, and the area of the p-type contact layer 4 can also be increased. + type contact layer 4 can also be increased.

[0211] In addition, in the above-described Embodiments 1 to 12, examples applied to the RC-IGBT have been described, but it can also be applied to MOSFETs and the like.

[0212] In addition, as an example of the manufacturing method, a manufacturing method using a Si substrate has been described, but a semiconductor substrate made of a different material such as silicon carbide (SiC) can also be used.

[0213] In addition, in Figure 2 etc., a strip-shaped unit having a strip-shaped buried gate electrode 8 having a trench structure is exemplified, but the present invention can also be applied to a so-called mesh-type unit extending in the vertical and horizontal directions, and can also be applied to a so-called planar-type unit structure having a planar gate.

[0214] <Other Structural Examples of RC-IGBT>

[0215] Next, other structural examples of the RC-IGBT are shown. Fig.632 is a top view showing a semiconductor device 2000 that is an RC-IGBT. Fig.64 1 is a plan view showing a semiconductor device 2001 which is an RC-IGBT. Fig.63 The semiconductor device 2000 shown in the figure has the IGBT region 110 and the diode region 120 arranged in a stripe shape, which can be simply referred to as a "strip type". Fig.64 In the semiconductor device 2001 shown in the figure, a plurality of diode regions 120 are provided in the vertical direction and the horizontal direction, and an IGBT region 110 is provided around the diode region 120, which can be simply referred to as an "island type".

[0216] <Overall planar structure of strip type>

[0217] exist Fig.63 In the embodiment, the semiconductor device 2000 includes an IGBT region 110 and a diode region 120 in one semiconductor device. The IGBT region 110 and the diode region 120 extend from one end of the semiconductor device 2000 to the other end, and are alternately arranged in stripes in a direction orthogonal to the extending direction of the IGBT region 110 and the diode region 120. Fig.63 , there are 3 IGBT regions 110 and 2 diode regions 120, and all diode regions 120 are sandwiched by the IGBT regions 110. However, the number of IGBT regions 110 and diode regions 120 is not limited to this. The number of IGBT regions 110 may be greater than or equal to 3, or less than or equal to 3, and the number of diode regions 120 may be greater than or equal to 2, or less than or equal to 2. In addition, Fig.63 The positions of the IGBT region 110 and the diode region 120 may be exchanged, or all the IGBT regions 110 may be sandwiched by the diode regions 120. In addition, the IGBT region 110 and the diode region 120 may be provided adjacent to each other one by one.

[0218] like Fig.63As shown, a pad region 140 is provided adjacent to the IGBT region 110 on the lower side of the paper. The pad region 140 is a region where a control pad 141 for controlling the semiconductor device 2000 is provided. The IGBT region 110 and the diode region 120 are collectively referred to as a cell region. In order to maintain the withstand voltage of the semiconductor device 2000, a terminal region 130 is provided around the region where the cell region and the pad region 140 are combined. A known withstand voltage maintenance structure can be appropriately and selectively provided in the terminal region 130. The withstand voltage maintenance structure can be, for example, provided on the surface side, i.e., the first main surface side, of the semiconductor device 2000, with an FLR that surrounds the cell region with a p-type terminal well layer of a p-type semiconductor and a VLD that surrounds the cell region with a p-type well layer having a concentration gradient. The number of annular p-type terminal well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 2000. In addition, a p-type terminal well layer may be provided over substantially the entire area of ​​the pad region 140, and an IGBT cell and a diode cell may be provided in the pad region 140. The control pad 141 may be, for example, a current sensing pad 141a, a Kelvin emitter pad 141b, a gate pad 141c, and temperature sensing diode pads 141d and 141e. The current sensing pad 141a is a control pad for detecting a current flowing in the cell region of the semiconductor device 2000, and is electrically connected to a portion of the IGBT cell or the diode cell in the cell region. When a current flows in the cell region of the semiconductor device 2000, a current of a few to tens of thousands of the current flowing in the entire cell region flows through the control pad.

[0219] The Kelvin emitter pad 141b and the gate pad 141c are control pads for applying a gate drive voltage for on / off control of the semiconductor device 2000. The Kelvin emitter pad 141b is electrically connected to the p-type base layer of the IGBT unit, and the gate pad 141c is electrically connected to the gate trench electrode of the IGBT unit. The Kelvin emitter pad 141b and the p-type base layer may also be connected via a p + The temperature sensing diode pads 141d and 141e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 2000. The temperature of the semiconductor device 2000 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0220] <Overall planar structure of island type>

[0221] exist Fig.64In the embodiment, the semiconductor device 2001 has an IGBT region 110 and a diode region 120 in one semiconductor device. A plurality of diode regions 120 are arranged in the vertical direction and the horizontal direction in the semiconductor device when viewed from above, and the diode region 120 is surrounded by the IGBT region 110. That is, a plurality of diode regions 120 are arranged in an island shape in the IGBT region 110. Fig.64 The structure in which the diode regions 120 are arranged in a matrix with 4 columns in the left-right direction of the paper and 2 rows in the up-down direction of the paper is shown, but the number and configuration of the diode regions 120 are not limited to this. It is sufficient as long as one or more diode regions 120 are dispersed in the IGBT region 110 and each diode region 120 is surrounded by the IGBT region 110.

[0222] like Fig.64 As shown, a pad region 140 is provided adjacent to the lower side of the IGBT region 110. The pad region 140 is a region where a control pad 141 for controlling the semiconductor device 2001 is provided. The IGBT region 110 and the diode region 120 are collectively referred to as a cell region. In order to maintain the withstand voltage of the semiconductor device 2001, a termination region 130 is provided around the region where the cell region and the pad region 140 are combined. A known withstand voltage maintaining structure can be appropriately and selectively provided in the termination region 130. The withstand voltage maintaining structure can be, for example, provided on the surface side, i.e., the first main surface side, of the semiconductor device 2001, with an FLR that surrounds the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor and a VLD that surrounds the cell region with a p-type well layer having a concentration gradient. The number of annular p-type termination well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 2001. Alternatively, a p-type end well layer may be provided over substantially the entire pad region 140 , and an IGBT cell and a diode cell may be provided in the pad region 140 .

[0223] The control pad 141 may be, for example, a current sensing pad 141a, a Kelvin emitter pad 141b, a gate pad 141c, and temperature sensing diode pads 141d and 141e. The current sensing pad 141a is a control pad for detecting the current flowing in the cell region of the semiconductor device 2001, and is electrically connected to a part of the IGBT cell or the diode cell in the cell region. When the current flows in the cell region of the semiconductor device 2001, a current of a few to tens of thousands of the current flowing in the entire cell region flows through the control pad.

[0224] The Kelvin emitter pad 141b and the gate pad 141c are control pads for applying a gate drive voltage for on / off control of the semiconductor device 2001. The Kelvin emitter pad 141b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The Kelvin emitter pad 141b and the p-type base layer can also be electrically connected via the p + The temperature sensing diode pads 141d and 141e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 2001. The temperature of the semiconductor device 2001 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0225] <Local Plane Structure>

[0226] Fig.65 It is a magnified representation Fig.63 The semiconductor device 2000 or Fig.64 FIG. 2 is a partial top view of a region 182 of the IGBT region 110 of the semiconductor device 2001 surrounded by a dotted line. Fig.65 As shown, an active trench gate 111 and a dummy trench gate 112 are provided in a strip shape in the IGBT region 110. In the semiconductor device 2000, the active trench gate 111 and the dummy trench gate 112 extend in the length direction of the IGBT region 110, and the length direction of the IGBT region 110 becomes the length direction of the active trench gate 111 and the dummy trench gate 112. On the other hand, in the semiconductor device 2001, the difference between the length direction and the width direction at the IGBT region 110 is not particularly limited, and the left-right direction of the paper can be set as the length direction of the active trench gate 111 and the dummy trench gate 112, and the up-down direction of the paper can also be set as the length direction of the active trench gate 111 and the dummy trench gate 112.

[0227] The active trench gate 111 is formed by providing a gate trench electrode 111a in a trench formed in a semiconductor substrate via a gate trench insulating film 111b. The dummy trench gate 112 is formed by providing a dummy trench electrode 112a in a trench formed in a semiconductor substrate via a dummy trench insulating film 112b. The gate trench electrode 111a of the active trench gate 111 is connected to the gate pad 141c ( Fig.63 , Fig.64 The dummy trench electrode 112 a of the dummy trench gate 112 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 2000 or the semiconductor device 2001 .

[0228] n +The type source layer 113 is provided so as to be in contact with the gate trench insulating film 111b on both sides of the active trench gate 111 in the width direction. + The source layer 113 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 .n + The source layer 113 is connected to the p-type source layer 113 along the extension direction of the active trench gate 111. + A p-type contact layer 114 is alternately provided. A p-type contact layer 114 is also provided between two adjacent dummy trench gates 112. + Type contact layer 114. + The p-type contact layer 114 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 .

[0229] like Fig.65 As shown, in the IGBT region 110 of the semiconductor device 2000 or the semiconductor device 2001, three dummy trench gates 112 are arranged next to three parallel active trench gates 111, and three active trench gates 111 are arranged next to three parallel dummy trench gates 112. The IGBT region 110 is configured such that groups of active trench gates 111 and groups of dummy trench gates 112 are alternately arranged as described above. Fig.65 In the figure, the number of active trench gates 111 included in one group of active trench gates 111 is 3, but it can be greater than or equal to 1. In addition, the number of dummy trench gates 112 included in one group of dummy trench gates 112 can be greater than or equal to 1, and the number of dummy trench gates 112 can also be zero. That is, all trenches provided in the IGBT region 110 can also be set as active trench gates 111.

[0230] <Local Section Structure>

[0231] Fig.66 yes Fig.65 The arrow direction section view of the AA line in the figure. Fig.66 As shown, the semiconductor device 2000 or the semiconductor device 2001 has n composed of a semiconductor substrate. - Type drift layer 91. - The drift layer 91 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 . Semiconductor substrates Fig.66 In the IGBT region 110, n + Type source layer 113 and p + The range from the p-type contact layer 114 to the p-type collector layer 116 .

[0232] exist Fig.66 In the IGBT region 110, n + Type source layer 113 and p + The upper end of the p-type contact layer 114 on paper is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 116 on paper is referred to as the second main surface of the semiconductor substrate.

[0233] The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 2000 or the semiconductor device 2001, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 2000 or the semiconductor device 2001. The semiconductor device 2000 or the semiconductor device 2001 has n between the first main surface and the second main surface opposite to the first main surface in the cell region, that is, the IGBT region 110. - Type drift layer 91.

[0234] like Fig.66 As shown, in the IGBT region 110, at n - The first main surface side of the type drift layer 91 is provided with an n-type impurity having a concentration ratio n - The n-type carrier storage layer 92 has a high n-type drift layer 91. The n-type carrier storage layer 92 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 In addition, the semiconductor device 2000 and the semiconductor device 2001 may not have the n-type carrier storage layer 92, but may have the n-type carrier storage layer 92 in the region thereof. - By providing the n-type carrier storage layer 92, the conduction loss when the current flows through the IGBT region 110 can be reduced. - The type drift layer 91 is collectively referred to as a drift layer.

[0235] The n-type carrier storage layer 92 is formed by implanting n-type impurity ions into the n-type carrier storage layer 92. - The semiconductor substrate of the type drift layer 91 is then annealed to diffuse the injected n-type impurities into the n -The type drift layer 91 is formed in the semiconductor substrate.

[0236] A p-type base layer 115 is provided on the first main surface side of the n-type carrier storage layer 92. The p-type base layer 15 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 115 is in contact with the gate trench insulating film 111 b of the active trench gate 111 . An n-type base layer 115 is provided on the first main surface side of the p-type base layer 115 in contact with the gate trench insulating film 111 b of the active trench gate 111 . + Type source layer 113, and a p + Type contact layer 114. + Type source layer 113 and p + The p-type contact layer 114 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 114 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 115. + In the case of the p-type contact layer 114 and the p-type base layer 115, each of them can be referred to separately, or the p + The p-type contact layer 114 and the p-type base layer 115 are collectively referred to as a p-type base layer.

[0237] In the semiconductor device 2000 or the semiconductor device 2001, - The second main surface side of the type drift layer 91 is provided with an n-type impurity having a concentration ratio n - The n-type buffer layer 93 is formed to suppress the breakdown of the depletion layer extending from the p-type base layer 115 to the second main surface when the semiconductor device 2000 or the semiconductor device 2001 is turned off. The n-type buffer layer 93 may be, for example, a layer of phosphorus (P) or protons (H + ) or by implanting phosphorus (P) or protons (H + ) are formed by the two. The concentration of n-type impurities in the n-type buffer layer 93 is 1.0×10 12 / cm 3 ~1.0×10 18 / cm 3 .

[0238] Alternatively, the semiconductor device 2000 or the semiconductor device 2001 may be provided with an n-type buffer layer 93 without providing the n-type buffer layer 93. - The structure of the n-type drift layer 91 can also be formed by forming the n-type buffer layer 93 and the n-type -The type drift layer 91 is collectively referred to as a drift layer.

[0239] The semiconductor device 2000 or the semiconductor device 2001 includes a p-type collector layer 116 disposed on the second main surface side of the n-type buffer layer 93. - A p-type collector layer 116 is provided between the drift layer 91 and the second main surface. The p-type collector layer 116 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 116 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 116 is provided not only in the IGBT region 110 but also in the terminal region 130 (not shown). The portion of the p-type collector layer 116 provided in the terminal region 130 constitutes a p-type terminal collector layer 116a. In addition, a portion of the p-type collector layer 116 may be provided so as to extend from the IGBT region 110 to the diode region 120.

[0240] like Fig.66 As shown, in the IGBT region 110, a layer is formed which penetrates through the p-type base layer 115 from the first main surface of the semiconductor substrate to the n-type base layer 115. - The active trench gate 111 is formed by providing a gate trench electrode 111a in the trench via a gate trench insulating film 111b. The gate trench electrode 111a is connected to the n-type drift layer 91 via the gate trench insulating film 111b. - The dummy trench electrode 112a is disposed in the trench via the dummy trench insulating film 112b to form the dummy trench gate 112. The dummy trench electrode 112a is disposed via the dummy trench insulating film 112b to the n-type drift layer 91. - The gate trench insulating film 111b of the active trench gate 111 is opposite to the p-type base layer 115 and the n-type drift layer 91. + The active trench gate 111 is in contact with the p-type source layer 113. When a gate driving voltage is applied to the gate trench electrode 111a, a channel is formed in the p-type base layer 115 in contact with the gate trench insulating film 111b of the active trench gate 111.

[0241] like Fig.66 As shown in FIG. 1 , an interlayer insulating film 94 is provided on the gate trench electrode 111a of the active trench gate 111. A barrier metal 95 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 94 is not provided and on the interlayer insulating film 94. The barrier metal 95 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). Fig.66As shown, the barrier metal 95 and n + Type source layer 113, p + The type contact layer 114 and the dummy trench electrode 112a make ohmic contact with the n + Type source layer 113, p + The type contact layer 114 and the dummy trench electrode 112a are electrically connected. An emitter electrode 96 is provided on the barrier metal 95. The emitter electrode 96 may be formed, for example, by an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode composed of a multilayer metal film having a coating formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The coating formed by chemical plating or electroplating may be, for example, a nickel (Ni) coating. In addition, in the case where there are tiny areas such as between adjacent interlayer insulating films 94, that is, areas that cannot be well buried by the emitter electrode 96, tungsten (W) having better burying properties than the emitter electrode 96 may be arranged in a tiny area, and the emitter electrode 96 may be provided on the tungsten. In addition, the barrier metal 95 may not be provided, and the n + Type source layer 113, p + The emitter electrode 96 is provided on the n-type contact layer 114 and the dummy trench electrode 112a. + A barrier metal 95 is provided on an n-type semiconductor layer such as an n-type source layer 113. The barrier metal 95 and the emitter electrode 86 may be collectively referred to as an emitter electrode. Fig.66 , the interlayer insulating film 94 is not provided on the dummy trench electrode 112a of the dummy trench gate 112, but the interlayer insulating film 94 may be formed on the dummy trench electrode 112a of the dummy trench gate 112. In the case where the interlayer insulating film 94 is formed on the dummy trench electrode 112a of the dummy trench gate 112, the emitter electrode 96 and the dummy trench electrode 112a may be electrically connected in other cross sections.

[0242] A collector electrode 97 is provided on the second main surface side of the p-type collector layer 116. The collector electrode 97 may be formed of an aluminum alloy or an aluminum alloy and a plated film, similarly to the emitter electrode 96. In addition, the collector electrode 97 may have a structure different from that of the emitter electrode 96. The collector electrode 97 makes ohmic contact with the p-type collector layer 116 and is electrically connected to the p-type collector layer 116.

[0243] Fig.67 yes Fig.65 The arrow direction section view of the BB line in the figure. Fig.67 The cross-sectional structure of the IGBT region 110 shown is along p + The cross-sectional structure of the arrangement direction of the p-type contact layer 114 is such that the p-type base layer 15 is entirely provided on the first main surface side. + Type contact layer 114, no n+ The source layer 113 is similar to Fig.66 Different. That is, Fig.65 As shown, n + The p-type source layer 113 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 114 is collectively referred to as a p-type base layer.

[0244] <Structure of diode region>

[0245] <Local Plane Structure>

[0246] Fig.68 It is a magnified representation Fig.63 The semiconductor device 2000 or Fig.54 FIG. 2 is a partial top view of a region 183 of the diode region 120 in the semiconductor device 2001 shown in FIG. Fig.68 As shown in FIG. 1 , in the diode region 120, a diode trench gate 121 extends from one end side of the unit region, i.e., the diode region 120, to the other end side opposite thereto along the first main surface of the semiconductor device 2000 or the semiconductor device 2001. The diode trench gate 121 is formed by providing a diode trench electrode 121a in a trench formed in the semiconductor substrate of the diode region 120 via a diode trench insulating film 121b. The diode trench electrode 121a is connected to the n-type semiconductor device 2000 or the n-type semiconductor device 2001 via the diode trench insulating film 121b. - A p-type drift layer 91 is provided between two adjacent diode trench gates 121. + type contact layer 124 and p-type anode layer 125.

[0247] p + The p-type contact layer 124 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 125 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 . p + The p-type contact layers 124 and the p-type anode layers 125 are alternately disposed in the length direction of the diode trench gate 121 .

[0248] <Local Section Structure>

[0249] Fig.69 yes Fig.68 The cross-sectional view in the direction of the arrow at the CC line in the figure. Fig.69 As shown, the semiconductor device 2000 or the semiconductor device 2001 also has an n-type semiconductor substrate in the diode region 120 similarly to the IGBT region 110. - Type drift layer 1. The n of diode region 120 - The drift layer 1 and the IGBT region 110 are n - The type drift layer 1 is continuously formed as a whole and is formed by the same semiconductor substrate. Fig.69 The semiconductor substrate is made of p + Type contact layer 124 to n + The range from the cathode layer 126 to the cathode layer 126. Fig.69 Lieutenant General + The upper end of the paper surface of the type contact layer 124 is called the first main surface of the semiconductor substrate. + The lower end of the cathode layer 126 is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 120 is the same as the first main surface of the IGBT region 110, and the second main surface of the diode region 120 is the same as the second main surface of the IGBT region 110.

[0250] like Fig.69 As shown, in the diode region 120, similarly to the IGBT region 110, - An n-type carrier storage layer 92 is provided on the first main surface side of the n-type drift layer 91. - An n-type buffer layer 93 is provided on the second main surface side of the type drift layer 91. The n-type carrier accumulation layer 92 and the n-type buffer layer 93 provided in the diode region 120 have the same structure as the n-type carrier accumulation layer 92 and the n-type buffer layer 93 provided in the IGBT region 110. In addition, it is not necessary to provide the n-type carrier accumulation layer 92 in the IGBT region 110 and the diode region 120. Even if the n-type carrier accumulation layer 92 is provided in the IGBT region 110, a structure in which the n-type carrier accumulation layer 92 is not provided in the diode region 120 may be adopted. In addition, similarly to the IGBT region 110, the n-type carrier accumulation layer 92 may be provided in the diode region 120. - The n-type drift layer 91, the n-type carrier accumulation layer 92, and the n-type buffer layer 93 are collectively referred to as a drift layer.

[0251] A p-type anode layer 125 is provided on the first main surface side of the n-type carrier storage layer 92. The p-type anode layer 125 is provided on the n-type carrier storage layer 92. -The p-type drift layer 91 and the first main surface are provided between the p-type anode layer 125 and the first main surface. The p-type impurity concentration of the p-type anode layer 125 may be set to the same concentration as the p-type base layer 15 of the IGBT region 110, and the p-type anode layer 125 and the p-type base layer 115 may be formed simultaneously. In addition, the p-type impurity concentration of the p-type anode layer 125 may be set lower than the p-type impurity concentration of the p-type base layer 115 of the IGBT region 110, so that the amount of holes injected into the diode region 120 during the diode operation is reduced. By reducing the amount of holes injected during the diode operation, the recovery loss during the diode operation can be reduced.

[0252] On the first main surface side of the p-type anode layer 125, a p + Type contact layer 124. + The concentration of the p-type impurity in the p-type contact layer 124 can be set to be equal to the concentration of the p-type impurity in the IGBT region 110. + The p-type impurity in the p-type contact layer 114 may have the same concentration or different concentrations. + The p-type contact layer 124 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 124 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 125. + In the case of the p-type contact layer 124 and the p-type anode layer 125, each of them can be referred to separately, or the p + The p-type contact layer 124 and the p-type anode layer 125 are collectively referred to as a p-type anode layer.

[0253] In the diode region 120 , an n-type buffer layer 93 is provided on the second main surface side. + Type cathode layer 126. + The type cathode layer 126 is disposed on the n - Between the type drift layer 91 and the second main surface. + The cathode layer 126 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3 .like Fig.69 As shown, n + The cathode layer 126 is disposed on a part or the whole of the diode region 120. + The p-type cathode layer 126 constitutes the second main surface of the semiconductor substrate. Although not shown in the figure, p-type impurities may be further selectively implanted into the n-type cathode layer 126 formed as described above. + The area of ​​the type cathode layer 126 will form an n +A portion of the region of the p-type cathode layer 126 is provided as a p-type semiconductor. In this way, n-type cathode layers are alternately arranged along the second main surface of the semiconductor substrate. + Type cathode layer and p + The diode with a cathode layer is called an RFC (Relaxed Field of Cathode) diode.

[0254] like Fig.69 As shown, in the diode region 120 of the semiconductor device 2000 or the semiconductor device 2001, a p-type anode layer 125 is formed from the first main surface of the semiconductor substrate to the n-type anode layer 125. - The diode trench gate 121 is formed by providing a diode trench electrode 121a in the trench of the diode region 120 via a diode trench insulating film 121b. The diode trench electrode 121a is connected to the n-type drift layer 91 via the diode trench insulating film 121b. - type drift layer 91 is opposite.

[0255] like Fig.69 As shown, in the diode trench electrodes 121a and p + A barrier metal 95 is disposed on the type contact layer 124. The barrier metal 95 is connected to the diode trench electrode 121a and the p + The type contact layer 124 makes ohmic contact with the diode trench electrode and the p + The barrier metal 95 may have the same structure as the barrier metal 95 of the IGBT region 110. An emitter electrode 96 is provided on the barrier metal 95. The emitter electrode 96 provided in the diode region 120 is formed continuously with the emitter electrode 96 provided in the IGBT region 110. In addition, as in the case of the IGBT region 110, the barrier metal 95 may not be provided, and the diode trench electrode 121a and the p + The type contact layer 124 makes ohmic contact with the emitter electrode 96. Fig.69 , the interlayer insulating film 94 is not provided on the diode trench electrode 121a of the diode trench gate 121, but the interlayer insulating film 94 may be formed on the diode trench electrode 121a of the diode trench gate 121. When the interlayer insulating film 94 is formed on the diode trench electrode 121a of the diode trench gate 121, the emitter electrode 96 and the diode trench electrode 121a may be electrically connected in other cross sections.

[0256] In n +A collector electrode 97 is provided on the second main surface side of the n-type cathode layer 126. Similar to the emitter electrode 96, the collector electrode 97 of the diode region 120 is formed continuously with the collector electrode 97 provided in the IGBT region 110. The collector electrode 97 is connected to the n-type cathode layer 126. + The type cathode layer 126 makes ohmic contact with the n + The cathode layer 126 is electrically connected.

[0257] Fig.70 yes Fig.68 The arrow direction section view at the DD line in the figure. Fig.70 The cross-sectional structure of the diode region 120 shown is a cross-sectional structure along the arrangement direction of the p-type anode layer 125, so no p-type anode layer 125 is provided between the p-type anode layer 125 and the barrier metal 95. + The p-type contact layer 124 and the p-type anode layer 125 constitute the first main surface of the semiconductor substrate. Fig.69 Different. That is, Fig.68 As shown, p + The p-type contact layer 124 is selectively provided on the first main surface side of the p-type anode layer 125 .

[0258] Fig.71 yes Fig.63 The semiconductor device 2000 or Fig.64 The cross-sectional view of the semiconductor device 2001 taken along the line GG shown in the arrow direction shows the structure of the boundary portion between the IGBT region 110 and the diode region 120 .

[0259] like Fig.71 As shown in FIG. 1 , the p-type collector layer 116 provided on the second main surface side of the IGBT region 110 is provided so as to extend from the boundary between the IGBT region 110 and the diode region 120 to the diode region 120 by a distance U1. In this way, by providing the p-type collector layer 116 to extend to the diode region 120, the n-type collector layer 116 of the diode region 120 can be + The distance between the cathode layer 126 and the active trench gate 111 is set large, so that even when a gate drive voltage is applied to the active trench gate 111 when the freewheeling diode is in operation, current can flow from the channel formed adjacent to the active trench gate 111 in the IGBT region 110 to the n-type cathode layer 126. + The type cathode layer 126 suppresses the above. The distance U1 may be, for example, 100 μm. In addition, the distance U1 may be zero or a distance smaller than 100 μm depending on the application of the RC-IGBT, that is, the semiconductor device 2000 or the semiconductor device 2001.

[0260] <Structure of the terminal area>

[0261] Fig.72 yes Fig.63The semiconductor device 2000 or Fig.64 The cross-sectional view of the semiconductor device 2001 taken along line EE in the direction of arrows shows the structure of the boundary portion between the IGBT region 110 and the termination region 130 .

[0262] like Fig.72 As shown, the terminal region 130 of the semiconductor device 2000 or the semiconductor device 2001 has n between the first main surface and the second main surface of the semiconductor substrate. - The first main surface and the second main surface of the terminal region 130 are coplanar with the first main surface and the second main surface of the IGBT region 110 and the diode region 120, respectively. - The type drift layer 91 is respectively connected to the n-type drift layer of the IGBT region 110 and the diode region 120. - The drift layer 91 has the same structure and is continuously formed as a whole.

[0263] In n - The first main surface side of the n type drift layer 91, that is, the first main surface of the semiconductor substrate and the n - A p-type end well layer 131 is provided between the p-type drift layers 91. The p-type end well layer 131 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity. The concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 The p-type end well layer 131 is provided to surround the cell region including the IGBT region 110 and the diode region 120. The p-type end well layer 131 is provided in a plurality of rings, and the number of the p-type end well layers 131 is appropriately selected according to the withstand voltage design of the semiconductor device 2000 or the semiconductor device 2001. In addition, an n-type end well layer 131 is provided at the further edge side of the p-type end well layer 131. + Type channel stop layer 132, n + The p-type channel stopper layer 132 surrounds the p-type end well layer 131 .

[0264] In n - A p-type end collector layer 116a is provided between the type drift layer 91 and the second main surface of the semiconductor substrate. The p-type end collector layer 116a is formed continuously and integrally with the p-type collector layer 116 provided in the cell region. Therefore, the p-type end collector layer 116 may also be referred to as the p-type collector layer 116 including the p-type end collector layer 116a.

[0265] A collector electrode 97 is provided on the second main surface of the semiconductor substrate. The collector electrode 97 is formed continuously and integrally from the cell region including the IGBT region 110 and the diode region 120 to the terminal region 130. On the other hand, an emitter electrode 96 continuous from the cell region and a terminal electrode 96a separated from the emitter electrode 96 are provided on the first main surface of the semiconductor substrate in the terminal region 130.

[0266] The emitter electrode 96 and the terminal electrode 96a are electrically connected via the semi-insulating film 133. The semi-insulating film 133 may be, for example, sinSiN (semi-insulating Silicon Nitride). + The type channel stopper layer 132 is electrically connected via a contact hole formed in the interlayer insulating film 94 provided on the first main surface of the termination region 130. In addition, a termination protection film 134 is provided in the termination region 130 so as to cover the emitter electrode 96, the termination electrode 96a and the semi-insulating film 133. The termination protection film 134 can be formed of, for example, polyimide.

[0267] Fig.73 yes Fig.63 The semiconductor device 2000 or Fig.64 The cross-sectional view along the line FF in the semiconductor device 2001 shown in the arrow direction shows the structure of the boundary portion between the IGBT region 110 and the termination region 130 .

[0268] like Fig.73 As shown in FIG. 1 , the end of the p-type terminal collector layer 116a on the diode region 120 is arranged to extend a distance U2 toward the diode region 120. Thus, by arranging the p-type terminal collector layer 116a to extend toward the diode region 120, the n-type diode region 120 can be + By setting the distance U2 between the p-type cathode layer 126 and the p-type end well layer 131 to be large, it is possible to suppress the p-type end well layer 131 from operating as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0269] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

[0270] Description of the label

[0271] 1 n - type drift layer, 2 p-type channel doping layer, 3 n + Type source layer, 4, 6 p +type contact layer, 5 p-type anode layer, 8 buried gate electrode, 10 n-type buffer layer, 11 p-type collector layer, 13 emitter electrode, 14 collector electrode, 15 contact hole, 16 p-type well layer, 101 IGBT region, 102 FWD region, 103 peripheral region, 105 IGBT unit cell region, 106 FWD unit cell region.

Claims

1. A semiconductor device comprising a transistor and a diode formed on a common semiconductor substrate, The semiconductor substrate has: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and a peripheral region surrounding a cell region including the transistor region and the diode region, The transistor region is divided into a plurality of transistor unit cell regions by a plurality of strip-shaped gate electrodes. The diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. The plurality of transistor unit cell regions have: a first semiconductor layer of a first conductivity type, provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, provided on the first main surface side of the semiconductor substrate relative to the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is selectively provided on an upper layer portion of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is selectively provided in a manner that the side surface is in contact with the fourth semiconductor layer; a first electrode electrically connected to the first semiconductor layer; as well as a second electrode electrically connected to the fourth semiconductor layer and the fifth semiconductor layer via a contact hole, The plurality of diode unit cell regions have: a sixth semiconductor layer of the second conductivity type, provided on the second main surface side of the semiconductor substrate; The second semiconductor layer is disposed on the sixth semiconductor layer; a seventh semiconductor layer of the first conductivity type, provided on the first main surface side of the semiconductor substrate relative to the second semiconductor layer; an eighth semiconductor layer of the first conductivity type, which is selectively provided on an upper layer portion of the seventh semiconductor layer; the first electrode being electrically connected to the sixth semiconductor layer; and The second electrode is electrically connected to the seventh semiconductor layer and the eighth semiconductor layer via the contact hole. The fifth semiconductor layer in the transistor region is configured to contact the first conductive type impurity layer which is provided in the peripheral region and defines the boundary with the cell region, or to intrude into the impurity layer, and the contact hole is configured to extend to the upper portion of the impurity layer in the peripheral region.

2. A semiconductor device comprising a transistor and a diode formed on a common semiconductor substrate, The semiconductor substrate has: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and a peripheral region surrounding a cell region including the transistor region and the diode region, The transistor region is divided into a plurality of transistor unit cell regions by a plurality of strip-shaped gate electrodes. The diode region is divided into a plurality of rectangular diode unit cell regions by a grid-shaped gate electrode. The plurality of transistor unit cell regions have: a first semiconductor layer of a first conductivity type, provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, provided on the first main surface side of the semiconductor substrate relative to the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is selectively provided on an upper layer portion of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is selectively provided in a manner that the side surface is in contact with the fourth semiconductor layer; a first electrode electrically connected to the first semiconductor layer; as well as a second electrode electrically connected to the fourth semiconductor layer and the fifth semiconductor layer via a contact hole, The plurality of diode unit cell regions have: a sixth semiconductor layer of the second conductivity type, provided on the second main surface side of the semiconductor substrate; The second semiconductor layer is disposed on the sixth semiconductor layer; a seventh semiconductor layer of the first conductivity type, provided on the first main surface side of the semiconductor substrate relative to the second semiconductor layer; an eighth semiconductor layer of the first conductivity type, which is selectively provided on an upper layer portion of the seventh semiconductor layer; the first electrode being electrically connected to the sixth semiconductor layer; and The second electrode is electrically connected to the seventh semiconductor layer and the eighth semiconductor layer via the contact hole. The fifth semiconductor layer in the transistor region is configured to contact the first conductive type impurity layer which is provided in the peripheral region and defines the boundary with the cell region, or to intrude into the impurity layer, and the contact hole is configured to extend to the upper portion of the impurity layer in the peripheral region.

3. The semiconductor device according to claim 1 or 2, wherein: The eighth semiconductor layer in the diode region is provided so as not to be in contact with the impurity layer in the peripheral region, and the contact hole is provided so as to extend to an upper portion of the impurity layer in the peripheral region.

4. The semiconductor device according to claim 1, wherein The eighth semiconductor layer in the diode region is provided so as to be in contact with the impurity layer in the peripheral region, and the contact hole is provided so as to extend to an upper portion of the impurity layer in the peripheral region.

5. The semiconductor device according to claim 1, wherein The eighth semiconductor layer in the diode region is provided so as to have a plan view shape that is a continuous line extending in the extending direction of the plurality of gate electrodes.

6. The semiconductor device according to claim 1, wherein The eighth semiconductor layer in the diode region is provided in a plan view with a plurality of elongated rectangular shapes extending in the extending direction of the plurality of gate electrodes, and is arranged at intervals so as to form a row in the longitudinal direction thereof. The interval is set to be shorter than the length in the longitudinal direction.

7. The semiconductor device according to claim 1, wherein The plurality of diode unit cell regions include: a first diode unit cell region, which does not have the eighth semiconductor layer; and a second diode unit cell region having the eighth semiconductor layer, The first diode unit cell region and the second diode unit cell region are alternately arranged in the arrangement direction of the plurality of gate electrodes. With respect to the second diode unit cell region, The seventh semiconductor layer and the eighth semiconductor layer are alternately arranged in the extending direction of the plurality of gate electrodes.

8. The semiconductor device according to claim 7, wherein: In the second diode unit cell regions on both sides of the first diode unit cell region, arrangement positions of the eighth semiconductor layer are different from each other in the extending direction of the plurality of gate electrodes.

9. The semiconductor device according to claim 1, wherein: In the plurality of diode unit cell regions, in each of the diode unit cell regions, the seventh semiconductor layer and the eighth semiconductor layer are alternately arranged in an extending direction of the plurality of gate electrodes.

10. The semiconductor device according to claim 1 or 2, wherein: The ratio of the area of ​​the 8th semiconductor layer in each of the multiple diode unit cell regions when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above is smaller than the ratio of the area of ​​the 7th semiconductor layer when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above.

11. The semiconductor device according to claim 10, wherein The ratio of the area of ​​the 8th semiconductor layer in each of the multiple diode unit cell regions when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above is smaller than the ratio of the area of ​​the 5th semiconductor layer in each of the multiple transistor unit cell regions when viewed from above to the total area of ​​the 4th semiconductor layer and the 5th semiconductor layer when viewed from above.

12. The semiconductor device according to claim 1, wherein The plurality of gate electrodes in the diode region are arranged at a wider interval than the plurality of gate electrodes in the transistor region.

13. The semiconductor device according to claim 1, wherein Among the multiple diode unit cell regions, the ratio of the area of ​​the 8th semiconductor layer in the diode unit cell region adjacent to the transistor region when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above is greater than the ratio of the area of ​​the 8th semiconductor layer in the diode unit cell region not adjacent to the transistor region when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above.

14. The semiconductor device according to claim 1, wherein Among the multiple diode unit cell regions, the ratio of the area of ​​the 8th semiconductor layer in the diode unit cell region adjacent to the transistor region when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above is smaller than the ratio of the area of ​​the 8th semiconductor layer in the diode unit cell region not adjacent to the transistor region when viewed from above to the total area of ​​the 7th semiconductor layer and the 8th semiconductor layer when viewed from above.

15. The semiconductor device according to claim 1, wherein Among the multiple transistor unit cell regions, the ratio of the area of ​​the 5th semiconductor layer in the transistor unit cell region adjacent to the diode region when viewed from above to the total area of ​​the 4th semiconductor layer and the 5th semiconductor layer when viewed from above is smaller than the ratio of the area of ​​the 5th semiconductor layer in the transistor unit cell region not adjacent to the diode region when viewed from above to the total area of ​​the 4th semiconductor layer and the 5th semiconductor layer when viewed from above.

16. The semiconductor device according to claim 1, wherein Among the multiple transistor unit cell regions, the ratio of the area of ​​the 5th semiconductor layer in the transistor unit cell region adjacent to the diode region when viewed from above to the total area of ​​the 4th semiconductor layer and the 5th semiconductor layer when viewed from above is greater than the ratio of the area of ​​the 5th semiconductor layer in the transistor unit cell region not adjacent to the diode region when viewed from above to the total area of ​​the 4th semiconductor layer and the 5th semiconductor layer when viewed from above.

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