Antifuse programming control circuit based on master-slave charge pump structure

Abstract

The present invention discloses an anti-fuse programming control circuit based on a master-slave charge pump structure, which relates to the technical field of anti-fuses. In the circuit, a master charge pump module obtains an external voltage and connects to each slave charge pump module. Each slave charge pump module is connected to an anti-fuse array, and the layout position of each slave charge pump module is no more than a predetermined distance from the layout position of the connected anti-fuse array. The feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module based on the programming voltage output by each slave charge pump module to the connected anti-fuse array. The master charge pump module adjusts the main drive signal provided to the slave charge pump module based on the feedback signal corresponding to each slave charge pump module to stabilize the programming voltage output by the slave charge pump module. The circuit can provide accurate programming voltage to the anti-fuse array, which is beneficial to improving the consistency of the resistance value after anti-fuse programming and optimizing performance.

Description

Technical Field

[0001] The present invention relates to the technical field of anti-fuse, in particular to an anti-fuse programming control circuit based on a master-slave charge pump structure. Background Art

[0002] MTM antifuse memory devices utilize a breakdown dielectric between two metal layers for programming and data storage. They possess inherent radiation resistance, high reliability, and high integration. However, the performance of MTM antifuse memory devices relies on the consistency of the antifuse's resistance after programming, which in turn is highly dependent on the programming voltage. Currently, the conventional approach is to use a charge pump to provide the programming voltage, but this accuracy is difficult to guarantee, impacting performance. Summary of the Invention

[0003] In response to the above problems and technical requirements, the inventors have proposed an anti-fuse programming control circuit based on a master-slave charge pump structure. The technical solution of the present invention is as follows:

[0004] An antifuse programming control circuit based on a master-slave charge pump structure includes a master charge pump module, a plurality of slave charge pump modules, and a feedback network. The master charge pump module obtains an external voltage and connects to each slave charge pump module. Each slave charge pump module is connected to an antifuse array, and the layout position of each slave charge pump module is within a predetermined distance from the layout position of the antifuse array to which it is connected.

[0005] The feedback network outputs a corresponding feedback signal from the slave charge pump module to the main charge pump module based on the programming voltage output by each slave charge pump module to the connected antifuse array. The main charge pump module adjusts the main drive signal provided to the slave charge pump module based on the feedback signal corresponding to each slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

[0006] Its further technical solution is that the main charge pump module includes four main charge pumps connected in parallel and working simultaneously, the phase difference between the working clocks of each main charge pump is 90°, and the main charge pump module provides the main drive signal of the current value required for anti-fuse programming through the four main charge pumps.

[0007] A further technical solution is that each main charge pump includes a first voltage conversion module, a second voltage conversion module, a third voltage conversion module, and a fourth voltage conversion module connected in cascade order, wherein the input end of the first voltage conversion module is connected to the input end of the main charge pump for obtaining an external voltage, and the output end of the fourth voltage conversion module is connected to the output end of the main charge pump for outputting a main drive signal;

[0008] Each voltage conversion module includes NMOS tubes N0, N4, N8, N9, N16 and N17, the drain of N8, the drain of N9 and the drain of N4 are all connected and serve as the input end of the voltage conversion module, the gate of N8, the source of N9, the gate of N17 and the gate of N4 are all connected, the gate of N9, the source of N8 and the gate of N16 are all connected, the source of N4 and the gate of N0 are connected and serve as the output end of the voltage conversion module, the drain and source of N0 are connected and serve as the first clock end of the voltage conversion module; the drain and source of N16 are connected and serve as the second clock end of the voltage conversion module, and the drain and source of N17 are connected and serve as the third clock end of the voltage conversion module;

[0009] Each clock terminal of each voltage conversion module is controlled by a clock signal determined by the working clock of the main charge pump.

[0010] A further technical solution is that each main charge pump operates in the first operating mode or the second operating mode according to the received mode control signal;

[0011] When the main charge pump operates in the first operating mode, the main charge pump obtains a first external voltage, and two adjacent voltage conversion modules operate in different operating states to perform voltage conversion and output. When the internal main charge pump of the main charge pump module operates in the first operating mode, the main drive signal output by the main charge pump module supports bit programming of the antifuse;

[0012] When the main charge pump operates in the second operating mode, all voltage conversion modules operate in the same operating state, the main charge pump directly transmits the acquired second external voltage, and the main drive signal output by the main charge pump module when the internal main charge pump operates in the second operating mode supports byte programming of the anti-fuse; the second external voltage is higher than the first external voltage.

[0013] A further technical solution is that, when the main charge pump operates in the first operating mode, in the main charge pump:

[0014] The first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module are both connected to the working clock CLK0 of the main charge pump, the second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are both connected to the working clock CLK0 of the main charge pump, and the third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are both connected to the first clock signal CLK1 of the main charge pump;

[0015] The first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump, the second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump, and the third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module are both connected to the third clock signal CLK3 of the main charge pump;

[0016] The first clock signal CLK1 and the working clock CLK0 are a pair of overlapping clocks, the second clock signal CLK2 and the third clock signal CLK3 are a pair of overlapping clocks, and the second clock signal CLK2 and the working clock CLK0 are a pair of inverted clocks.

[0017] A further technical solution is that the second clock signal CLK2 and the working clock CLK0 are a pair of non-overlapping inverted clocks, and CLK0 and CLK2 are simultaneously high level within a predetermined time period at the rising edge and the falling edge.

[0018] A further technical solution is that the main charge pump further includes OR gates I0 and I1 and two input selectors I2 and I3, one input terminal of I0 is connected to the mode control signal UTR, the other input terminal is connected to the second clock signal CLK2, and the output terminal of I0 is connected to the first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module; one input terminal of I1 is connected to the mode control signal UTR, the other input terminal is connected to the working clock CLK0, and the output terminal of I1 is connected to the first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module;

[0019] The second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are connected to the working clock CLK0, and the third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are connected to the first clock signal CLK1;

[0020] The first input terminal of I2 is connected to the second clock signal CLK2, the second input terminal is connected to the working clock CLK0, the output terminal of I2 is connected to the second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module, and the selection input terminal of I2 is connected to the mode control signal UTR;

[0021] The first input terminal of I3 is connected to the third clock signal CLK3, the second input terminal is connected to the first clock signal CLK1, the output terminal of I3 is connected to the third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module, and the selection input terminal of I3 is connected to the mode control signal UTR;

[0022] When the mode control signal UTR is 0, I2 outputs the second clock signal CLK2, I3 outputs the third clock signal CLK3, and the charge pump enters the first working mode;

[0023] When the mode control signal UTR is 1, I2 outputs the working clock CLK0, I3 outputs the first clock signal CLK1, and the charge pump enters the second working mode.

[0024] A further technical solution is that the feedback network includes a feedback voltage selection module, a comparator, and a voltage divider module respectively connected to the output end of each slave charge pump module, each voltage divider module outputs a voltage divider signal of the programming voltage of the connected slave charge pump module, the feedback voltage selection module includes multiple input ends and an output end, each input end of the feedback voltage selection module is respectively connected to each voltage divider module to obtain the voltage divider signal, the output end of the feedback voltage selection module is connected to the inverting input end of the comparator, and the non-inverting input end of the comparator is connected to the reference voltage;

[0025] The feedback voltage selection module selects and outputs a voltage-divided signal of the programming voltage of the slave charge pump module to the comparator, and the output end of the comparator outputs a selected feedback signal of the slave charge pump module to the main charge pump module as an enable signal of the main charge pump module, and the main charge pump module is enabled at a high level.

[0026] Its further technical solution is that the feedback voltage selection module includes several gating switch tubes, each of which is connected between a voltage divider module and the output end of the feedback voltage selection module, and the gating switch tube is controlled by the selection signal of the anti-fuse array connected to the charge pump module connected to the voltage divider module.

[0027] Its further technical solution is that the input end of each slave charge pump module is used to connect to the output end of the master charge pump module and obtain the main drive signal HV_M output by the master charge pump module, the drain of the NMOS tube MN0 is connected to the drain of the NMOS tube MN1 and is connected to the input end of the slave charge pump module; the source of MN0 is connected to the output end of the slave charge pump module for outputting the programming voltage HV_S; the source of MN1 is connected to the drain of the NMOS tube MN2, the gate of MN2 and the gate of the NMOS tube MN3, the gate of MN1 is connected to the gate of MN0 and the source of MN2, the drain and source of MN3 are connected and connected to the working clock of the master charge pump module.

[0028] The beneficial technical effects of the present invention are:

[0029] The present application discloses an anti-fuse programming control circuit based on a master-slave charge pump structure. The anti-fuse programming control circuit adopts a structure combining a master charge pump module and a slave charge pump module. The slave charge pump module is arranged closely following the connected anti-fuse array and uses a feedback network for feedback, so that the master charge pump module can timely adjust the programming voltage of each slave charge pump module, thereby providing an accurate programming voltage to the anti-fuse array, which is beneficial to improving the consistency of the resistance value after anti-fuse programming and optimizing performance.

[0030] The main charge pump module operates simultaneously through four parallel, four-phase main charge pumps to ensure the current required for antifuse programming. This antifuse programming control circuit offers dual-mode operation, enabling bit-by-bit programming. This eliminates the need for external high voltage, as the programming high voltage is provided entirely by the internal master and slave charge pump modules. Byte-by-byte programming is also possible. In this case, the main charge pump's "transparent transmission" technology seamlessly transmits the high voltage supplied by an external pin to the antifuse for programming, improving programming efficiency. The flexible switching between dual-mode operation modes accommodates diverse programming needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a circuit structure diagram of the anti-fuse programming control circuit of the present application.

[0032] Figure 2 FIG. 4 is a clock phase diagram of the operating clocks of the four main charge pumps in the main charge pump module.

[0033] Figure 3 This is a circuit diagram of a main charge pump.

[0034] Figure 4 This is a clock phase diagram of each clock signal in a main charge pump.

[0035] Figure 5 This is a circuit diagram of a charge pump module.

[0036] Figure 6 FIG. 4 is a structural diagram of a feedback network in an embodiment. DETAILED DESCRIPTION

[0037] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0038] This application discloses an anti-fuse programming control circuit based on a master-slave charge pump structure. Figure 1 The antifuse programming control circuit includes a master charge pump module, several slave charge pump modules and a feedback network. The master charge pump module obtains the external voltage VIN and connects to each slave charge pump module. Each slave charge pump module is connected to an antifuse array, such as Figure 1 The charge pumps 0 to 15 are shown to be connected to the antifuse arrays BANK0 to BANK15, respectively. For example, each antifuse array is a 16K-bit MTM memory array, which actually includes word lines WL and bit lines BL, which are not described in detail in this application.

[0039] The feedback network outputs a corresponding feedback signal FB from each slave charge pump module to the master charge pump module based on the programming voltage output by the slave charge pump module to the connected antifuse array. The master charge pump module adjusts the main drive signal HV_M provided to each slave charge pump module based on the corresponding feedback signal to stabilize the programming voltage output by each slave charge pump module. In one embodiment, the feedback signal FB serves as an enable signal for the master charge pump module. When the master charge pump module receives a valid feedback signal FB from a slave charge pump module, it is enabled to operate. The master charge pump module outputs the main drive signal HV_M to the slave charge pump module, causing the slave charge pump module to operate normally and increase the programming voltage. Otherwise, the master charge pump module stops operating when the feedback signal FB is inactive.

[0040] The slave charge pump modules in this application utilize a distributed layout. Each slave charge pump module is positioned no more than a predetermined distance from the antifuse array to which it is connected. This means that each slave charge pump module is close to the antifuse array to which it is connected, and its operating time is synchronized with that of the antifuse array to which it is connected. This layout, unlike traditional charge pump layouts, effectively addresses the significant difference in programming voltage between the nearest and farthest antifuse arrays in traditional layouts, ensuring that all antifuse arrays receive precise programming voltages.

[0041] The current required for antifuse programming is generally large, usually 8mA / bit. The main charge pump module needs to provide the main drive signal HV_M of the current value required for antifuse programming. In one embodiment, the main charge pump module is implemented using an existing circuit structure that can provide the main drive signal HV_M of the current value required for antifuse programming. Or in another embodiment, the main charge pump module includes four main charge pumps connected in parallel and working simultaneously, and the main charge pump module provides the main drive signal HV_M of the current value required for antifuse programming through the four main charge pumps. In this embodiment, each main charge pump provides a driving capability of 2mA@9V, and the main charge pump module provides a total driving capability of 8mA@9V through the four main charge pumps, which meets the programming requirements of the antifuse array. The working clocks of the four main charge pumps are respectively recorded as CLK0[0], CLK0[1], CLK0[2] and CLK0[3]. The phase difference between the working clocks of each main charge pump is 90°. Please refer to Figure 2 , so that there can be a driving output in every 360° clock cycle.

[0042] Please refer to Figure 3Each main charge pump includes a first voltage conversion module, a second voltage conversion module, a third voltage conversion module and a fourth voltage conversion module cascaded in sequence. The input end of the first voltage conversion module is connected to the input end of the main charge pump for obtaining the external voltage VIN, and the output end of the fourth voltage conversion module is connected to the output end of the main charge pump for outputting the main drive signal HV_M.

[0043] The circuit structure of the four voltage conversion modules is the same. Figure 3 Taking the first voltage conversion module within the dashed box as an example, each voltage conversion module includes NMOS transistors N0, N4, N8, N9, N16, and N17. The drain of N8, the drain of N9, and the drain of N4 are all connected and serve as the input of the voltage conversion module. The gate of N8, the source of N9, the gate of N17, and the gate of N4 are all connected. The gate of N9, the source of N8, and the gate of N16 are all connected. The source of N4 is connected to the gate of N0 and serves as the output of the voltage conversion module. The drain and source of N0 are connected and serve as the first clock terminal of the voltage conversion module. The drain and source of N16 are connected and serve as the second clock terminal of the voltage conversion module. The drain and source of N17 are connected and serve as the third clock terminal of the voltage conversion module. N8, N9, N16, and N17 form a voltage stacker, with N0 used for charge storage. The purpose of the voltage stacker is to increase the voltage at the gate of the charge transfer transistor N4, thereby improving transfer efficiency. In order to improve the driving capability of the charge pump, each level of voltage conversion module inside the charge pump is implemented with NMOS tubes. Figure 3 Other symbols are used to represent the NMOS transistors in other voltage conversion modules.

[0044] Each clock terminal of each voltage conversion module is controlled by a clock signal determined by the working clock of the main charge pump. Each main charge pump in the present application has two working modes: a first working mode and a second working mode, and each main charge pump operates in the same working mode, so that the entire main charge pump module also operates in this working mode, that is, all main charge pumps operate in the first working mode, so that the entire main charge pump module also operates in the first working mode, or all main charge pumps operate in the second working mode, so that the entire main charge pump module also operates in the second working mode. Each main charge pump operates in the first working mode or the second working mode according to the received mode control signal UTR.

[0045] (1) When the main charge pump operates in the first operating mode, the main charge pump obtains a first external voltage, and two adjacent voltage conversion modules operate in different operating states to perform voltage conversion and output. The main drive signal output by the main charge pump module when the internal main charge pump operates in the first operating mode supports bit programming of the antifuse. The first external voltage is generally a voltage less than the voltage value required for antifuse programming. In one embodiment, the first external voltage is 5V, and the main charge pump converts the first external voltage to 9.5V for output, meeting the requirements of bit programming of the antifuse.

[0046] In each main charge pump, the first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module are both connected to the main charge pump's operating clock CLK0. The second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are both connected to the main charge pump's operating clock CLK0. The third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are both connected to the main charge pump's first clock signal CLK1.

[0047] The first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump. The second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump. The third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module are both connected to the third clock signal CLK3 of the main charge pump.

[0048] Among them, CLK1, CLK2 and CLK3 are all determined by the working clock CLK0, such as Figure 4 As shown, the first clock signal CLK1 and the working clock CLK0 are a pair of overlapping clocks. The second clock signal CLK2 and the third clock signal CLK3 are a pair of overlapping clocks. The second clock signal CLK2 and the working clock CLK0 are a pair of inverted clocks. Figure 3 and Figure 4 The main charge pump clock is Figure 2 For example, CLK0[0] in the charge pump is written as CLK0[0], CLK1[0], CLK2[0] and CLK3[0]. Figure 2 The main charge pump of CLK0[1] in the figure is written as CLK0[1], CLK1[1], CLK2[1] and CLK3[1] respectively, and so on for the others.

[0049] Further, such as Figure 4As shown, the second clock signal CLK2 and the working clock CLK0 in a charge pump are a pair of non-overlapping inverted clocks. CLK0 and CLK2 are simultaneously high within a predetermined time length T at the rising edge and the falling edge, thereby reducing the loss of charge and improving the transmission efficiency of each voltage conversion module.

[0050] (2) When the main charge pump operates in the second working mode, all voltage conversion modules operate in the same working state, and the main charge pump directly transmits the second external voltage obtained. The main drive signal output by the main charge pump module when the main charge pump operates in the second working mode supports byte programming of the antifuse. The second external voltage is higher than the first external voltage, and the second external voltage is generally a voltage equal to the voltage value required for antifuse programming. In this case, based on Figure 3 In the structure shown, the voltage superimposed on the four-stage voltage conversion module operates in the same state. The gate voltages of the charge transfer transistors (N4, N5, N6, and N7) used for charge transmission in the four voltage conversion modules are all the same: the second external voltage superimposed on the high-level voltage of the clock signal. This eliminates threshold voltage loss when transmitting the second external voltage, a process known as transparent transmission. For example, in one example, the second external voltage is 9.5V and the high-level voltage of the clock signal is 3.3V. The gate voltages of N4, N5, N6, and N7 are all 12.8V. There is no threshold voltage loss when transmitting the 9.5V second external voltage, and the externally input second external voltage is directly transparently transmitted to the slave charge pump module. This compensates for the on-chip charge pump's inability to deliver tens of mA of current, satisfies the byte-by-byte programming capability of the antifuse array, and improves programming efficiency.

[0051] For details, please refer to Figure 3 Each main charge pump further includes OR gates I0 and I1 and two input selectors I2 and I3. I0 has one input connected to the mode control signal UTR and another input connected to the second clock signal CLK2. The output of I0 is connected to the first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module. I1 has one input connected to the mode control signal UTR and another input connected to the operating clock CLK0. The output of I1 is connected to the first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module.

[0052] The second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are connected to the working clock CLK0 , and the third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are connected to the first clock signal CLK1 .

[0053] The first input terminal of I2 is connected to the second clock signal CLK2, the second input terminal is connected to the working clock CLK0, the output terminal of I2 is connected to the second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module, and the selection input terminal of I2 is connected to the mode control signal UTR.

[0054] The first input terminal of I3 is connected to the third clock signal CLK3, the second input terminal is connected to the first clock signal CLK1, the output terminal of I3 is connected to the third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module, and the selection input terminal of I3 is connected to the mode control signal UTR.

[0055] When the mode control signal UTR is 0, I2 outputs the second clock signal CLK2, I3 outputs the third clock signal CLK3, I0 outputs CLK2, and I1 outputs CLK0. At this time, the charge pump enters the first working mode.

[0056] When the mode control signal UTR is 1, the outputs of I0 and I1 are permanently 1. The charge storage modules N0, N1, N2, and N3 in the four voltage conversion modules no longer require a bootstrap voltage. I2 outputs the operating clock CLK0, and I3 outputs the first clock signal CLK1. This results in the four voltage conversion modules operating in the same state, and the charge pump enters its second operating mode.

[0057] Please refer to Figure 5 , the input end of each slave charge pump module is used to connect to the output end of the master charge pump module and obtain the main drive signal HV_M output by the master charge pump module, the drain of the NMOS tube MN0 is connected to the drain of the NMOS tube MN1 and is connected to the input end of the slave charge pump module. The source of MN0 is connected to the output end of the slave charge pump module for outputting the programming voltage HV_S. The source of MN1 is connected to the drain of the NMOS tube MN2, the gate of MN2 and the gate of the NMOS tube MN3, the gate of MN1 is connected to the gate of MN0 and the source of MN2, the drain and source of MN3 are connected and connected to the working clock of the master charge pump module. The working clock of the master charge pump module here refers to the working clock of any master charge pump in the master charge pump module, that is, it can be Figure 2 Any one of CLK0[0], CLK0[1], CLK0[2] and CLK0[3], Figure 5 Take connecting CLK0[0] as an example.

[0058] Please refer to Figure 6 , Figure 6 Relative to Figure 1The word lines and bit lines are omitted. The feedback network includes a feedback voltage selection module, a comparator CMP, and a voltage divider module connected to the output of each slave charge pump module. The voltage divider module includes resistors R1 and R2 connected in series. One end of the series circuit is connected to the output of the slave charge pump module and the other end is grounded. The common end of R1 and R2 outputs a voltage divider signal VFB1-VFB15 of the programming voltage of the connected slave charge pump module.

[0059] The feedback voltage selection module includes multiple inputs and one output. Each input of the feedback voltage selection module is connected to a voltage divider module to obtain voltage divider signals VFB1-VFB15. The output of the feedback voltage selection module is connected to the inverting input of a comparator CMP, while the non-inverting input of the comparator CMP is connected to a reference voltage VREF. The feedback voltage selection module selects and outputs a voltage divider signal from the programming voltage of the charge pump module to the comparator. Specifically, the feedback voltage selection module includes several gate switches, each connected between a voltage divider module and the output of the feedback voltage selection module. The gate switches are controlled by a selection signal from the antifuse arrays BANK0-BANK15 connected to the charge pump module, provided by an address decoder. For example, the switch connected to the voltage divider module of charge pump module 3 obtains voltage divider signal VFB3, and this switch is controlled by the selection signal from the antifuse array BANK3.

[0060] The output end of the comparator CMP outputs a selected feedback signal FB from the charge pump module to the main charge pump module as an enable signal of the main charge pump module, and the main charge pump module is enabled at a high level. Figure 6 In this structure, when the feedback voltage selection module selects a slave charge pump module and outputs its corresponding divided voltage signal to the comparator, and if the output divided voltage signal is lower than the reference voltage VREF, the comparator outputs a high-level feedback signal FB, enabling the main charge pump module. The main charge pump module starts operating, increasing the programming voltage HV_S output by the selected slave charge pump module to achieve stability. Otherwise, the comparator outputs a low-level feedback signal FB.

[0061] The above description is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. An anti-fuse programming control circuit based on a master-slave charge pump structure, characterized in that: The antifuse programming control circuit includes a master charge pump module, a plurality of slave charge pump modules, and a feedback network. The master charge pump module obtains an external voltage and connects to each slave charge pump module. Each slave charge pump module is connected to an antifuse array, and the layout position of each slave charge pump module is within a predetermined distance from the layout position of the antifuse array to which it is connected. The feedback network outputs a feedback signal corresponding to each slave charge pump module to the master charge pump module based on the programming voltage output by each slave charge pump module to the connected antifuse array, and the master charge pump module adjusts the main drive signal provided to the slave charge pump module based on the feedback signal corresponding to each slave charge pump module to stabilize the programming voltage output by the slave charge pump module; The main charge pump module includes four main charge pumps connected in parallel and working simultaneously, the phase difference between the working clocks of each main charge pump is 90 degrees, and the main charge pump module provides a main drive signal of the current value required for antifuse programming through the four main charge pumps; Each main charge pump includes a first voltage conversion module, a second voltage conversion module, a third voltage conversion module and a fourth voltage conversion module connected in cascade in sequence. The input end of the first voltage conversion module is connected to the input end of the main charge pump for obtaining an external voltage. The output end of the fourth voltage conversion module is connected to the output end of the main charge pump for outputting a main drive signal. Each voltage conversion module includes NMOS tubes N0, N4, N8, N9, N16 and N17. The drain of N8, the drain of N9 and the drain of N4 are all connected and serve as the input end of the voltage conversion module. The gate of N8, The source of N9, the gate of N17, and the gate of N4 are all connected; the gate of N9, the source of N8, and the gate of N16 are all connected; the source of N4 and the gate of N0 are connected and serve as the output terminal of the voltage conversion module; the drain and source of N0 are connected and serve as the first clock terminal of the voltage conversion module; the drain and source of N16 are connected and serve as the second clock terminal of the voltage conversion module; the drain and source of N17 are connected and serve as the third clock terminal of the voltage conversion module; each clock terminal of each voltage conversion module is respectively controlled by a clock signal determined by the working clock of the main charge pump; Each main charge pump operates in a first operating mode or a second operating mode according to a received mode control signal; When the main charge pump operates in the first operating mode, the main charge pump obtains a first external voltage, and two adjacent voltage conversion modules operate in different operating states to perform voltage conversion and output. The main drive signal output by the main charge pump module when the internal main charge pump operates in the first operating mode supports bit programming of the anti-fuse; when the main charge pump operates in the second operating mode, all voltage conversion modules operate in the same operating state, and the main charge pump directly transmits the obtained second external voltage out. The main drive signal output by the main charge pump module when the internal main charge pump operates in the second operating mode supports byte programming of the anti-fuse; the second external voltage is higher than the first external voltage.

2. The anti-fuse programming control circuit according to claim 1, wherein: When the main charge pump operates in the first operating mode, in the main charge pump: The first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module are both connected to the working clock CLK0 of the main charge pump, the second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are both connected to the working clock CLK0 of the main charge pump, and the third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are both connected to the first clock signal CLK1 of the main charge pump; The first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump, the second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module are both connected to the second clock signal CLK2 of the main charge pump, and the third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module are both connected to the third clock signal CLK3 of the main charge pump; The first clock signal CLK1 and the working clock CLK0 are a pair of overlapping clocks, the second clock signal CLK2 and the third clock signal CLK3 are a pair of overlapping clocks, and the second clock signal CLK2 and the working clock CLK0 are a pair of inverted clocks.

3. The anti-fuse programming control circuit according to claim 2, wherein: The second clock signal CLK2 and the working clock CLK0 are a pair of non-overlapping inverse clocks. CLK0 and CLK2 are simultaneously at a high level within a predetermined time period at the rising edge and the falling edge.

4. The anti-fuse programming control circuit according to claim 2, wherein: The main charge pump further includes OR gates I0 and I1 and two input selectors I2 and I3, one input terminal of I0 is connected to the mode control signal UTR, the other input terminal is connected to the second clock signal CLK2, and the output terminal of I0 is connected to the first clock terminal of the second voltage conversion module and the first clock terminal of the fourth voltage conversion module; one input terminal of I1 is connected to the mode control signal UTR, the other input terminal is connected to the working clock CLK0, and the output terminal of I1 is connected to the first clock terminal of the first voltage conversion module and the first clock terminal of the third voltage conversion module; The second clock terminal of the first voltage conversion module and the second clock terminal of the third voltage conversion module are connected to the working clock CLK0, and the third clock terminal of the first voltage conversion module and the third clock terminal of the third voltage conversion module are connected to the first clock signal CLK1; The first input terminal of I2 is connected to the second clock signal CLK2, the second input terminal is connected to the working clock CLK0, the output terminal of I2 is connected to the second clock terminal of the second voltage conversion module and the second clock terminal of the fourth voltage conversion module, and the selection input terminal of I2 is connected to the mode control signal UTR; The first input terminal of I3 is connected to the third clock signal CLK3, the second input terminal is connected to the first clock signal CLK1, the output terminal of I3 is connected to the third clock terminal of the second voltage conversion module and the third clock terminal of the fourth voltage conversion module, and the selection input terminal of I3 is connected to the mode control signal UTR; When the mode control signal UTR is 0, I2 outputs the second clock signal CLK2, I3 outputs the third clock signal CLK3, and the charge pump enters the first working mode; When the mode control signal UTR is 1, I2 outputs the working clock CLK0, I3 outputs the first clock signal CLK1, and the charge pump enters the second working mode.

5. The anti-fuse programming control circuit according to claim 1, wherein: The feedback network includes a feedback voltage selection module, a comparator, and a voltage divider module respectively connected to the output end of each slave charge pump module, each voltage divider module outputs a voltage divider signal of the programming voltage of the connected slave charge pump module, the feedback voltage selection module includes multiple input ends and an output end, each input end of the feedback voltage selection module is respectively connected to each voltage divider module to obtain the voltage divider signal, the output end of the feedback voltage selection module is connected to the inverting input end of the comparator, and the non-inverting input end of the comparator is connected to the reference voltage; The feedback voltage selection module selects and outputs a voltage-divided signal of the programming voltage of the slave charge pump module to the comparator, and the output end of the comparator outputs a selected feedback signal of the slave charge pump module to the main charge pump module as an enable signal of the main charge pump module, and the main charge pump module is enabled at a high level.

6. The anti-fuse programming control circuit according to claim 5, wherein: The feedback voltage selection module includes a plurality of gate switch tubes, each of which is connected between a voltage divider module and the output end of the feedback voltage selection module. The gate switch tube is controlled by a selection signal of an anti-fuse array connected to a charge pump module and connected to the voltage divider module.

7. The anti-fuse programming control circuit according to claim 1, wherein: The input end of each slave charge pump module is used to connect to the output end of the master charge pump module and obtain the main drive signal HV_M output by the master charge pump module. The drain of the NMOS tube MN0 is connected to the drain of the NMOS tube MN1 and is connected to the input end of the slave charge pump module; the source of MN0 is connected to the output end of the slave charge pump module for outputting the programming voltage HV_S; the source of MN1 is connected to the drain of the NMOS tube MN2, the gate of MN2 and the gate of the NMOS tube MN3, the gate of MN1 is connected to the gate of MN0 and the source of MN2, and the drain and source of MN3 are connected and connected to the working clock of the master charge pump module.

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