Method for manufacturing si c substrate

Abstract

The present application provides a novel technique for manufacturing a SiC substrate, which can remove strain and achieve a flat surface to the same degree as in the case of CMP. The technique etches a SiC substrate having an arithmetic average roughness (Ra) of 100 nm or less of a surface under an atmosphere containing Si and C elements.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for manufacturing a SiC substrate. BACKGROUND

[0002] A silicon carbide (SiC) wafer is formed by slicing a boule of a SiC single crystal. At the surface of the SiC substrate after slicing, there is a surface layer (hereinafter referred to as a processed metamorphic layer) having a strain or a scratch of the crystal introduced at the time of slicing. In order not to reduce the yield in a device manufacturing step, it is necessary to remove this processed metamorphic layer.

[0003] In order to obtain a SiC substrate that is epitaxial-ready in which the processed metamorphic layer can be removed and epitaxial growth for SiC device manufacturing is performed, conventionally, mechanical processing is performed. This mechanical processing generally goes through the following stages: a rough grinding step using abrasive grains such as diamond, a fine grinding step using abrasive grains having a smaller particle diameter than the abrasive grains used in the rough grinding step, and a chemical mechanical polishing (CMP) step in which the mechanical action of a polishing pad and the chemical action of a slurry are combined to perform polishing (for example, Patent Literature 1).

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2015-5702 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] In order to obtain a SiC substrate having an epitaxial surface, conventionally, a chemical mechanical polishing (CMP) is generally performed. However, there is a problem of high cost associated with CMP. In addition, there is a problem of introducing new strain due to CMP.

[0009] In view of the above problems, the present application aims to provide a novel technology for manufacturing a SiC substrate that can remove strain and achieve a flat surface to the same degree as in the case where CMP is performed.

[0010] MEANS FOR SOLVING THE PROBLEMS

[0011] The present application that solves the above problems is a method for manufacturing a SiC substrate, including: an etching step of etching a SiC substrate having an arithmetic mean roughness (Ra) of 100 nm or less at the surface in an atmosphere containing Si element and C element.

[0012] By etching a SiC substrate having an arithmetic average roughness (Ra) of 100 nm or less on the surface in an atmosphere containing Si element and C element, a SiC substrate having a surface from which strain is removed and which is extremely smooth (smooth and free from unevenness) can be produced.

[0013] In a preferred embodiment of the present application, the etching step is performed on a SiC substrate having an arithmetic average roughness (Ra) of 2 nm or less on the surface in an atmosphere containing Si element and C element.

[0014] By etching a SiC substrate having an arithmetic average roughness (Ra) of 2 nm or less on the surface in an atmosphere containing Si element and C element, a SiC substrate having a more planar surface can be obtained.

[0015] The present application also relates to a method for producing a SiC substrate, comprising: a planarization step of planarizing a surface of a SiC substrate so as to have an arithmetic average roughness (Ra) of 100 nm or less; and an etching step of etching the SiC substrate after the planarization step in an atmosphere containing Si element and C element.

[0016] By etching a SiC substrate having an arithmetic average roughness (Ra) of 100 nm or less on the surface in an atmosphere containing Si element and C element, a SiC substrate having a surface from which strain is removed and which is extremely smooth can be produced.

[0017] In a preferred embodiment of the present application, in the planarization step, a surface of a SiC substrate is planarized so as to have an arithmetic average roughness (Ra) of 2 nm or less.

[0018] By etching a SiC substrate having an arithmetic average roughness (Ra) of 2 nm or less on the surface in an atmosphere containing Si element and C element, a SiC substrate having a more planar surface can be obtained.

[0019] The present application also relates to a method for producing a SiC substrate, comprising: a planarization step of planarizing a surface of a SiC substrate using abrasive grains having an average abrasive grain particle diameter of 10 μm or less; and an etching step of etching the SiC substrate after the planarization step in an atmosphere containing Si element and C element.

[0020] By etching a SiC substrate planarized using abrasive grains having an average abrasive grain particle diameter of 10 μm or less in an atmosphere containing Si element and C element, a SiC substrate having a surface from which strain is removed and which is extremely smooth can be obtained.

[0021] In a preferred embodiment of the present application, the average abrasive grain particle diameter of the abrasive grains is 0.5 μm or less.

[0022] By etching a SiC substrate that has been planarized using abrasive grains having an average grain size of 0.5 μm or less in an atmosphere containing Si and C elements, a SiC substrate having a more planar surface can be obtained.

[0023] In a preferred embodiment of the present application, the etching step includes a step of etching the SiC substrate by opposing the SiC substrate and the SiC material and heating them so that a temperature gradient is formed between the SiC substrate and the SiC material.

[0024] In a preferred embodiment of the present application, the etching step includes a step of disposing the SiC substrate into which a crack has been introduced in a quasi-enclosed space having a Si / C atomic ratio of 1 or less and heating it.

[0025] In a preferred embodiment of the present application, no mechanical processing of the surface of the SiC substrate is performed after the etching step.

[0026] In a preferred embodiment of the present application, no cleaning step of cleaning the surface of the SiC substrate with a liquid agent is performed after the etching step.

[0027] In a preferred embodiment of the present application, an epitaxial growth step of forming an epitaxial layer at the surface of the SiC substrate is performed after the etching step.

[0028] In a preferred embodiment of the present application, the etching step is a step of etching a SiC single crystal original substrate and manufacturing a SiC single crystal seed substrate, and after the etching step, a crystal ingot formation step of causing the SiC single crystal seed substrate to undergo crystal growth to obtain a crystal ingot is included.

[0029] Thus, the present application can be applied to the manufacture of a SiC crystal ingot.

[0030] In a preferred embodiment of the present application, the SiC substrate is 2 inches (about 5.08 cm) or more.

[0031] Effects of the Invention

[0032] According to the disclosed technology, a SiC substrate that has been removed of strain and has an extremely smooth surface can be manufactured.

[0033] Further, according to the present application, a step of chemical mechanical polishing (CMP) that is costly can be reduced, and a SiC device can be manufactured industrially advantageously.

[0034] Other technical problems to be solved, features, and advantages will become apparent by reading the following detailed description in conjunction with the drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1is a schematic view showing manufacturing steps of a SiC substrate of one embodiment.

[0036] Figure 2 is an explanatory view of a manufacturing apparatus of a SiC substrate of one embodiment.

[0037] Figure 3 is a schematic view of a main vessel and a high-melting-point vessel of one embodiment.

[0038] Figure 4 is an explanatory view showing an outline of etching in an etching step.

[0039] Figure 5 is a schematic view showing one embodiment in which the present application is applied to SiC ingot manufacturing.

[0040] Figure 6 is a cross-sectional SEM-EBSD imaging image of a test piece 1 before and after etching in a test example.

[0041] Figure 7 SEM images (magnification 3000x) of surfaces of test pieces 1 to 4 before and after etching in a test example are shown, in which the upper stage is an initial state before etching, the middle stage is a surface after etching according to Condition A, and the lower stage is a surface after etching according to Condition B.

[0042] Figure 8 is a graph showing results of the test piece 1 in the test example, in which the vertical axis represents the arithmetic average roughness (Ra) and the horizontal axis represents the etching amount, the temperature shown near each plotted point represents the heating temperature in the etching step, and the black arrow in the graph represents the depth of a strain present in the SiC substrate before etching.

[0043] Figure 9 is a graph showing results of the test piece 3 in the test example, in which the vertical axis represents the arithmetic average roughness (Ra) and the horizontal axis represents the etching amount, the temperature shown near each plotted point represents the heating temperature in the etching step, and the black arrow in the graph represents the depth of a strain present in the SiC substrate before etching.

[0044] Figure 10 is a graph showing results of the test piece 4 in the test example, in which the vertical axis represents the arithmetic average roughness (Ra) and the horizontal axis represents the etching amount, the temperature shown near each plotted point represents the heating temperature in the etching step, and the black arrow in the graph represents the depth of a strain present in the SiC substrate before etching.

[0045] Figure 11 is an explanatory view showing manufacturing steps of a conventional SiC substrate.

[0046] Figure 12This is a conceptual diagram of the surface of a SiC substrate after general mechanical processing, viewed from a cross-section. Detailed Implementation

[0047] This invention is a method for manufacturing SiC substrates. The term "SiC substrate" as used in this specification, in addition to the so-called "SiC wafer" cut from a crystal ingot, also broadly includes "SiC seed substrates" used in the manufacture of SiC crystal ingots, and "SiC single crystal substrates" that are in a state further prior to the "SiC seed substrates" used in the crystal ingot formation step.

[0048] Hereinafter, the present invention will be described using embodiments for manufacturing "SiC wafers" and embodiments for manufacturing "SiC single-crystal seed substrates".

[0049] [SiC wafer manufacturing method]

[0050] Reference Figure 1 The method for manufacturing SiC wafers according to the present invention will be described in more detail. Preferred embodiments are shown in the accompanying drawings. However, the invention can be implemented in many different ways and is not limited to the embodiments described in this specification.

[0051] Furthermore, in understanding this invention, it is considered useful to compare it with conventional SiC wafer manufacturing steps. Therefore, appropriate reference is made. Figure 11 While comparing each step of the SiC wafer manufacturing method with that of conventional SiC wafer manufacturing methods, each step of the SiC wafer manufacturing method of the present invention will be described.

[0052] For SiC single crystals, which form the basis of SiC semiconductors, the raw materials are sublimated at temperatures above 2000℃ to artificially create ingots as crystal blocks. The material properties of SiC single crystals are such that they are considered to be second only to diamond and boron carbide in hardness, with high hardness and chemical and thermal stability sufficient for use as polishing materials. They also have crystal orientation and direction, thus exhibiting the cleavage properties characteristic of brittle materials, making them very difficult to process.

[0053] To form a semiconductor on the surface of the material, a planarization step S20 is conventionally performed after slicing a SiC wafer from a single-crystal ingot via a slicing step S1. In conventional methods, the planarization step S20 typically includes a grinding step S21 to flatten the ripples, a rough grinding step S22 to remove the processed altered layer 11, and a fine grinding step S23. Figure 11 ).

[0054] Then, for the SiC wafer after planarization step S20, a final chemical mechanical polishing (CMP) step S41, which enables strain-free processing, is generally performed. Figure 11 ).

[0055] exist Figure 1 The outline of the SiC wafer manufacturing method of the present invention is shown below. Figure 1 As shown, the SiC wafer manufacturing method of the present invention performs an etching step S31 after a planarization step is performed until a predetermined surface roughness is achieved, or after a planarization step is performed using abrasive grains with a predetermined particle size or smaller.

[0056] Because of this structure, it is not necessary to perform all the steps of grinding step S21, rough grinding step S22, and fine grinding step S23 in this invention. Figure 1 (Right side).

[0057] For example, if a SiC wafer with a predetermined surface roughness can be obtained through the grinding step S21, then the etching step S31 can be performed subsequently without going through the coarse grinding step S22 or the fine grinding step S23.

[0058] Of course, the etching step S31 can also be performed after all the grinding steps S21, rough grinding steps S22 and fine grinding steps S23.

[0059] Alternatively, the etching step S31 can be performed only on SiC wafers with a predetermined surface roughness, regardless of the type of processing steps performed on the SiC wafer.

[0060] Furthermore, the SiC substrates to which the present invention can be applied include, without limitation, SiC substrates with an offset angle and SiC substrates without an offset angle.

[0061] Furthermore, the application of this invention is not limited even if the SiC substrate is any crystal polymorph such as 4H-SiC, 6H-SiC, or 3C-SiC.

[0062] Furthermore, the main surface (the surface to be processed) of the SiC substrate to which the present invention is applied can be either the Si surface (0001) or the C surface (000-1).

[0063] also, Figure 12A conceptual diagram is shown when viewing the surface of a wafer after mechanical processing in cross-section. Typically, a processing-modified layer 11 containing a cracked layer 111 with numerous cracks (scratches) or a strained layer 112 that has undergone strain in the lattice remains on the surface of a SiC wafer 10 that has been mechanically processed as in conventional methods.

[0064] In order not to reduce the yield during the device manufacturing process, the processing modification layer 11 needs to be removed. That is, preferably, the bulk layer 12 under the processing modification layer 11, which does not introduce cracks or lattice strain caused by surface processing, is exposed.

[0065] According to the SiC wafer manufacturing method of the present invention, by using thermal etching to remove the processing-modified layer 11, the bulk layer 12 that has not introduced cracks or lattice strain can be exposed.

[0066] The manufacturing method of SiC wafer of the present invention will be described below according to one embodiment.

[0067] <1> Slicing step S1

[0068] The slicing step S1 is the step of cutting SiC wafers from SiC ingots. Examples of slicing methods for the slicing step S1 include: multi-wire sawing that cuts the ingot at predetermined intervals by reciprocating multiple metal wires, or electrical discharge machining that cuts by intermittently generating plasma discharge, or laser cutting that forms a layer that serves as the cutting base point by irradiating and converging a laser in the ingot.

[0069] <2> Flattening step S20

[0070] like Figure 1 As shown, the planarization step S20 of the present invention includes: planarization to a predetermined roughness below a certain level, and planarization using abrasive grains with a predetermined particle size below a certain level. These methods are related to each other.

[0071] First, the method of planarization using abrasive grains will be explained.

[0072] (1) Planarization using abrasive particles

[0073] Examples of abrasive grains include diamond, boron carbide (B4C), silicon carbide (SiC), and aluminum oxide (Al2O3).

[0074] As a planarization method in the planarization step S20, examples include: free abrasive grain processing (grinding, polishing, etc.) where fine abrasive grains are poured onto a platform while processing, and fixed abrasive grain processing (grinding, grinding, etc.) where abrasive grains are embedded in a bonding material using a grinding stone.

[0075] When using a fixed abrasive grain method, examples of rough grinding or fine grinding using diamond abrasive grains can be given.

[0076] Furthermore, when using free abrasive particles, it is desirable for the abrasive particles to drip as a mixture (slurry) with water or a dispersant.

[0077] The processing apparatus used in this step can be a general-purpose processing apparatus used in conventional free abrasive processing.

[0078] The average abrasive grain size of the abrasive grains used in the planarization step S20 is preferably 10 μm or less, more preferably 9 μm or less, more preferably 8 μm or less, more preferably 7 μm or less, more preferably 6 μm or less, more preferably 5 μm or less, more preferably 4 μm or less, more preferably 3 μm or less, even more preferably 2 μm or less, even more preferably 1 μm or less, even more preferably 0.8 μm or less, even more preferably 0.6 μm or less, even more preferably 0.5 μm or less, even more preferably 0.4 μm or less, even more preferably 0.3 μm or less.

[0079] By performing a planarization step S320 and an etching step S31 using abrasive grains with an average abrasive grain size within the above-mentioned numerical range, a SiC wafer with strain removed and a surface planarized to the same extent as after a chemical mechanical polishing step S41 can be obtained.

[0080] In particular, by using abrasive grains with an average abrasive grain size of less than 0.5 μm for planarization step S20 and etching step S31, SiC wafers with extremely flat surfaces can be manufactured. This implementation is also applicable to mass production processes.

[0081] There is no limitation on the size of the SiC substrate to which this invention can be applied. This invention can be applied to SiC substrates that are preferably 2 inches or larger, and more preferably 4 inches (about 10.16 cm) or larger.

[0082] Furthermore, when planarizing SiC wafers by grinding the surface with abrasive grains, a problem arises where flatness deviations occur on the same wafer due to the grinding location. This problem becomes significant, for example, when planarizing large-diameter SiC wafers of 6 inches (approximately 15.24 cm) or larger.

[0083] According to the present invention, the SiC wafer can be corrected by the subsequent etching step S31 for the flatness deviation caused by the planarization step S20 using abrasive particles.

[0084] In other words, the present invention is applicable to the processing of large-diameter SiC wafers of 6 inches or more, more preferably 8 inches (about 20.32 cm) or more.

[0085] In addition, when the average abrasive grain size is mentioned in this specification, it refers to the average grain size based on Japanese Industrial Standard (JIS) R6001-2:2017.

[0086] (2) Flattening to achieve a surface roughness below the predetermined level

[0087] In the planarization step S20, the planarization step S20 is performed such that the arithmetic mean roughness (Ra) is preferably 100 nm or less, more preferably 90 nm or less, more preferably 80 nm or less, more preferably 70 nm or less, more preferably 60 nm or less, more preferably 50 nm or less, more preferably 45 nm or less, more preferably 40 nm or less, more preferably 35 nm or less, more preferably 30 nm or less, more preferably 25 nm or less, more preferably 20 nm or less, more preferably 18 nm or less, more preferably 15 nm or less, more preferably 12 nm or less, more preferably 10 nm or less, more preferably 9 nm or less, more preferably 8 nm or less, more preferably 7 nm or less, more preferably 6 nm or less, more preferably 5 nm or less, more preferably 4 nm or less, more preferably 3 nm or less, further preferably 2 nm or less, further preferably 1.5 nm or less, and further preferably 1 nm or less.

[0088] By performing a planarization step S20 to achieve the surface roughness within the aforementioned numerical range, and then performing an etching step S31, a SiC wafer with strain removed and a surface planarized to the same extent as after a chemical mechanical polishing step S41 can be obtained.

[0089] Specifically, by performing a planarization step S20 to achieve an arithmetic mean roughness (Ra) of less than 2 nm, and then performing an etching step S31, a SiC wafer with an extremely flat surface can be manufactured. This implementation is also applicable to mass production processes.

[0090] Furthermore, in this specification, the arithmetic mean roughness (Ra) is based on the arithmetic mean roughness of Japanese Industrial Standard (JIS) B0601-2001. The arithmetic mean roughness (Ra) of the SiC substrate surface can be measured using an atomic force microscope (AFM) or a laser microscope.

[0091] In addition, when referred to as “arithmetic mean roughness (Ra)” unless otherwise specified in this specification, it refers to the arithmetic mean roughness (Ra) measured by AFM.

[0092] In the planarization step S20, as a means to achieve the surface roughness within the above-mentioned numerical range on the surface of the SiC wafer, it is preferable to use abrasive grains having the above-mentioned predetermined average abrasive grain size.

[0093] In addition to using abrasive particles, planarization step S20 can also be performed by various etching methods. Examples of planarization step S20 utilizing etching include Si vapor pressure etching.

[0094] <3> Cleaning step S51

[0095] like Figure 1 As shown, it is preferable to perform the cleaning step S51 after the planarization step S20. By removing organic and particulate contamination, oxide layers, and ionic contamination through the cleaning step S51 before the etching step S31, abnormal etching can be suppressed, and contamination of the etching furnace can be prevented.

[0096] RCA cleaning can be exemplified as a specific method for cleaning step S51.

[0097] <4> Etching step S31

[0098] Etching step S31 is a step of etching the SiC wafer after the planarization step S20 described above.

[0099] Furthermore, even without the planarization step S20, the etching step S31 can still be performed on the SiC wafer with a surface roughness within the aforementioned numerical range. For example, if the surface roughness of the SiC wafer obtained by the slicing step S1 is within the aforementioned numerical range, the etching step S31 can be performed after the slicing step S1 without the planarization step S20.

[0100] Etching step S31 is a step of etching a SiC wafer in an atmosphere containing Si and C elements.

[0101] More specifically, the etching step S31 is the step of heating the SiC wafer 10 and the SiC material relative to each other, transferring SiC elements and C elements from the SiC wafer 10 to the SiC material, and etching the SiC wafer 10.

[0102] The SiC material is composed of SiC, which can receive Si and C elements from the SiC wafer 10 by heating it relative to the SiC wafer 10. Examples include SiC containers or SiC substrates (SiC components). Furthermore, any polymorph can be used as the crystal polymorph of the SiC material, including polycrystalline SiC.

[0103] Hereinafter, as a preferred embodiment, the method of using the main body container 20 will be described, which can accommodate the SiC wafer 10 and is configured to function as a SiC material itself.

[0104] First, the structure of the apparatus that enables the etching step S31 will be described.

[0105] like Figure 2 As shown, the etching apparatus for etching step S31 includes: a main container 20 capable of housing the SiC wafer 10, and generating vapor pressures of gaseous species containing Si and gaseous species containing C in the internal space by heating; and a heating furnace 30 housing the main container 20, and heating it to generate vapor pressures of gaseous species containing Si in the internal space and to form a temperature gradient.

[0106] Furthermore, the main body container 20 has an etching space X1, which is formed by positioning a portion of the main body container 20 positioned on the low-temperature side of the temperature gradient relative to the SiC wafer 10 while the SiC wafer 10 is positioned on the high-temperature side of the temperature gradient.

[0107] In this specification, the surface on which the semiconductor element is fabricated in the SiC wafer 10 (specifically, the surface on which the epitaxial layer is deposited) is referred to as the main surface 101, and the surface opposite to the main surface 101 is referred to as the back surface 102. Furthermore, the main surface 101 and the back surface 102 are collectively referred to as surfaces, and the direction through the main surface 101 and the back surface 102 is referred to as the surface-back direction.

[0108] Additionally, as the main surface 101, a surface with an offset angle of a few degrees (e.g., 0.4 to 8°) from the (0001) surface or the (000-1) surface can be exemplified. (Also, in this specification, in the Miller index markings, the horizontal bar "-" indicates that the index is immediately following it).

[0109] The main container 20 only needs to have the following structure: capable of housing the SiC substrate 10, and generating vapor pressures of gaseous species containing Si and gaseous species containing C within its internal space during heat treatment. For example, the main container 20 can be made of a material containing polycrystalline SiC. In this embodiment, the entire main container 20 is made of polycrystalline SiC. By heating the main container 20 made of this material, vapor pressures of gaseous species containing Si and gaseous species containing C can be generated.

[0110] That is, it is desirable that the environment inside the main container 20, after heat treatment, is a vapor pressure environment of a mixed system of gaseous species containing Si and gaseous species containing C. Examples of the Si-containing gaseous species include Si, Si2, Si3, Si2C, SiC2, and SiC. Examples of the C-containing gaseous species include Si2C, SiC2, SiC, and C. In other words, the main container 20 is in a state where SiC-based gases exist.

[0111] Furthermore, this structure can be used as long as it generates vapor pressures of gaseous species containing Si and gaseous species containing C in the internal space during the heat treatment of the main container 20. For example, a structure in which polycrystalline SiC is exposed at a portion of the inner surface, or a structure in which polycrystalline SiC is separately disposed within the main container 20, can be shown.

[0112] like Figure 3 As shown, the main container 20 is a fitted container including an upper container 21 and a lower container 22 that can fit together. A small gap 23 is formed at the fitting part of the upper container 21 and the lower container 22, and is configured to allow air to be vented (vacuumed) from the main container 20 through the gap 23.

[0113] With this structure, it is preferable that a quasi-closed space is formed inside the main container 20. Furthermore, in this specification, "quasi-closed space" refers to a space capable of being evacuated inside the container, but capable of sealing off at least a portion of the vapor generated inside the container.

[0114] The main container 20 has an etching space X1, which is formed when a portion of the main container 20, positioned on the low-temperature side of the temperature gradient, is opposite to the SiC wafer 10 while the SiC wafer 10 is positioned on the high-temperature side of the temperature gradient. That is, by utilizing the temperature gradient provided in the furnace 30, the temperature of at least a portion of the main container 20 (e.g., the bottom surface of the lower container 22) is lower than that of the SiC wafer 10, thereby forming the etching space X1.

[0115] The etching space X1 is a space in which the Si and C atoms on the surface of the SiC wafer 10 are transported to the body container 20 by using the temperature difference between the SiC wafer 10 and the body container 20 as a driving force.

[0116] For example, the SiC wafer 10 is configured such that when comparing the temperature of the main surface 101 (or back surface 102) of the SiC wafer 10 with the temperature of the bottom surface of the lower container 22 opposite to the main surface 101, the temperature on the main surface 101 side is higher and the temperature on the bottom surface side of the lower container 22 is lower (see reference). Figure 4Thus, by forming a space (etched space X1) with a temperature difference between the main surface 101 and the bottom surface of the lower container 22, the temperature difference can be used as a driving force to transport Si atoms and C atoms from the main surface 101 to the bottom surface of the lower container 22.

[0117] The main container 20 may also have a substrate holding device 24 disposed between the SiC wafer 10 and the main container 20.

[0118] The heating furnace 30 according to this embodiment is structured such that heating is performed to create a temperature gradient, causing the temperature to drop from the upper container 21 of the main container 20 to the lower container 22. Therefore, by providing a substrate holding device 24 capable of holding the SiC wafer 10 between the SiC wafer 10 and the lower container 22, an etching space X1 can be formed between the SiC wafer 10 and the lower container 22.

[0119] The substrate holding device 24 can be any structure capable of holding at least a portion of the SiC wafer 10 within the hollow body container 20. For example, any commonly used support method, such as a one-point support, a three-point support, a structure supporting the outer periphery, or a structure clamping a portion, can be used. The substrate holding device 24 can be made of SiC or a high-melting-point metal.

[0120] Alternatively, depending on the direction of the temperature gradient in the furnace 30, the substrate holding fixture 24 may not be provided. For example, if the furnace 30 forms a temperature gradient such that the temperature decreases from the lower container 22 toward the upper container 21, the SiC wafer 10 may be placed on the bottom surface of the lower container 22 (without providing the substrate holding fixture 24).

[0121] like Figure 2 As shown, the heating furnace 30 includes: a main heating chamber 31, capable of heating the workpiece (such as SiC wafer 10) to a temperature of 1000°C or higher and 2300°C or lower; a preheating chamber 32, capable of preheating the workpiece to a temperature of 500°C or higher; a high melting point container 40, capable of housing the main container 20; and a moving device 33 (moving stage), capable of moving the high melting point container 40 from the preheating chamber 32 to the main heating chamber 31.

[0122] The main heating chamber 31 is formed as a regular hexagon in the top sectional view, and a high melting point container 40 is arranged inside it.

[0123] A heater 34 (mesh heater) is installed inside the main heating chamber 31. In addition, a multi-layer heat-reflective metal plate (not shown) is fixed to the side wall or top of the main heating chamber 31. The multi-layer heat-reflective metal plate is configured to reflect the heat from the heater 34 toward approximately the center of the main heating chamber 31.

[0124] Therefore, a heater 34 is arranged in the main heating chamber 31 to surround the high melting point container 40 containing the object to be processed, and a multi-layer heat-reflective metal plate is arranged on its outside, thereby allowing the temperature to be raised to a temperature of more than 1000°C and less than 2300°C.

[0125] Alternatively, the heater 34 can be, for example, a resistance heater or a high-frequency induction heater.

[0126] Furthermore, heater 34 may also employ a structure capable of forming a temperature gradient within the high-melting-point container 40. For example, heater 34 may also be configured to have multiple heaters arranged on the upper (or lower) side. Additionally, heater 34 may be configured to increase in width as it moves upward (or downward). Alternatively, heater 34 may be configured to increase the supplied power as it moves upward (or downward).

[0127] In addition, the main heating chamber 31 is connected to: a vacuum forming valve 35 for venting the main heating chamber 31; an inert gas injection valve 36 for introducing inert gas into the main heating chamber 31; and a vacuum gauge 37 for measuring the vacuum level in the main heating chamber 31.

[0128] Vacuum forming valve 35 is connected to a vacuum pump (not shown) for evacuating the exhaust gas from the main heating chamber 31. Through this vacuum forming valve 35 and vacuum pump, the vacuum level in the main heating chamber 31 can be adjusted to, for example, 10 Pa or less, more preferably 1 Pa or less, and even more preferably 10 Pa. -3 Pa or less. A turbomolecular pump can be exemplified as this vacuum pump.

[0129] An inert gas injection valve 36 is connected to an inert gas supply source (not shown). Through this inert gas injection valve 36 and the inert gas supply source, inert gas can be injected at 10... -5 The gas is introduced into the main heating chamber 31 within a range up to 10000 Pa. Ar, He, N2, etc., can be selected as the inert gas.

[0130] The preheating chamber 32 is connected to the main heating chamber 31 and is configured to allow the high-melting-point container 40 to be moved by the moving device 33. Furthermore, in this embodiment, the preheating chamber 32 is configured to utilize the residual heat from the heater 34 of the main heating chamber 31 for heating. For example, when the main heating chamber 31 is heated to 2000°C, the preheating chamber 32 is heated to approximately 1000°C, allowing for degassing of the workpiece (SiC wafer 10, main container 20, high-melting-point container 40, etc.).

[0131] The moving device 33 is configured to carry the high melting point container 40 and is capable of moving between the main heating chamber 31 and the preheating chamber 32. Since the transfer between the main heating chamber 31 and the preheating chamber 32 by the moving device 43 is completed in as little as 1 minute, heating and cooling rates of 1 to 1000°C / min can be achieved.

[0132] Because of the ability to rapidly heat up and cool down, it is possible to observe surface shapes that are difficult to achieve in conventional devices and do not have a low-temperature growth history during heating and cooling.

[0133] In addition, Figure 2 In this configuration, the preheating chamber 32 is located below the main heating chamber 31, but it is not limited to this and can also be located in any direction.

[0134] Furthermore, the moving device 33 according to this embodiment is a moving stage for placing the high-melting-point container 40. A small amount of heat is released from the contact area between the moving stage and the high-melting-point container 40. This allows a temperature gradient to be formed within the high-melting-point container 40.

[0135] In the heating furnace 30 of this embodiment, since the bottom of the high melting point container 40 is in contact with the moving platform, the temperature gradient is set such that the temperature decreases from the upper container 41 of the high melting point container 40 toward the lower container 42.

[0136] Furthermore, the direction of this temperature gradient can be set arbitrarily by changing the position of the contact portion between the moving stage and the high-melting-point container 40. For example, when the contact portion is positioned at the top of the high-melting-point container 40 using a suspension type or the like on the moving stage, heat escapes upwards. Therefore, the temperature gradient is set such that the temperature rises from the upper container 41 of the high-melting-point container 40 towards the lower container 42. Additionally, it is desirable that this temperature gradient form along the surface / back surface direction of the SiC wafer 10.

[0137] In addition, as mentioned above, a temperature gradient can also be formed through the structure of heater 34.

[0138] According to this embodiment, the vapor pressure environment of gaseous species containing Si in the heating furnace 30 is formed using a high-melting-point container 40 and a Si vapor supply source 44. For example, any method that can form a vapor pressure environment of gaseous species containing Si around the main container 20 can be used in an etching apparatus.

[0139] The high-melting-point container 40 is configured to contain a high-melting-point material. Examples include C as a general heat-resistant component, W, Re, Os, Ta, and Mo as high-melting-point metals, Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, and MoC as carbides, HfN, TaN, BN, Ta2N, ZrN, and TiN as nitrides, HfB2, TaB2, ZrB2, NB2, and TiB2 as borides, and polycrystalline SiC, etc.

[0140] The high-melting-point container 40, like the main container 20, is a fitted container comprising an upper container 41 and a lower container 42 that can fit together, and is configured to accommodate the main container 20. A small gap 43 is formed at the fitting portion of the upper container 41 and the lower container 42, and is configured to allow venting (vacuuming) of the high-melting-point container 40 through this gap 43.

[0141] The high-melting-point container 40 has a Si vapor supply source 44 capable of supplying the vapor pressure of a gaseous species containing Si to the high-melting-point container 40. The Si vapor supply source 44 can be any structure that generates Si vapor within the high-melting-point container 40 during heat treatment, for example, solid Si (Si particles such as single-crystal Si wafers, Si powder, etc.) or Si compounds can be exemplified.

[0142] In the etching apparatus, TaC is used as the material for the high-melting-point container 40, and tantalum silicide is used as the Si vapor supply source 44. That is, as... Figure 3 As shown, a tantalum silicide layer is formed on the inner side of the high melting point container 40, and is configured such that, during heat treatment, a vapor pressure of gaseous species containing Si is supplied from the tantalum silicide layer into the container, thereby forming a Si vapor pressure environment.

[0143] Furthermore, any structure that forms a vapor pressure of a gaseous species containing Si elements within a high-melting-point container 40 during heat treatment can be used.

[0144] According to the above-described etching apparatus, it is configured to include: a main container 20 that houses a SiC wafer 10 and generates vapor pressures of gaseous species containing Si and gaseous species containing C in its internal space by heating; and a heating furnace 30 that houses the main container 20 and heats it to generate vapor pressures of gaseous species containing Si in its internal space and to form a temperature gradient. The main container 20 has an etching space X1, which is formed by placing a portion of the main container 20, which is positioned on the low-temperature side of the temperature gradient, opposite to the SiC wafer 10 while the SiC wafer is positioned on the high-temperature side of the temperature gradient.

[0145] According to this structure, a near-thermal equilibrium state can be formed between the SiC wafer 10 and the main container 20, and a vapor pressure environment (partial pressure of gaseous species containing Si and C, such as Si2, Si3, Si2C, SiC2, SiC, etc.) can be formed within the main container 20. In this environment, mass transport occurs driven by the temperature gradient of the furnace 30, resulting in the etching and planarization of the SiC wafer 10.

[0146] Furthermore, by heating the main container 20 in a vapor pressure environment containing Si elements (e.g., a Si vapor pressure environment), the discharge of Si-containing gaseous species from the main container 20 can be suppressed. That is, by balancing the vapor pressure of Si-containing gaseous species inside the main container 20 with the vapor pressure of Si-containing gaseous species outside the main container 20, the environment inside the main container 20 can be maintained.

[0147] Furthermore, according to the etching apparatus described above, the main container 20 is made of polycrystalline SiC. By adopting this structure, when the main container 20 is heated using the furnace 30, vapor pressures containing only Si and C gaseous species can be generated within the main container 20.

[0148] like Figure 3 and Figure 4 As shown, in the etching step S31 of this embodiment, the SiC wafer 10 is housed inside the main body container 20, which is used to generate vapor pressures of gaseous species containing Si and gaseous species containing C in the internal space, and the main body container 20 is heated to form a temperature gradient in the environment of vapor pressures of gaseous species containing Si, thereby etching the SiC wafer 10.

[0149] Figure 4 This is an explanatory diagram showing the outline of the etching mechanism. Consider heating the main container 20 on which the SiC wafer 10 is disposed in a temperature range of 1400°C to 2300°C, and continuously performing the reactions 1) to 5) below, resulting in etching.

[0150] 1) SiC(s) → Si(v) + C(s)

[0151] 2) 2C(s) + Si(v) → SiC2(v)

[0152] 3) C(s) + 2Si(v) → Si₂C(v)

[0153] 4) Si(v) + SiC2(v) → 2SiC(s)

[0154] 5) Si₂C(v) → Si(v) + SiC(s)

[0155] 1) Explanation: By heating the SiC wafer 10 (SiC(s)), Si atoms (Si(v)) are decomposed from the surface of the SiC wafer 10 through thermal decomposition (Si atom sublimation step).

[0156] Explanation of 2) and 3): The C (C(s)) remaining on the surface of the SiC wafer 10 due to the detachment of Si atoms (Si(v)) reacts with the Si vapor (Si(v)) in the main container 20 to become Si2C or SiC2 and sublimate from the surface of the SiC wafer 10 (C atom sublimation step).

[0157] Explanation of 4) and 5): The sublimated Si2C or SiC2, etc., reach the bottom surface (polycrystalline SiC) inside the main container 20 due to the temperature gradient and grow.

[0158] That is, the etching step S31 includes: a Si atom sublimation step, which thermally sublimates Si atoms from the surface of the SiC wafer 10; and a C atom sublimation step, which causes C atoms remaining on the surface of the SiC wafer 10 to react with Si vapor in the main container 20 and sublimate from the surface of the SiC wafer 10.

[0159] Alternatively, etching step S31 can be performed with a Si element supply source or a C element supply source other than the SiC wafer 10 disposed inside the main container 20. There is no particular problem even if a Si element supply source or a C element supply source other than the SiC wafer 10 is present.

[0160] Furthermore, when the SiC wafer 10 has cracks (crack layer 111), it is preferable to arrange the SiC wafer 10 in a quasi-enclosed space with a Si / C atomic ratio of 1 or less and then heat it. For example, when a SiC wafer 10 with a stoichiometric ratio of 1:1 and SiC material with a stoichiometric ratio of 1:1 are arranged in a container (main container 20) made of SiC with a stoichiometric ratio of 1:1, the Si / C atomic ratio in the main container 20 is 1. Alternatively, a C vapor supply source (C particles, etc.) can be provided to make the Si / C atomic ratio 1 or less.

[0161] By etching the SiC wafer 10 in such an environment, cracks (crack layer 111) can be removed at high speed.

[0162] Furthermore, the presence and depth of the crack and crack layer 111 are related to the arithmetic mean roughness (Ra). That is, the arithmetic mean roughness (Ra) of the surface of the SiC wafer 10 with cracks is 10 nm or more, or 15 nm or more, or 20 nm or more, or 25 nm or more, or 30 nm or more, or 35 nm or more, or 40 nm or more.

[0163] In addition, the etching step S31 etches the SiC wafer 10 disposed on the high-temperature side of the temperature gradient and a portion of the main body container 20 disposed on the low-temperature side of the temperature gradient relative to each other.

[0164] That is, by arranging the main surface 101 of the SiC wafer 10 and the bottom surface of the body container 20, which has a lower temperature than the main surface 101, opposite each other, an etching space X1 is formed between them. In this etching space X1, the temperature gradient formed by the heating furnace 30 is used as a driving force to transport mass, and as a result, the SiC wafer 10 can be etched.

[0165] The etching temperature in etching step S31 is preferably set in the range of 1400°C to 2300°C, and more preferably in the range of 1600°C to 2000°C.

[0166] The etching rate in etching step S31 can be controlled by the above temperature range and can be selected in the range of 0.001 μm / min to 2 μm / min.

[0167] There are no particular limitations on the amount of etching in etching step S31, as long as the strain on the SiC substrate can be removed and the surface of the SiC substrate can be made to a predetermined surface roughness.

[0168] Whether the strain on the SiC substrate was removed by the etching step S31 can be evaluated by the following method.

[0169] The strain (more specifically, lattice strain) of a SiC substrate can be determined by comparing it with a reference lattice. One method for measuring this lattice strain is, for example, the SEM-EBSD method. SEM-EBSD is a method for measuring strain in a small area using a scanning electron microscope (SEM) based on a Kikuchi line diffraction pattern obtained through electron backscattering (EBSD). In this method, the lattice strain can be determined by comparing the diffraction pattern of the reference lattice with the diffraction pattern of the measured lattice.

[0170] As a reference lattice, a reference point can be set, for example, in a region where lattice strain is not expected to occur. Typically, the depth of the processed modified layer introduced by machining is approximately 10 μm. Therefore, it is sufficient to set the reference point at a depth of approximately 20 to 35 μm, which is considered sufficiently deep to be deeper than the processed modified layer 101.

[0171] Next, the diffraction pattern of the lattice at the reference point is compared with the diffraction patterns of the lattice in each measurement region, measured at nanometer-level spacing. From this, the lattice strain of each measurement region relative to the reference point can be calculated.

[0172] Furthermore, the case of setting a reference lattice as a reference point that is considered to be free from lattice strain is shown, but of course it is also possible to use an ideal lattice of single-crystal SiC as a reference, or a lattice that occupies most (e.g., more than half) of the surface of the measurement region as a reference.

[0173] By measuring the presence of lattice strain using this SEM-EBSD method, the presence or absence of a processing-modified layer can be determined. That is, when processing damage such as scratches, potential scratches, and strain introduced through machining is introduced, lattice strain is generated at the SiC substrate, and the stress is observed using the SEM-EBSD method.

[0174] Furthermore, the "predetermined surface roughness" of the SiC substrate to be achieved by etching step S31, as the arithmetic mean roughness (Ra), is preferably 60 nm or less, more preferably 50 nm or less, more preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, more preferably 10 nm or less, even more preferably 5 nm or less, even more preferably 4 nm or less, even more preferably 3 nm or less, even more preferably 2 nm or less.

[0175] As described above, there is no particular limitation on the etching amount, as long as it can remove the strain of the SiC substrate and achieve the surface roughness within the above-mentioned numerical range. Specifically, it is preferably 0.5 μm or more, more preferably 0.6 μm or more, more preferably 0.7 μm or more, more preferably 0.8 μm or more, more preferably 0.9 μm or more, even more preferably 1 μm or more, even more preferably 2 μm or more, and even more preferably 3 μm or more.

[0176] The etching time in etching step S31 can be set to any time to achieve the desired etching amount. For example, if the etching amount is 1 μm when the etching rate is 1 μm / min, the etching time is 1 minute.

[0177] The temperature gradient in etching step S31 is set in the etching space X1 within the range of 0.1℃ / mm to 5℃ / mm.

[0178] <5> Steps after etching step S31

[0179] The SiC wafer after etching step S31 has an extremely smooth surface with reduced strain.

[0180] Therefore, it is possible to proceed without any further machining after the etching step S31. Examples of machining processes include chemical mechanical polishing (CMP).

[0181] In machining processes, including CMP, numerous scratches (cracks) or strains sometimes occur on the surface of SiC wafers. By omitting machining after etching step S31, higher quality SiC wafers can be provided.

[0182] Furthermore, conventionally, after performing the mirror polishing step S40, which includes a chemical mechanical polishing step S41, a cleaning step S52 is performed to remove fine particles remaining on the surface of the SiC wafer. As a cleaning method, RCA cleaning is generally performed. Figure 11 ).

[0183] On the other hand, in this invention, where strain removal and an extremely smooth surface are achieved through etching step S31 instead of mirror polishing step S40, no residual foreign matter that should be removed by cleaning step S52 is generated after etching step S31. Therefore, cleaning step S52 can also be omitted after etching step S31. Figure 1 ).

[0184] As described above, in this invention, a SiC wafer having a surface suitable for epitaxial growth can be obtained through etching step S31.

[0185] Therefore, performing the epitaxial growth step S61, which forms an epitaxial layer on the surface of the SiC wafer, after the etching step S31 is effective from the perspective of reducing working time.

[0186] As a method for performing the epitaxial growth step S61 after the etching step S31, any known method can be used.

[0187] For example, CVD, PVE, or LPE can be used as epitaxial growth methods. Here, CVD refers to Chemical Vapor Deposition, PVE refers to Physical Vapor Epitaxy, and LPE refers to Liquid Phase Epitaxy.

[0188] [Manufacturing method of SiC single crystal seed substrate]

[0189] This invention can be applied to the fabrication of SiC single-crystal seed substrates. Figure 5 An embodiment of the invention is shown when it is applied to the fabrication of a SiC single-crystal seed substrate.

[0190] like Figure 5As shown, in this embodiment, for the SiC single crystal substrate, after the planarization step is performed until a predetermined surface roughness is achieved, or after the planarization step S20 is performed using abrasive grains with a predetermined particle size or smaller, the etching step S31 is performed.

[0191] The above description of the SiC wafer manufacturing method is appropriate regarding the specific aspects of the planarization step S20 and the etching step S31.

[0192] In this embodiment, an ingot forming step S62 is included, in which a crystal ingot is obtained by growing a SiC single crystal seed substrate obtained by etching step S31.

[0193] The specific method of ingot formation step S62 can be any known ingot formation method without particular restrictions, such as sublimation, CVD, and gas growth.

[0194] Alternatively, the SiC ingot obtained in this way can be used as raw material for the slicing step S1, and through... Figure 1 The embodiment shown manufactures SiC wafers.

[0195] Example

[0196] <1> Sample preparation (planarization step)

[0197] A SiC substrate was prepared, which underwent mirror finishing and had potential defects such as scratches removed.

[0198] For this SiC substrate, diamond abrasive grains with average abrasive grain sizes of 15μm, 10μm, 1μm or 0.3μm were used to perform pseudo-planarization by fixing the abrasive grains, and these were used as samples 1 to 4 respectively.

[0199] The arithmetic mean roughness (Ra) of samples 1 to 4 was measured. Additionally, the arithmetic mean roughness (Ra) of sample 1 was measured using a laser microscope, and the arithmetic mean roughness (Ra) of samples 2 to 4 was measured using an arithmetic mechanical microscope (AFM).

[0200] For samples 1 to 4, the average abrasive grain size and arithmetic mean roughness (Ra) of the abrasive grains used in the fabrication are summarized in Table 1 below. Additionally, for the arithmetic mean roughness (Ra), the value with the first decimal place rounded is shown in the table.

[0201] [Table 1]

[0202] Sample No. 1 2 3 4 Average abrasive grain size of abrasive grains used (μm) 15 10 1 0.3 Arithmetic average roughness (Ra) (nm) 1100 53 17 1

[0203] <2> Etching steps

[0204] The following main container 20, high-melting-point container 40, and samples 1 to 4 (SiC wafer 10) are configured as follows:Figure 2 and Figure 3 The structure shown.

[0205] [Main Container 20]

[0206] Material: Polycrystalline SiC

[0207] Container dimensions: 60mm in diameter × 4mm in height

[0208] Material of substrate holding fixture 24: single crystal SiC

[0209] Distance between SiC wafer 10 and the bottom surface of main container 20: 2mm

[0210] [High melting point container 40]

[0211] Materials: TaC

[0212] Container dimensions: 160mm in diameter × 60mm in height

[0213] Si vapor supply source 44 (Si compound): TaSi2

[0214] [Etching Steps]

[0215] Temperature gradient: 1℃ / mm, main heating chamber vacuum: 10 -5 Samples 1 to 4, prepared under the above conditions, were subjected to heat treatment under Pa conditions.

[0216] In addition, experiments were conducted on each sample under two conditions: Condition A and Condition B. Condition A involved etching with a single-crystal Si wafer inside the main container 20 as the Si vapor supply source, while Condition B involved etching without a single-crystal Si wafer inside the main container 20.

[0217] That is, condition A is the condition of arranging SiC wafer 10 in a quasi-closed space with a Si / C atomic ratio of more than 1 and heating it, and condition B is the condition of arranging SiC wafer 10 in a quasi-closed space with a Si / C atomic ratio of less than 1 and heating it.

[0218] Etching was performed at heating temperatures of 1500℃, 1600℃, 1700℃, 1800℃, and 1900℃, respectively, under multiple conditions with different etching amounts. Furthermore, the etching amount could be adjusted by changing the heating time.

[0219] <3> evaluate

[0220] <3-1> Strain Measurement by SEM-EBSD Method

[0221] The strain at specimens 1 to 4 before and after the etching step was observed using SEM-EBSD. The strain measurement by SEM-EBSD was performed on the cross-sections of the SiC substrates of specimens 1 to 4 after they were cut open using a scanning electron microscope under the following conditions.

[0222] SEM apparatus: Zeiss Merline

[0223] EBSD Analysis: TSL Solutions OIM Crystal Orientation Analysis System

[0224] Accelerating voltage: 15kV

[0225] Probe current: 15nA

[0226] Step size: 200nm

[0227] Reference point R depth: 20μm

[0228] As a result of the measurements, strain was observed at specimens 1 to 4 before the etching step. This is lattice strain introduced by the pseudo-planarization step during specimen fabrication, indicating the presence of a processed modified layer. Additionally, compressive stress was observed at all specimens. Specifically, a strain of 5 μm depth was observed at specimen 1, a strain of 3 μm depth at specimen 3, and a strain of 1 μm depth at specimen 4.

[0229] On the other hand, no strain was observed in etched samples 1 to 4. This result indicates that the processed altered layer was removed by the etching step.

[0230] Figure 6 The cross-sectional SEM-EBSD images of the SiC substrate of sample 1 before and after etching are shown. Figure 6 Image (a) is a cross-sectional SEM-EBSD image of sample 1 before etching. Before etching, the black-and-white contrast of the image shows that strain was introduced to a depth of 5 μm. Figure 6 Image (b) is a SEM-EBSD image of the etched cross-section. After this etching, the same black-and-white contrast as before etching was not observed. That is, as... Figure 6 As shown, a strain of 5 μm depth was introduced before the etching step, but it can be removed by etching.

[0231] <3-2> Surface Evaluation by SEM

[0232] The surfaces of samples 1 to 4 before and after the etching step were observed by SEM. Figure 7SEM images (3000x magnification) of the surface of SiC substrates of samples 1 to 4 are shown before the etching step, after etching 3.08 μm under condition A (temperature 1800 °C) and after etching 5 μm under condition B (temperature 1800 °C).

[0233] like Figure 7 As shown, even after etching under either condition A or B, sample 1 still has significant unevenness remaining on its surface.

[0234] On the other hand, such as Figure 7 As shown in samples 2 to 4, an extremely smooth surface can be achieved through etching, and no significant unevenness was observed as in sample 1.

[0235] In sample 3, tiny pits (indicated by white arrows) were observed after etching under condition B. However, in sample 4, no pits were observed even when etching under condition B, and a smoother surface was obtained.

[0236] <3-3> Relationship between arithmetic mean roughness (Ra) and etching amount

[0237] For the SiC substrates of samples 1, 3, and 4 etched under the various conditions described above, the etching amount and arithmetic mean roughness (Ra) were measured. Additionally, the arithmetic mean roughness (Ra) of sample 1 was measured using laser microscopy, and the arithmetic mean roughness (Ra) of samples 3 and 4 was measured using AFM. The arithmetic mean roughness (Ra) before and after etching, along with the etching amount, are plotted on a graph.

[0238] The results of sample 1 are in Figure 8 The results for sample 3 are shown in the figure. Figure 9 The results for sample 4 are shown in the figure. Figure 10 As shown in the figure. In addition, in the graphs showing the results, the depth of strain measured in <3-1> above is indicated by black arrows.

[0239] like Figure 8 As shown, for the SiC substrate of sample 1 (with an initial arithmetic mean roughness (Ra) of approximately 1100 nm) processed with abrasive grains of average diameter of 15 μm, the arithmetic mean roughness (Ra) does not fall below 60 nm even with deep etching. In particular, for the SiC substrate etched under condition B, even regions were observed where the surface roughness increased with increasing etching amount.

[0240] This result indicates that the strain on the SiC substrate of sample 1 can be removed by etching, but an extremely smooth surface cannot be achieved.

[0241] On the other hand, for the SiC substrate of sample 3 (initial arithmetic mean roughness (Ra) of approximately 17 nm) processed with abrasive grains of average abrasive diameter of 1 μm, the arithmetic mean roughness (Ra) is less than 5 nm near an etching depth of 1000 nm. Figure 9 ).

[0242] Furthermore, it is known that if etching is performed to a depth exceeding the strain present before etching, the arithmetic mean roughness (Ra) can be reduced to below 2 nm. Figure 9 ).

[0243] Furthermore, when the SiC substrate of sample 4 (with an initial arithmetic mean roughness (Ra) of approximately 0.5 nm) processed with abrasive grains of an average abrasive grain size of 0.3 μm was etched, an extremely flat surface with an arithmetic mean roughness (Ra) of less than 2 nm and further less than 1 nm was confirmed to be formed. Figure 10 ).

[0244] In addition, according to Figure 8 It can be seen that in the SiC wafer 10 with cracks, i.e., sample 1, the etching rate under condition B is faster than that under condition A up to 5 μm of the removal of the processed altered layer.

[0245] Therefore, when etching a SiC wafer 10 with cracks, high-speed etching can be performed by including a step (condition B) of arranging the SiC wafer 10 in a quasi-enclosed space with a Si / C atomic ratio of less than 1 and heating it.

[0246] Specifically, when etching a SiC wafer 10 with cracks, etching can be performed first under condition B and then under condition A, which can shorten the etching time of the SiC wafer 10.

[0247] <4> Summarize

[0248] The above results demonstrate that by performing a planarization step on a SiC substrate until the arithmetic mean roughness (Ra) of the surface is below 100 nm, or by performing a planarization step using abrasive grains with an average particle size of below 10 μm, etching in an atmosphere containing Si and C elements can yield a SiC substrate with strain-free surface and an extremely smooth surface. The SiC substrate thus obtained can be used for epitaxial growth steps even without further mechanical processing such as CMP.

[0249] Explanation of reference numerals in the attached figures

[0250] 10. SiC substrate (SiC wafer)

[0251] 101 Main Surface

[0252] 11 Processing the altered layer

[0253] 111 Crack Layer

[0254] 112 Strain Layer

[0255] 12 block layers

[0256] 20 Main Containers

[0257] 24. Substrate holding fixtures

[0258] 30 Heating Furnace

[0259] 40 High melting point containers

[0260] 44 Si vapor supply source

[0261] X1 Etching Space

[0262] S1 Slicing Steps

[0263] S20 Flattening Steps

[0264] S21 Grinding Step

[0265] S22 Rough Grinding Steps

[0266] S23 Fine grinding steps

[0267] S31 Etching Step

[0268] S40 Mirror Polishing Steps

[0269] S41 Chemical Mechanical Polishing Steps

[0270] S51, S52 Cleaning Steps

[0271] S61 Epitaxial Growth Steps

[0272] S62 Ingot Formation Steps

Claims

1. A method for manufacturing a SiC substrate, comprising: The etching step involves placing a SiC substrate with an arithmetic mean roughness (Ra) of less than 100 nm in a SiC container, positioning the SiC substrate and the SiC container opposite each other, and heating the container to create a temperature gradient between them, thereby etching the SiC substrate in an atmosphere containing Si and C elements.

2. The method for manufacturing a SiC substrate according to claim 1, comprising: The etching step is performed on a SiC substrate with an arithmetic mean roughness (Ra) of less than 2 nm.

3. The method for manufacturing a SiC substrate according to claim 1, comprising: The planarization step is used to planarize the surface of the SiC substrate so that its arithmetic mean roughness (Ra) is below 100 nm. The etching step involves etching the SiC substrate after the planarization step.

4. The method for manufacturing a SiC substrate according to claim 3, wherein, In the planarization step, the surface of the SiC substrate is planarized so that its arithmetic mean roughness (Ra) is less than 2 nm.

5. A method for manufacturing a SiC substrate, comprising: The planarization step involves planarizing the surface of the SiC substrate using abrasive grains with an average abrasive grain size of less than 10 μm. The process includes an etching step in which the SiC substrate after the planarization step is placed in a SiC container, with the SiC substrate and the SiC container facing each other, and heating is performed to create a temperature gradient between the SiC substrate and the SiC container, thereby etching the SiC substrate in an atmosphere containing Si and C elements.

6. The method for manufacturing a SiC substrate according to claim 5, wherein, The average abrasive grain size is less than 0.5 μm.

7. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, The etching step includes: placing a cracked SiC substrate within a quasi-enclosed space where the Si / C atomic ratio is less than 1 and then heating it. The quasi-enclosed space is formed by the container made of SiC.

8. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, No mechanical processing is performed on the surface of the SiC substrate after the etching step.

9. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, No cleaning step is performed after the etching step.

10. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, An epitaxial growth step is performed after the etching step to form an epitaxial layer on the surface of the SiC substrate.

11. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, The etching step is a step of etching the SiC single crystal primary substrate and manufacturing the SiC single crystal seed substrate, and after the etching step, there is an ingot forming step of growing the SiC single crystal seed substrate to obtain an ingot.

12. The method for manufacturing a SiC substrate according to any one of claims 1 to 6, wherein, The SiC substrate is 2 inches or larger.

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