A Quadtree Monitoring Network Design Method

Abstract

This invention discloses a quadtree monitoring network design method, belonging to the field of chip design technology. It designs a quadtree-based monitoring network in a GPU chip. First, the tree structure parameters are calculated based on the number of modules to be monitored in the GPU and their corresponding power domains. Then, the structural design of the quadtree monitoring network is performed, taking into account the requirements of the monitored modules. Next, the logical design of the branch nodes as routers is carried out, divided into routing and transmission two-level pipelines to realize the transmission function of monitoring data in the network. Finally, the network communication protocol is designed hierarchically, combining the transmission characteristics between each layer and the layer splicing scheme, to complete the quadtree monitoring network design. This invention combines the characteristics of monitoring modules with a quadtree network, solving the problem of difficult back-end layout and routing caused by excessively long physical distances in GPU monitoring networks, and also introducing lower routing requirements for the monitoring network.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology and relates to a design method for GPU monitoring networks, specifically a quadtree monitoring network design method. Background Technology

[0002] As chip performance becomes increasingly powerful, the complexity and volume of data involved in the interactions between internal modules also increase significantly. Monitoring module performance has become a crucial aspect of chip design, as it greatly reduces time costs in design and verification. Monitoring units are strategically placed near each functional module to calculate performance parameters. The monitoring module then reads and analyzes these parameters from each monitoring unit to identify performance bottlenecks or operational anomalies. This guidance helps designers debug functions and optimize performance to meet chip design requirements.

[0003] A GPU is a display chip designed for image and graphics-related computations. Its internal data interaction requirements are particularly high, necessitating continuous optimization at each stage of chip design. Monitoring modules, by evaluating the data transmission performance, can significantly improve debugging speed. As GPU functionality and performance continue to improve, the area and number of its functional modules also increase. Monitoring units are distributed throughout the chip, and connections to the main monitoring module need to bypass numerous modules. Excessive physical distances can lead to backend layout and routing issues. Furthermore, the congestion caused by excessive wiring used for monitoring signal transmission can significantly increase the risk of chip design problems.

[0004] Therefore, a novel design methodology for GPU monitoring networks is needed to overcome the shortcomings of existing technologies. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a quadtree monitoring network design method. This method employs a novel and unique design and layout approach to solve the problem of backend wiring caused by excessively long physical distances in monitoring modules, and also to resolve the issue of congested wiring caused by monitoring signal transmission.

[0006] To achieve the above objectives, this invention provides a quadtree monitoring network design method, which mainly includes the following steps:

[0007] S1: Calculate the tree structure parameters based on the number of modules that need to be monitored in the GPU and their corresponding power domains. Then, design the tree-structured monitoring network based on the requirements of the modules to be monitored.

[0008] S2: Based on the structural design of the tree-shaped monitoring network, node logic design is carried out, divided into two-level pipelines: routing and transmission, to realize the transmission of monitoring data in the tree-shaped monitoring network.

[0009] S3: Based on the design in step S2, design the network protocol, combine the transmission characteristics between each layer and the layer splicing scheme, design the network communication protocol in layers, and complete the quadtree monitoring network design.

[0010] In step S1, in the structural design of the tree-structured monitoring network, the main monitoring module reads monitoring data from each monitoring unit. The main monitoring module corresponds to the root node in the tree structure, and the monitoring unit corresponds to the leaf node in the tree structure. By default, the number of leaf nodes is less than 64.

[0011] Further, in step S1, the degree of the tree is set to 4 based on the number of interfaces of the storage and graphics processing high-performance modules in the GPU, to ensure that one GPU has 1-2 nodes corresponding to its storage and graphics processing high-performance modules, thus realizing a quadtree structure in the monitoring network. In the quadtree monitoring network, different structural parameters need to be calculated based on the number of power domains. If the quadtree monitoring network is for a single power domain, the root node does not contain a power domain subtree structure. The depth of the tree is calculated based on the number of leaves. Branch nodes in the quadtree monitoring network are distributed in the GPU as routers to forward monitoring data. The number of branch nodes in the network is calculated based on the number of leaves. If the quadtree monitoring network contains multiple power domains, the root node will generate child nodes corresponding to the number of power domains, and these child nodes will serve as the parent nodes of each power domain subtree. The number of leaves in each subtree structure is determined, and the depth of the tree and the number of branch nodes in each power domain subtree are obtained accordingly. The number of branch nodes in the multi-power domain quadtree monitoring network is calculated based on the above parameters.

[0012] In step S2, the node logic design includes a two-level pipeline: routing and transmission. The node routing pipeline implements the routing logic, while the node transmission pipeline is the communication logic between the current node and its child nodes, thus enabling the transmission of monitoring data between nodes.

[0013] Furthermore, in step S2, the node routing pipeline uses a speculative routing algorithm, combines the monitoring unit ID to perform routing calculations, and combines the data packet sequence number to complete the virtual channel allocation, reducing the traditional routing pipeline to 1 level and improving the performance of the routing node.

[0014] Furthermore, the node routing logic separates the data and command channels and adopts a 5-way virtual channel design. Of the 5 virtual channels, 4 are used for data transmission and 1 is used as the command channel. The buffer of the single physical channel output to the parent node is divided into 4 virtual channels, which correspond to the link data of its 4 child nodes respectively. Data communication of the 4 virtual channels is carried out through time-division multiplexing to improve bandwidth utilization.

[0015] Furthermore, the command channel only needs to handshake with the virtual channel used for data communication once to complete the routing function.

[0016] Furthermore, the node transmission pipeline employs hierarchical splicing technology. Each communication link communicating with child nodes buffers two already-handshaked data packets. It polls four communication links, transmitting one data packet after each hierarchical splicing. The number of data packets transmitted after each hierarchical splicing is half the number of data packets transmitted in the child hierarchy. This method uses narrow connections for data packets on the links, reducing cable congestion.

[0017] Furthermore, in the network transmission protocol design process, the protocol needs to include the monitoring unit ID number, data packet sequence number, data and completion indicator bits, and the data bit width needs to be adjusted according to different levels, and the network communication protocol is designed in a hierarchical manner.

[0018] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0019] This invention provides a quadtree monitoring network design method that integrates functional sub-modules from a monitoring module into a tree structure to form a quadtree monitoring network. Based on the characteristics of the monitoring module's structure and parameters, hierarchical splicing and virtual channels are designed to optimize the data packet transmission rate within the monitoring network. This invention combines monitoring modules with a quadtree network to solve the problem of excessively long physical distances caused by overly dispersed monitoring modules during GPU placement and routing. Furthermore, it reduces transmission bandwidth by leveraging network data packet transmission, resulting in lower trace congestion and significantly improving the transmission performance and physical feasibility of monitoring modules within the GPU. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a quadtree monitoring network design method according to an embodiment of the present invention;

[0021] Figure 2 This is a flowchart illustrating the network structure design of an embodiment of the present invention;

[0022] Figure 3 This is a network structure diagram of an embodiment of the present invention;

[0023] Figure 4 This is a flowchart illustrating the node logic design of an embodiment of the present invention.

[0024] Figure 5 This is a network protocol structure diagram according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] Figure 1 The flowchart illustrates a quadtree monitoring network design method according to an embodiment of the present invention. As shown in the figure, the present invention provides a quadtree monitoring network design method that integrates functional sub-modules in the monitoring module into a tree structure to form a quadtree monitoring network. The quadtree monitoring network is a hardware network, and a quadtree is a data structure. The monitoring network is designed using the concept of data structures.

[0027] Figure 1 This is a flowchart illustrating a quadtree monitoring network design method according to an embodiment of the present invention. Figure 1 It can be seen that, logically, it includes three steps from beginning to end:

[0028] Step S1: The main task is to design the network structure. Based on the number of modules that need to be monitored in the GPU and their corresponding power domains, the tree structure parameters are calculated. Combined with the requirements of the modules that need to be monitored, the structure of the quadtree monitoring network is designed.

[0029] Step S2: The main focus is on node logic design, which is divided into two-level pipelines: routing and transmission, to realize the transmission function of monitoring data in the monitoring network.

[0030] Step S3: The main task is to design the network protocol, combining the transmission characteristics between each layer and the layer splicing scheme, and designing the network communication protocol layer by layer.

[0031] Figure 2 This is a flowchart illustrating the network structure design of an embodiment of the present invention. Figure 2 First, the monitoring network adopts a tree structure. The monitoring module samples monitoring parameters from the root node, and the monitoring unit corresponds to a leaf node in the tree structure. Next, the degree of the tree structure network is determined based on the number of commonly used interfaces of the high-performance modules performing storage and graphics processing in the GPU. Specifically, the degree of the tree can be set to 4 based on the number of commonly used interfaces of the high-performance modules performing storage and graphics processing in the GPU, ensuring that one high-performance module performing storage and graphics processing corresponds to 1-2 nodes. This is why the data structure of this invention adopts a quadtree structure. Then, the interfaces of the monitoring units are mapped to the tree structure network. The number of leaves in the tree structure network is L, and by default, the number of leaves L in the tree structure network is less than 64.

[0032] Next, determine whether the tree-structured network is within a single power domain. If it is, there is no cross-power domain transmission, and no subtree structure is needed. In this case, when the root node does not contain a power domain subtree structure (i.e., level 1), the tree depth D is:

[0033] D = Ceiling(log4L) + 1

[0034] The Ceiling function rounds the parameter up to the nearest integer; for example, celing3.1 equals 4. The branch nodes in the tree-structured network are distributed across the chip, acting as routers to forward monitoring data. The number B of branch nodes in the tree-structured network is:

[0035] B=Ceiling(log4L)+Ceiling(log 16 L)+1

[0036] If a tree-structured network contains multiple power domains, then the number of power domains emanating from the root node (i.e., level 1) is N. pd The child node (i.e., level 2) is selected, and this child node serves as the parent node of each power domain subtree network, and the number of leaves L in each subtree structure is determined. pdx Based on the number of leaves L in each subtree structure pdx The depth D of the tree can be obtained. pd :

[0037] D pd =Ceiling(log4max(L pdx ))+2

[0038] The number of branch nodes B in each power domain subtree network pdx for:

[0039] B pdx =Ceiling(log4L) pdx )+Ceiling(log 16 L pdx )+1

[0040] The number of branch nodes B in a tree-structured network under multiple power domain conditions pd for:

[0041]

[0042] Where x refers to the x-th power domain. B pdx This refers to the number of branch nodes in the x-th power domain. pd stands for powerdomain.

[0043] Thus, we can obtain the tree structure network in the case of a single power domain or a tree structure network containing multiple power domains.

[0044] Figure 3The diagram illustrates the network structure of this invention. As shown, the tree-structured network calculated using the above formula requires further network structure design. Specifically, firstly, the monitoring module acts as the host of the tree-structured network, accessing various monitoring units within it. Next, the root node integrates data packets and interacts with the monitoring module in the form of data packets. The cross-power domain nodes under the root node support multi-power domain design, employing level conversion units (located between parent and child nodes) for cross-power domain transmission. Cross-clock domain nodes are set under the cross-power domain nodes under the root node, interconnecting with each monitoring unit. The cross-clock domain nodes under the root node support multi-clock domain design, using asynchronous FIFOs (also located between parent and child nodes) for cross-clock domain transmission. Simultaneous clock domain nodes under the root node can interconnect with their parent nodes without processing. Cross-clock domain nodes, as child nodes of cross-power domain nodes, are interconnected by inserting an asynchronous FIFO after the level conversion unit. The monitoring units, acting as leaves of the tree-structured network, monitor the high-performance modules requiring monitoring, such as storage and graphics processing modules.

[0045] Figure 4 This is a flowchart illustrating the node logic design of an embodiment of the present invention, such as... Figure 4 As shown, the node logic design described in this invention includes a two-stage pipeline of routing and transmission. The node routing pipeline implements the routing logic, and the node transmission pipeline is the communication logic between the current node and its child nodes. The node logic design is used to implement the function of transmitting monitoring data between nodes.

[0046] Specifically, firstly, based on the further designed tree-structured network, the corresponding node logic design is further refined, reducing the traditional router design, which includes a five-stage pipeline of buffer design, route calculation, virtual channel selection, switch selection, and switch transmission, to a single stage. Hierarchical splicing and link transmission are integrated into this single-stage pipeline, resulting in a node logic design comprising two stages: routing and transmission. Next, the first-stage routing pipeline is designed, with main functions including route calculation and virtual channel selection. Then, a speculative routing algorithm is used, combined with the monitoring unit ID, to calculate the route, select the routing path, and address the corresponding virtual channel entry point. Further, virtual channel selection is performed based on the packet sequence number, separating data and command channels, and employing a 5-channel design: 4 virtual channels for data communication and 1 virtual channel for command communication. The buffer of the single physical channel output to the parent node is divided into 4 virtual channels, each corresponding to the link data of its 4 child nodes. Time-division multiplexing is used for data communication across these 4 virtual channels, thereby improving bandwidth utilization. The instruction channel only needs to handshake with its data virtual channel once to complete the routing function and the first-level pipeline. Next, the second-level routing pipeline is designed, whose main functions include hierarchical splicing and link transmission. More specifically, the node communication logic uses hierarchical splicing technology. Each link communicating with child nodes buffers two data packets, polling four communication links. The first round of four clock cycles is used to buffer the first data from the four communication links. In the second round, the first clock cycle checks if the first communication link has buffered two data packets, and the next clock cycle queries the next communication link. If two data packets are buffered, the data packets are spliced ​​into one data packet in the next clock cycle, and the buffer is cleared, waiting for the next access to that communication link. At each level of splicing, narrow connections are used on the link to reduce congestion, and the splicing validity signal is pulled high, transmitting half the number of data packets as the previous level. Finally, the data packet is sent to the next level node, completing the second-level pipeline.

[0047] Figure 5 This is a network protocol structure diagram of an embodiment of the present invention, such as... Figure 5 As shown, the network protocol needs to include a monitoring unit ID number, packet sequence number, data, and a completion indicator bit. The data bit width needs to be adjusted according to different layers. The unit ID number is used to identify the source for the monitoring module; the packet sequence number is used to identify the order during concatenation; the data is concatenated at each layer, with each concatenation being half of the previous layer, and zero at the root node; the monitoring parameters are in 32-bit units, with each concatenation being twice the size of the previous one; the completion indicator bit is used to indicate whether the data packet transmission is complete.

[0048] Specifically, Figure 5In the tree or sub-level 1, the 6-bit monitoring unit ID (referring to the module ID in the diagram) indicates the interface number. The 128-bit data is composed of four 32-bit data packets concatenated through two layers. A 1-bit completion indicator is used to indicate that the transmission is complete. In the tree or sub-level 2, the 6-bit monitoring unit ID indicates the interface number. The 64-bit data is composed of two 32-bit data packets concatenated through one layer. A 1-bit completion indicator is used to indicate that the transmission is complete. In the tree or sub-level 3, i.e., the leaf node, the 6-bit monitoring unit ID indicates the interface number, the 64-bit data is the monitoring unit's return data packet, and a 1-bit completion indicator is used to indicate that the transmission is complete.

[0049] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for designing a quadtree monitoring network, characterized in that, It includes the following steps: S1: Calculate the tree structure parameters based on the number of modules that need to be monitored in the GPU and their corresponding power domains. Then, design the tree-structured monitoring network based on the requirements of the modules to be monitored. In the tree-structured monitoring network, the main monitoring module reads monitoring data from each monitoring unit. The main monitoring module corresponds to the root node in the tree structure, and the monitoring units correspond to the leaf nodes. By default, the number of leaf nodes is less than 64. The degree of the tree is set to 4 based on the number of interfaces of the high-performance storage and graphics processing modules in the GPU, ensuring that one high-performance storage and graphics processing module in the GPU corresponds to 1 to 2 nodes, and ensuring that the data structure in the monitoring network is a quadtree structure. If the quadtree monitoring network is a single power domain, and the root node does not contain a power domain subtree structure, the tree depth is calculated based on the number of leaves. In the quadtree monitoring network, branch nodes are distributed across the GPU as routers to forward monitoring data. The number of branch nodes in the quadtree monitoring network is calculated based on the number of leaves. Specifically, when the root node does not contain a power domain subtree structure, the tree depth is... for: in, A function is defined as rounding a parameter up to the nearest integer; the number of branch nodes in a tree-structured network. for: The number of leaves in a tree structure network. Less than 64 If a quadtree monitoring network contains multiple power domains, the root node leads to a number of child nodes corresponding to the number of power domains, and these child nodes serve as the parent nodes of each power domain subtree. The number of leaves in each subtree structure is determined, and the tree depth and the number of branch nodes in each power domain subtree are obtained based on the number of leaves. The total number of branch nodes in the multi-power-domain quadtree monitoring network is then calculated using these parameters. tree depth : Number of branch nodes in each power domain subtree network for: in, The number of leaves in each subtree structure. Number of branch nodes in a tree-structured network under multiple power domains for: in, It refers to the first A power domain, It refers to the first The number of branch nodes in each power domain. It refers to the power domain, which means the power supply domain in Chinese. It is the total number of power domains. S2: Based on the structural design of the tree-shaped monitoring network, node logic design is carried out, divided into two-level pipelines: routing and transmission, to realize the transmission of monitoring data in the tree-shaped monitoring network. S3: Based on the design in step S2, design the network protocol, combine the transmission characteristics between each layer and the layer splicing scheme, design the network communication protocol in layers, and complete the quadtree monitoring network design.

2. The quadtree monitoring network design method as described in claim 1, characterized in that, In step S2, the node logic design includes a two-level pipeline: routing and transmission. The node routing pipeline implements the routing logic, while the node transmission pipeline is the communication logic between the current node and its child nodes, thus enabling the transmission of monitoring data between nodes.

3. The quadtree monitoring network design method as described in claim 2, characterized in that, In step S2, the node routing pipeline uses a speculative routing algorithm, combines the monitoring unit ID to perform routing calculations, and combines the packet sequence number to complete the virtual channel allocation, reducing the traditional routing pipeline to 1 level.

4. The quadtree monitoring network design method as described in claim 3, characterized in that, In step S2, the node routing logic separates the data and command channels and adopts a 5-way virtual channel design. Four of the five virtual channels are used for data transmission, and one virtual channel is used as the command channel. The buffer of the single physical channel output to the parent node is divided into four virtual channels, which correspond to the link data of its four child nodes respectively. Data communication between the four virtual channels is carried out through time-division multiplexing.

5. The quadtree monitoring network design method as described in claim 4, characterized in that, In step S2, the command channel only shakes hands with the virtual channel used for data communication once to complete the routing function.

6. The quadtree monitoring network design method as described in claim 5, characterized in that, In step S2, the node transmission pipeline uses hierarchical splicing technology. Each communication link communicating with the child node buffers two handshake data packets. It polls four communication links. After each hierarchical splicing, one data packet is transmitted. The number of data packets transmitted after one hierarchical splicing is half the number of data packets transmitted by the child layer.

7. The quadtree monitoring network design method as described in claim 6, characterized in that, In step S3, the network transmission protocol design step requires the network transmission protocol to include the monitoring unit ID number, data packet sequence number, data and completion indicator bits. The data bit width is adjusted according to different levels, and the network communication protocol is designed in layers.

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