Preventing overwriting of shared memory segments

Abstract

A technique for preventing overwriting of a shared line segment is disclosed. The technique includes sending a data unit from a first processor to a second processor using an enhanced hardware cache coherence protocol, the enhanced hardware cache coherence protocol being enhanced to maintain dirty bit information during the exchange of the data unit within the cache coherence domain. The size of the data unit is a fraction of the size of any shared line of the shared memory, and writing the data unit to a segment of the shared line of the shared memory includes using another protocol without overwriting another segment of the shared line. The write is based at least in part on the dirty bit information, and the another protocol does not support hardware coherence and maintains the dirty bit information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the filing date of U.S. Provisional Application No. 63 / 084,091 (filed on September 28, 2020), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the technical field of shared memory, and more particularly to a technique for preventing overwriting of line segments shared between different processing units. Background Art

[0004] Advanced driver assistance systems (ADAS) and autonomous vehicle (AV) systems use cameras and other sensors along with object classifiers designed to detect specific objects in the environment of a vehicle traveling on the road. Object classifiers are designed to detect predefined objects and are used within ADAS and AV systems to control the vehicle or warn the driver based on the type of object detected, its location, and more.

[0005] As ADAS and AV systems evolve toward fully autonomous operation, it will be beneficial to protect the data generated by these systems.

[0006] In addition, a system on a chip (SoC) can be implemented as an integral part of an ADAS and / or AV system. The SoC includes a variety of processing units, memory units, and other units that can exchange data in various ways and using different protocols. The SoC can implement memory that is shared between the various processing units. For example, the shared memory can have an architecture such that lines of shared memory are shared between different processing units of the SoC. One type of sharing involves assigning different shared line segments to different processing units so that different processing units can modify their assigned shared line segments without overwriting other shared line segments assigned to other processing units. This is typically achieved through the use of a "dirty bit" that indicates which shared line segments can and cannot be written to by a particular processing unit.

[0007] Various technologies have been proposed to manage the transfer of data and the interoperability of different processing units of SoCs. For example, the ARM Advanced Microcontroller Bus Architecture (AMBA™) is an open standard on-chip interconnect specification for the connection and management of functional blocks in such system-on-chip (SoC) designs (see www.wikipedia.org). AMBA™ promotes the development of multi-processor designs with a large number of controllers and peripherals using a bus architecture. AMBA™ was introduced by ARM in 1996. In 2003, ARM introduced the third generation AMBA™ 3, including the Advanced Extensible Interface (AXI) and Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. In 2011, ARM introduced AMBA™ 4, which includes the AXI Coherence Extension (ACE) protocol.

[0008] It has been discovered that in various scenarios involving data units being sent using different protocols—particularly when a first processor modifies a data unit and a second processor (which shares a cache coherence domain with the first processor) requests to retrieve the data unit—the dirty bit can be removed. In such situations, i.e., when the dirty bit is removed from the communication and / or does not reach a certain processing unit, the processing unit can then overwrite data segments that were not assigned to that processing unit. Therefore, there is a growing need to provide a solution that will prevent overwriting of data units in shared memory. Summary of the Invention

[0009] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the following description to represent the same or similar parts. Although several illustrative embodiments are described herein, modifications, adaptations, and other implementations are possible. For example, components shown in the drawings may be replaced, added, or modified, and the illustrative methods described herein may be modified by replacing, reordering, removing, or adding steps to the disclosed methods. Accordingly, the following detailed description is not limited to the disclosed embodiments and examples.

[0010] The disclosed embodiments provide systems and methods that can be used as a component of or in conjunction with autonomous navigation / driving and / or driver assistance technology features. Driver assistance technology refers to any appropriate technology that assists a driver in navigating and / or controlling their vehicle, such as FCW, LDW, and TSR, as opposed to fully autonomous driving. In various embodiments, the system may include one, two, or more cameras that may be installed in the vehicle and an associated processor that monitors the vehicle's environment. In other embodiments, additional types of sensors may be installed in the vehicle and can be used in the autonomous navigation and / or driver assistance systems. In some examples of the presently disclosed subject matter, the system may provide technology for processing images of the environment in front of a vehicle traveling on a road for use in training a neural network or deep learning algorithm to estimate the vehicle's future path based on the images. In yet other examples of the presently disclosed subject matter, the system may provide technology for using a trained neural network to process images of the environment in front of a vehicle traveling on a road to estimate the vehicle's future path.

[0011] Systems and methods as described in the claims and specification are provided herein.

[0012] Any combination of any subject matter of any claims may be provided.

[0013] Any combination of any methods and / or method steps disclosed in any figures and / or in the specification may be provided.

[0014] Any combination of any units, devices and / or components disclosed in any figures and / or the specification may be provided. Non-limiting examples of such units include an acquisition unit, an image processor, and the like.

[0015] As discussed in greater detail herein, the disclosed embodiments may include methods, apparatus, and computer-readable media (eg, non-transitory computer-readable media) for preventing overwriting of shared memory line segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The subject matter of aspects of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, the disclosure as to the organization and method of operation, together with objects, features, and advantages thereof, will be best understood from the following detailed description when read with the accompanying drawings, including:

[0017] Figure 1 is a block diagram representation of a system in accordance with the disclosed embodiments;

[0018] Figure 2A is a diagrammatic side view representation of an exemplary vehicle including a system in accordance with the disclosed embodiments;

[0019] Figure 2B According to the disclosed embodiments, Figure 2Aa diagrammatic top view representation of the vehicle and systems shown;

[0020] Figure 2C is a diagrammatic top view representation of another embodiment of a vehicle including a system in accordance with the disclosed embodiments;

[0021] Figure 2D is a diagrammatic top view representation of yet another embodiment of a vehicle including a system in accordance with the disclosed embodiments;

[0022] Figure 2E is a diagrammatic representation of an exemplary vehicle control system in accordance with the disclosed embodiments;

[0023] Figure 3 is a diagrammatic representation of a vehicle interior including a rearview mirror and a user interface for a vehicle imaging system in accordance with a disclosed embodiment;

[0024] Figure 4A An example of a portion of an apparatus according to the disclosed embodiments is shown;

[0025] Figure 4B An example showing a portion of an apparatus in accordance with the disclosed embodiments; and

[0026] Figure 5A An example of a method according to the disclosed embodiment is shown.

[0027] Figure 5B An example of a method according to the disclosed embodiment is shown. DETAILED DESCRIPTION

[0028] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the following description to represent the same or similar parts. Although several illustrative embodiments are described herein, modifications, adaptations, and other implementations are possible. For example, components shown in the drawings may be replaced, added, or modified, and the illustrative methods described herein may be modified by replacing, reordering, removing, or adding steps to the disclosed methods. Accordingly, the following detailed description is not limited to the disclosed embodiments and examples.

[0029] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the present disclosure can be practiced without these specific details. In other instances, well-known methods, processes, and components have not been described in detail in order to avoid obscuring an understanding of the present disclosure.

[0030] The subject matter which is regarded as the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, the disclosure both as to organization and method of operation, together with objects, features, and advantages thereof, will best be understood from a reading of the following detailed description with reference to the accompanying figures.

[0031] It will be understood that for simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals may be repeated between the drawings to indicate corresponding or similar elements.

[0032] Because the illustrated embodiments of the present disclosure can be implemented to a large extent using electronic components and circuits known to those skilled in the art, details will not be described to any greater extent than is deemed necessary as described above in order to appreciate and understand the basic concepts of the disclosure and not to obscure or distract from the teachings of the disclosure.

[0033] Any reference to a method in the specification applies mutatis mutandis to a system capable of performing the method and should apply mutatis mutandis to a non-transitory computer-readable medium storing instructions that, once executed by a computer, cause the method to be performed.

[0034] Any reference in the specification to the system and any other components should be applied mutatis mutandis to methods executable by the memory device and should be applied mutatis mutandis to non-transitory computer-readable media storing instructions executable by the memory device.

[0035] Any reference in the specification to a non-transitory computer-readable medium should apply, with appropriate modifications, to a system capable of executing instructions stored in a non-transitory computer-readable medium, and should apply, with appropriate modifications, to a method executable by a computer that reads instructions stored in a non-transitory computer-readable medium.

[0036] Any combination of any modules or units listed in any of the drawings, any part of the specification and / or any claims may be provided. In particular, any combination of any claimed features may be provided.

[0037] A pixel may be a picture element obtained by a camera and may be a processed picture element.

[0038] Before discussing in detail examples of processing images of the environment ahead of a vehicle traveling on a road for use in training a neural network or deep learning algorithm to estimate features of the vehicle's future path based on the images, or using a trained neural network to process images of the environment ahead of a vehicle traveling on a road to estimate features of the vehicle's future path, a description is provided of various possible implementations and configurations of a vehicle-mountable system that can be used to perform and implement methods according to examples of the presently disclosed subject matter. In some embodiments, various examples of the system can be installed in a vehicle and can be operated while the vehicle is in motion. In some embodiments, the system can implement methods according to examples of the presently disclosed subject matter.

[0039] However, it will be understood that embodiments of the present disclosure are not limited to situations where suspected upright object indications are caused by passing through high-level roads. Suspected upright object indications can be associated with a variety of other situations and can be generated from other types of image data and also from data that is not image-based or not exclusively image-based.

[0040] Part IA. Vehicle Systems and Operations

[0041] Now referring to Figure 1 is a block diagram representation of a system according to the disclosed embodiments. System 100 can include various components depending on the requirements of a particular implementation. In some examples, system 100 can include a processing unit 110, an image acquisition unit 120, and one or more memory units 140, 150. Processing unit 110 can include one or more processing devices. In some embodiments, processing unit 110 can include an application processor 180, an image processor 190, or any other suitable processing device. Similarly, image acquisition unit 120 can include any number of image acquisition units and components depending on the requirements of a particular application. In some embodiments, image acquisition unit 120 can include one or more image capture devices (e.g., cameras), such as image capture device 122, image capture device 124, and image capture device 126. In some embodiments, system 100 can also include a data interface 128 that communicatively connects processing unit 110 to image acquisition unit 120. For example, data interface 128 can include one or more wired and / or wireless links for transmitting image data acquired by image acquisition unit 120 to processing unit 110.

[0042] Both the application processor 180 and the image processor 190 can include various types of processing devices. For example, either or both of the application processor 180 and the image processor 190 can include one or more microprocessors, preprocessors (e.g., image preprocessors), graphics processors, central processing units (CPUs), support circuits, digital signal processors, integrated circuits, memories, or any other type of device suitable for running applications and suitable for image processing and analysis. In some embodiments, the application processor 180 and / or the image processor 190 can include any type of single-core or multi-core processor, mobile device microcontroller, central processing unit, etc. Various processing devices can be used, including, for example, processors such as processors available from manufacturers such as , and can include various architectures (e.g., x86 processors, wait).

[0043] In some embodiments, the application processor 180 and / or the image processor 190 can include Any of the available EyeQ series of processor chips. Each of these processor designs includes multiple processing units with local memory and instruction sets. Such processors may include video inputs for receiving image data from multiple image sensors and may also include video output capabilities. In one example, Using 90nm-microtechnology operating at 332Mhz. Architecture features two floating point hyperthreaded 32-bit RISC CPUs ( cores), five visual computing engines (VCEs), and three vector microcode processors Denali 64-bit mobile DDR controller, 128-bit internal Sonics interconnect, dual 16-bit video input and 18-bit video output controllers, 16-channel DMA and several peripherals. MIPS34K CPU manages five VCEs, three and DMA, a second MIPS34K CPU and multi-channel DMA and other peripherals. Five VCEs, three and MIPS34K CPUs are capable of performing the intensive visual computations required by multi-function bundled applications. In another example, It is a third generation processor and is faster than In yet another example, a fourth generation processor Can be used in the disclosed examples.

[0044] Although Figure 1Two independent processing devices are shown as being included in processing unit 110, but more or fewer processing devices can be used. For example, in some examples, a single processing device can be used to complete the tasks of application processor 180 and image processor 190. In other embodiments, these tasks can be performed by more than two processing devices.

[0045] The processing unit 110 can include various types of devices. For example, the processing unit 110 may include various devices, such as a controller, an image processor, a central processing unit (CPU), support circuits, a digital signal processor, an integrated circuit, memory, or any other type of device for image processing and analysis. The image preprocessor can include a video processor for capturing, digitizing, and processing images from the image sensor. The CPU can include any number of microcontrollers or microprocessors. The support circuits can be any number of circuits generally known in the art, including caches, power supplies, clocks, and input-output circuits. The memory can store software that, when executed by the processor, controls the operation of the system. The memory can include databases and image processing software, including trained systems such as neural networks. The memory can include any number of random access memories, read-only memories, flash memories, disk drives, optical storage devices, removable storage devices, and other types of storage devices. In one embodiment, the memory can be separate from the processing unit 110. In another embodiment, the memory can be integrated into the processing unit 110.

[0046] Each memory 140, 150 can include software instructions that, when executed by a processor (e.g., application processor 180 and / or image processor 190), can control various aspects of the operation of system 100. These memory units can include various databases and image processing software. The memory units can include random access memory, read-only memory, flash memory, disk drives, optical storage devices, tape storage devices, removable storage devices, and / or other types of storage devices. In some examples, the memory units 140, 150 can be separate from the application processor 180 and / or image processor 190. In other embodiments, these memory units can be integrated into the application processor 180 and / or image processor 190.

[0047] In some embodiments, the system can include a location sensor 130. Location sensor 130 can include any type of device suitable for determining a location associated with at least one component of system 100. In some embodiments, location sensor 130 can include a GPS receiver. Such a receiver can determine user location and velocity by processing signals broadcast by global positioning system satellites. Location information from location sensor 130 can be made available to application processor 180 and / or image processor 190.

[0048] In some embodiments, the system 100 can be operatively connected to various systems, devices, and units on a vehicle in which the system 100 can be installed, and the system 100 can communicate with the vehicle's systems via any suitable interface (e.g., a communication bus). Examples of vehicle systems with which the system 100 can cooperate include: a throttle system, a braking system, and a steering system.

[0049] In some embodiments, system 100 can include a user interface 170. User interface 170 can include any device suitable for providing information to one or more users of system 100 or for receiving input from one or more users, including, for example, a touch screen, a microphone, a keyboard, a pointing device, a track wheel, a camera, knobs, buttons, etc. Information can be provided by system 100 to the user via user interface 170.

[0050] In some embodiments, system 100 may include a map database 160. Map database 160 may comprise any type of database for storing digital map data. In some examples, map database 160 may include data related to the locations of various items in a reference coordinate system, including roads, water features, geographic features, points of interest, and the like. Map database 160 may store not only the locations of such items but also descriptors associated with those items, including, for example, names associated with each of the stored features and other information related to them. For example, the database may include the location and type of known obstacles, information related to the topography of the road, or the slope at certain points along the road. In some embodiments, map database 160 may be physically located with the other components of system 100. Alternatively, or in addition, map database 160 or portions thereof may be remotely located relative to other components of system 100 (e.g., processing unit 110). In such embodiments, information from map database 160 may be downloaded via a wired or wireless data connection to a network (e.g., via a cellular network and / or the Internet).

[0051] Image capture devices 122, 124, and 126 can each include any type of device suitable for capturing at least one image from the environment. Furthermore, any number of image capture devices can be used to acquire images for input to the image processor. Some examples of the presently disclosed subject matter can include or be implemented using only a single image capture device, while other examples can include or be implemented using two, three, or even four or more image capture devices. Figures 2B-2E Image capture devices 122, 124, and 126 are further described.

[0052] It will be understood that the system 100 can include or be operatively associated with other types of sensors, including, for example, acoustic sensors, RF sensors (e.g., radar transceivers), LIDAR sensors, etc. Such sensors can be used independently of or in conjunction with the image acquisition unit 120. For example, data from a radar system (not shown) can be used to validate processed information received from processing images acquired by the image acquisition unit 120, such as to filter out certain false positives resulting from processing images acquired by the image acquisition unit 120, or it can be combined with or otherwise supplement image data from the image acquisition unit 120 or some processed variation or derivative of the image data from the image acquisition unit 120.

[0053] The system 100 or its various components can be incorporated into a variety of different platforms. In some embodiments, the system 100 can be included in a vehicle 200, such as Figure 2A For example, the vehicle 200 can be equipped with the processing unit 110 and any of the other components of the system 100, as described above with respect to Figure 1 While in some embodiments the vehicle 200 can be equipped with only a single image capture device (e.g., a camera), in some embodiments such as in combination with Figures 2B-2E In other embodiments, such as those described above, multiple image capture devices can be used. For example, Figure 2A As shown, either of the image capture devices 122 and 124 of vehicle 200 can be part of an ADAS (Advanced Driver Assistance System) imaging suite.

[0054] The image capture device included on the vehicle 200 as part of the image acquisition unit 120 can be positioned at any suitable location. In some embodiments, Figures 2A-2E and Figure 3 As shown, image capture device 122 can be located near a rearview mirror. This location can provide a similar line of sight to the driver of vehicle 200, which can help determine what is and is not visible to the driver.

[0055] Other locations for the image capture devices of image capture unit 120 can also be used. For example, image capture device 124 can be located on or in the bumper of vehicle 200. This location can be particularly suitable for image capture devices with a wide field of view. The line of sight of a bumper-positioned image capture device can be different from the driver's line of sight. Image capture devices (e.g., image capture devices 122, 124, and 126) can also be located in other locations. For example, the image capture device can be located on or in one or both of the side mirrors of vehicle 200, on the roof of vehicle 200, on the hood of vehicle 200, on the trunk of vehicle 200, on the side of vehicle 200, mounted on, positioned behind, or positioned in front of any of the windows of vehicle 200, mounted in or near light images on the front and / or rear of vehicle 200, etc. Image capture unit 120, or an image capture device that is one of multiple image capture devices used in image capture unit 120, can have a field of view (FOV) that is different from the driver of the vehicle and may not necessarily see the same objects. In one example, the FOV of image acquisition unit 120 can extend beyond the FOV of a typical driver and, therefore, can image objects outside the driver's FOV. In yet another example, the FOV of image acquisition unit 120 is a portion of the driver's FOV. In some embodiments, the FOV of image acquisition unit 120 corresponds to a sector that covers the area of ​​the road ahead of the vehicle and, possibly, also the surrounding area of ​​the road.

[0056] In addition to the image capture device, the vehicle 200 can also include various other components of the system 100. For example, the processing unit 110 can be included on the vehicle 200, integrated with the vehicle's engine control unit (ECU), or separate. The vehicle 200 can also be equipped with a location sensor 130 (e.g., a GPS receiver) and can also include a map database 160 and memory units 140 and 150.

[0057] Figure 2A is a diagrammatic side view representation of a vehicle imaging system according to an example of the presently disclosed subject matter. Figure 2B yes Figure 2A A diagrammatic top view illustration of the example shown. Figure 2B As shown, the disclosed example can include a vehicle 200 that includes the system 100 in a vehicle body having a first image capture device 122 positioned near a rearview mirror and / or near a driver of the vehicle 200, a second image capture device 124 positioned on or in a bumper area (e.g., one of the bumper areas 210) of the vehicle 200, and a processing unit 110.

[0058] like Figure 2CAs shown, both image capture devices 122 and 124 may be positioned near a rearview mirror and / or near the driver of vehicle 200. Figure 2B and Figure 2C Two image capture devices 122 and 124 are shown in FIG, but it should be understood that other embodiments may include more than two image capture devices. Figure 2D In the illustrated embodiment, first, second, and third image capture devices 122 , 124 , and 126 are included in the system 100 of a vehicle 200 .

[0059] like Figure 2D As shown, image capture devices 122, 124, and 126 may be positioned near rearview mirrors and / or near the driver's seat of vehicle 200. The disclosed examples are not limited to any particular number and configuration of image capture devices, and the image capture devices may be positioned at any suitable location within and / or on vehicle 200.

[0060] It is also understood that the disclosed embodiments are not limited to a particular type of vehicle 200 and may be applicable to all types of vehicles, including automobiles, trucks, trailers, motorcycles, bicycles, self-balancing transporters, and other types of vehicles.

[0061] First image capture device 122 can include any suitable type of image capture device. Image capture device 122 can include an optical axis. In one example, image capture device 122 can include an Aptina M9V024W VGA sensor with a global shutter. In another example, a rolling shutter can be used. Image acquisition unit 120 and any image capture device implemented as part of image acquisition unit 120 can have any desired image resolution. For example, image capture device 122 can provide a resolution of 1280×960 pixels and can include a rolling shutter.

[0062] Image acquisition unit 120 and any image capture device implemented as part of image acquisition unit 120 can include various optical elements. In some embodiments, one or more lenses can be included, for example, to provide a desired focal length and field of view for image acquisition unit 120 and any image capture device implemented as part of image acquisition unit 120. In some examples, an image capture device implemented as part of image acquisition unit 120 can include or be associated with any optical element (e.g., a 6 mm lens or a 12 mm lens). In some examples, image capture device 122 can be configured to capture images with a desired (and known) field of view (FOV).

[0063] The first image capture device 122 may have a scan rate associated with the acquisition of each of the first series of image scan lines. The scan rate may represent the rate at which the image sensor is able to acquire image data associated with each pixel included in a particular scan line.

[0064] Figure 2E is a diagrammatic representation of a vehicle control system according to an example of the presently disclosed subject matter. Figure 2E As shown, vehicle 200 can include a throttle system 220, a brake system 230, and a steering system 240. System 100 can provide input (e.g., control signals) to one or more of throttle system 220, brake system 230, and steering system 240 via one or more data links (e.g., one or more wired and / or wireless links for transmitting data). For example, based on analysis of images captured by image capture devices 122, 124, and / or 126, system 100 can provide control signals to one or more of throttle system 220, brake system 230, and steering system 240 to navigate vehicle 200 (e.g., by inducing acceleration, turning, lane deviation, etc.). In addition, system 100 can receive input from one or more of throttle system 220, brake system 230, and steering system 240 indicating the operating condition of vehicle 200 (e.g., speed, whether vehicle 200 is braking and / or turning, etc.).

[0065] like Figure 3 As shown, vehicle 200 may also include a user interface 170 for interacting with the driver or passengers of vehicle 200. For example, user interface 170 in a vehicle application may include a touch screen 320, a knob 330, buttons 340, and a microphone 350. The driver or passengers of vehicle 200 may also interact with system 100 using handles (e.g., located on or near the steering column of vehicle 200, including, for example, a turn signal handle), buttons (e.g., located on the steering wheel of vehicle 200), and the like. In some embodiments, microphone 350 may be positioned adjacent to rearview mirror 310. Similarly, in some embodiments, image capture device 122 may be located near rearview mirror 310. In some embodiments, user interface 170 may also include one or more speakers 360 (e.g., speakers of a vehicle audio system). For example, system 100 may provide various notifications (e.g., warnings) via speakers 360.

[0066] As will be appreciated by those skilled in the art having the benefit of this disclosure, numerous variations and / or modifications may be made to the embodiments disclosed above. For example, not all components are essential to the operation of system 100. Furthermore, any component may be located in any appropriate portion of system 100, and the components may be rearranged in a variety of configurations while still providing the functionality of the disclosed embodiments. Therefore, the configurations described above are examples, and regardless of the configurations described above, system 100 is capable of providing a wide range of functionality for analyzing the environment surrounding vehicle 200 and navigating and / or otherwise controlling and / or operating vehicle 200 in response to this analysis. Navigation, control, and / or operation of vehicle 200 may include enabling and / or disabling (directly or via an intermediate controller, such as the controller described above) various features, components, devices, modes, systems, and / or subsystems associated with vehicle 200. Alternatively, or in addition, navigation, control, and / or operation may include interacting with a user, driver, passengers, pedestrians, and / or other vehicles or users that may be located inside or outside vehicle 200, for example, by providing visual, audio, tactile, and / or other sensory alerts and / or indications.

[0067] As discussed in more detail below and in accordance with various disclosed embodiments, system 100 can provide a variety of features related to autonomous driving, semi-autonomous driving, and / or driver assistance technologies. For example, system 100 can analyze image data, location data (e.g., GPS location information), map data, speed data, and / or data from sensors included in vehicle 200. System 100 can collect data from, for example, image acquisition unit 120, location sensor 130, and other sensors for analysis. Furthermore, system 100 can analyze the collected data to determine whether vehicle 200 should take a certain action and then automatically take the determined action without human intervention. It will be appreciated that in some cases, the actions automatically taken by the vehicle are under human supervision, and that the ability for a human to intervene, adjust, abort, or override the machine's actions is enabled in some cases or at all times. For example, when vehicle 200 is navigating without human intervention, system 100 can automatically control the braking, acceleration, and / or steering of vehicle 200 (e.g., by sending control signals to one or more of throttle system 1220, braking system 1230, and steering system 1240). In addition, the system 100 can analyze the collected data and issue warnings, instructions, recommendations, alerts, or instructions to the driver, passengers, users, or others inside or outside the vehicle (or to other vehicles) based on the analysis of the collected data. Additional details regarding various embodiments provided by the system 100 are provided below.

[0068] B. Prevent overwriting of shared memory segments

[0069] Lines of shared memory can be shared between different units.

[0070] One type of sharing involves assigning different shared segments to different cells, such that different cells can modify their assigned shared segments without overwriting other shared segments assigned to other cells.

[0071] The dirty bits indicate which shared line segments can be written to and which cannot be written to by a unit.

[0072] When the dirty bit is removed or does not reach a unit, the unit can overwrite the data segment that is not assigned to the unit.

[0073] The ARM Advanced Microcontroller Bus Architecture (AMBA™) is an open-standard on-chip interconnect specification for connecting and managing functional blocks in system-on-chip (SoC) designs (see www.wikipedia.org). It facilitates the development of multiprocessor designs with a large number of controllers and peripherals using a bus architecture. AMBA is a registered trademark of ARM Ltd in the United Kingdom.

[0074] AMBA™ was introduced by ARM in 1996. In 2003, ARM introduced the third generation AMBA™ 3, which included the Advanced eXtensible Interface (AXI) and Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. In 2011, ARM introduced AMBA™ 4, which included the AXI Coherence Extensions (ACE) protocol.

[0075] A system on a chip may include a variety of processing units, memory units, and other units that may exchange data in various ways and using different protocols.

[0076] It has been discovered that the dirty bit can be removed in various situations involving sending data units using different protocols - particularly when a first processor modifies a data unit and a second processor (sharing a cache coherence domain with the first processor) requests to retrieve the data unit.

[0077] There is an increasing need to provide a solution that will prevent overwriting of data units in shared memory.

[0078] Figure 4A An example of a portion of an apparatus 400 is shown. The portion of the apparatus may be included in an integrated circuit, may be included on more than a single integrated circuit, etc. Portion 400 may, for example, belong to processing unit 110 of the previous figures.

[0079] Figure 4A Two clusters of processing units are shown. The number of clusters may be one, or may be or exceed two.

[0080] Clustering can simplify maintaining consistency by introducing a hierarchical structure where each cluster maintains its consistency and additional measures are taken to maintain consistency between clusters. This simplifies maintaining consistency, especially when there are many processing units that should access shared memory while maintaining consistency.

[0081] The first cluster includes a first processor 410, a second processor 420, a first coherency fabric 430, a first processing unit 450, and a first shared memory 440. The first cluster may include additional processing units and / or additional interconnects or any other units.

[0082] The first processor 410 may include a first first level cache 411. The second processor 420 may include a second first level cache 421.

[0083] The first processor 410 and the second processor 420 are in a first cache coherence domain.

[0084] The first coherency structure 430 is located between (a) the first processor 410 and the second processor 420 and (b) the first shared memory 440 .

[0085] The first and second processors may communicate using an enhanced hardware cache coherence protocol. The enhanced hardware cache coherence protocol is enhanced to maintain dirty bit information during exchanges of data units within the first cache coherence domain.

[0086] The first processing unit 450 , the first coherency fabric 430 , and the first shared memory 440 may communicate with each other using another protocol (“other” protocol) that differs from the enhanced hardware cache coherency protocol because it does not support hardware coherency and maintains dirty bit information.

[0087] The second cluster includes third processor 412, fourth processor 422, second coherency fabric 432, second processing unit 452, and second shared memory 442. The second cluster may include additional processing units and / or additional interconnects or any other units.

[0088] The third processor 412 and the fourth processor 422 are in the second cache coherence domain.

[0089] The third processor 412 may include a third first level cache 413. The fourth processor 422 may include a fourth first level cache 423.

[0090] The second coherency structure 432 is located between (a) the third processor 412 and the fourth processor 422 and (b) the second shared memory 442 .

[0091] The third and fourth processors may communicate using an enhanced hardware cache coherence protocol.

[0092] The second processing unit 452 , the second coherency structure 432 , and the second shared memory 442 may communicate with each other using other protocols.

[0093] The first and second shared memories 440 and 442 may be cache memories or may be distinct from cache memories.The first and second shared memories may be the same memory unit.

[0094] The first shared memory 440 and the second shared memory 442 are coupled to a third coherency structure 460 , which is further coupled to a third shared memory 470 .

[0095] Figure 4B Portion 450 and the various steps performed by portion 450 are shown.

[0096] Assume that the first and second processors can only update the first segment 490.1 of the shared memory line 490—but are not allowed to update the second segment 490.2 of the shared memory line. A shared memory line can have any size. For example, it can include two or more (e.g., 64) bytes.

[0097] The first segment 490.1 may be assigned to a first cluster, while the second segment 490.2 may be assigned to a second cluster.

[0098] The allocation may be fixed or may vary over time. Different clusters may receive segments of the same size, while at least two clusters may be allocated segments of different sizes.

[0099] The first processor, the second processor, and any units of portion 450 may perform the following steps:

[0100] The previous version DU(n-1) 480 of the data unit is retrieved by the first processor 410 from the first shared memory 440 (or from any other shared memory - including the third shared memory 470).

[0101] A previous version of the data unit is modified by the first processor to provide data unit DU(n) 482. The data unit is smaller than the shared memory line, and a dirty bit indicating a modified data unit is generated to indicate that the data unit is modified.

[0102] The data unit is requested (eg, by the second processor via the first coherency structure 430). This is done before the data unit is written to the shared memory.

[0103] The data unit DU(N) 482 is sent (using the enhanced hardware cache coherence protocol) with a dirty bit Db(n) 488 indicating that only this data unit is to be modified. The first and second processors are allowed to update only the first segment 490.1 - not the second segment 490.2.

[0104] The data unit 482(n) is modified by the second processor to provide a new data unit DU(n+1) 483, and the dirty bit is updated to reflect the modification.

[0105] The new data unit is written to the first segment 490.1 without overwriting the second segment 490.2. Thus, the new data unit is written without modifying the second segment 490.2.

[0106] It should be noted that the resolution of the dirty bit can be finer than the size of the data unit, and that modification of a portion of a data unit can be signaled by the dirty bit information. For example, each byte can have an assigned dirty bit, and a data unit can be two or more bits long—thus assigning multiple dirty bits to a single data unit. Any reference to modification of a data unit should apply mutatis mutandis to modification of a portion of a data unit.

[0107] Figure 5A A method 500 of preventing overwriting of cache information is shown.

[0108] Step 500 may include a preliminary step 510 .

[0109] Step 510 may include:

[0110] Step 511 of retrieving, by the first processor, a previous version of the data unit from the shared memory.

[0111] A previous version of the data unit is modified by the first processor to provide a step 513 of the data unit.

[0112] A step 515 of generating a request by the second processor to retrieve the data unit.

[0113] Step 510 may be followed by step 520 of sending the data unit from the first processor to the second processor using the enhanced hardware cache coherence protocol. The enhanced hardware cache coherence protocol is enhanced to maintain dirty bit information during exchanges of data units within a cache coherence domain.

[0114] It should be noted that applying hardware cache coherence (without enhancement) may cause the dirty bit information to be lost—and cause the second processor to overwrite the entire shared line when writing to the shared memory. This overwrite may delete the contents of other segments written to the shared line.

[0115] The size of the data unit is a fraction of the size of any shared line of shared memory.

[0116] Step 520 may be performed before the first processor sends the data unit to the shared memory.

[0117] Step 520 may be followed by step 530 of writing the data unit to a segment of a shared line of shared memory using another protocol without overwriting another segment of the shared line, wherein the writing is based at least in part on the dirty bit information, and wherein the other protocol does not support hardware coherency and preserves the dirty bit information.

[0118] Method 500 may further include step 540 of writing, by a processing entity outside the cache coherence domain, another data unit to another segment of the shared line. Step 540 may be performed in parallel with any of steps 510, 520, and 530.

[0119] The other protocol may be an Advanced Extensible Interface (AXI) protocol, and the enhanced hardware coherency protocol may be an Enhanced AXI Coherency Extensions (ACE) protocol.

[0120] The ACE protocol supports various enhanced consistency commands, such as:

[0121] ReadShared—Requests a read of any cache line in the dirty / shared state (which the requesting master typically does not have).

[0122] ReadUnique—Requests to read a cache line (which the requesting master typically does not have) that is in Unique state (i.e., no other master has a copy of it). Typically because the master expects to write to it.

[0123] CleanUnique—Requests that a cache line (the requesting master usually already has a cache line in the shared state) be changed to the unique state, usually because the master anticipates writing to it.

[0124] Step 530 may include sending the data unit to the first coherency structure, and sending the data unit from the first coherency structure to the segment of the shared line.

[0125] Although steps 510, 520, and 530 are shown relative to certain units, it should be noted that steps 510, 520, and 530 may be performed by other and / or additional units. For example, it may be performed for multiple clusters.

[0126] For example, method 500 may include: (a) sending another data unit from a third processor to a fourth processor using an enhanced hardware cache coherence protocol, wherein a size of the another data unit is a fraction of a size of any shared line of another shared memory; and (b) writing the another data unit to a segment of a shared line of another shared memory using another protocol without overwriting another segment of the shared line, wherein the write is based at least in part on dirty bit information.

[0127] Section IIA. Additional Vehicle Systems and Operations

[0128] This document provides examples of processing images of the environment ahead of a vehicle traveling on a road for use in training neural networks, deep learning algorithms to estimate features of the vehicle's future path based on the images, and using trained neural networks to process images of the environment ahead of a vehicle traveling on a road to estimate features of the vehicle's future path. Before disclosing the details of these example features, a description of various possible implementations and configurations of vehicle-mountable systems that can be used to implement embodiments of the presently disclosed subject matter is provided. In some embodiments, various examples of the system can be installed in a vehicle and can be operated while the vehicle is in motion. In some embodiments, the system can implement methods according to examples of the presently disclosed subject matter.

[0129] Figure 1 1 shows an exemplary block diagram of a system according to one or more embodiments of the present disclosure. Figure 1 The illustrated system 100 may include various components depending on the requirements of a particular implementation. In some examples, the system 100 may include a processing unit 110 , an image acquisition unit 120 , and one or more memory units 140 , 150 .

[0130] The processing unit 110 may alternatively be referred to herein as a processing circuit and may include one or more processors or processing devices, software components, or a combination of these. In some embodiments, the processing unit 110 may include an application processor 180, an image processor 190, or any other appropriate processing device. Similarly, the image acquisition unit 120 may alternatively be referred to herein as an image acquisition circuit and may include one or more processors or processing devices, software components, or a combination of these. The image acquisition unit 120 may include any appropriate number of processors or processing devices and / or components (which may include software executable components) configured to perform image acquisition, depending on the requirements of a particular application. In some embodiments, the image acquisition unit 120 may include one or more image capture devices (e.g., photographic devices), such as image capture device 122, image capture device 124, and image capture device 126.

[0131] In some embodiments, the system 100 may further include a data interface 128, which is configured as any suitable type of hardware component, software component, or combination thereof configured to communicatively connect the processing unit 110 to the image acquisition unit 120. For example, the data interface 128 can include any number of wired and / or wireless links, buses, terminals, ports, links, etc. for transmitting image data acquired by the image acquisition unit 120 to the processing unit 110.

[0132] Both the application processor 180 and the image processor 190 may be implemented as any suitable number and / or type of processing devices. For example, either or both of the application processor 180 and the image processor 190 may be implemented as one or more microprocessors, preprocessors (e.g., image preprocessors), graphics processors, central processing units (CPUs), support circuits, digital signal processors, integrated circuits, memories, or any other type of device suitable for running applications and suitable for image processing and analysis. In some embodiments, the application processor 180 and / or the image processor 190 may be implemented as any suitable type of single-core or multi-core processor, mobile device microcontroller, central processing unit, etc. A variety of processing devices may be used, including, for example, processors such as processors available from manufacturers such as, for example, x86 processors, wait).

[0133] In some embodiments, the application processor 180 and / or the image processor 190 may be implemented as Any of the available EyeQ series of processor chips. These processor designs may include multiple processing units with local memory and instruction sets. Such processors may include video inputs for receiving image data from multiple image sensors and may also include video output capabilities. In one example, Using 90nm-microtechnology operating at 332Mhz. Architecture features two floating point hyperthreaded 32-bit RISC CPUs ( cores), five visual computing engines (VCEs), and three vector microcode processors Denali 64-bit mobile DDR controller, 128-bit internal Sonics interconnect, dual 16-bit video input and 18-bit video output controllers, 16-channel DMA and several peripherals. MIPS34K CPU manages five VCEs, three and DMA, a second MIPS34K CPU and multi-channel DMA and other peripherals. Five VCEs, three and MIPS34K CPUs are capable of performing the intensive visual computations required by multi-function bundled applications. In another example, It is a third generation processor and is faster than In yet another example, a fourth generation processor Can be used in the disclosed examples.

[0134] Although Figure 1 While two independent processing devices are shown as being included in processing unit 110, embodiments include processing unit 110 implemented using any suitable number of processors and / or processing devices. For example, in some examples, a single processing device may be used to perform the tasks of application processor 180 and image processor 190. As another example, in other embodiments, these tasks may be performed by more than two processing devices.

[0135] The processing unit 110 may be implemented as any suitable type of device. For example, the processing unit 110 may be implemented as various devices, such as a controller, an image processor, a central processing unit (CPU), support circuits, a digital signal processor, an integrated circuit, a memory, or any other suitable type of device for image processing and analysis. The image preprocessor may include a video processor for capturing, digitizing, and processing images from the image capture devices 122, 124, 126. The CPU may include any suitable number and / or type of microcontroller or microprocessor. The support circuits may include any suitable number and / or type of circuits, including circuits known in the art, such as caches, power supplies, clocks, and input-output circuits.

[0136] System 100 may include any suitable number of memory units, with two memory units 140, 150 being shown for simplicity. Figure 1 . Memory units 140, 150 may alternatively be referred to herein as memories. Memories 140 and / or 150 may store software that, when executed by any appropriate processor (e.g., one or more processors identified by processing unit 110), controls the operation of system 100. Memories 140 and / or 150 may include databases and / or image processing software, including trained systems such as, for example, neural networks. Memories 140 and / or 150 may include any appropriate number of random access memories, read-only memories, flash memories, disk drives, optical storage devices, removable storage devices, and any other appropriate type of storage device. In one example, memories 140 and / or 150 may be separate from processing unit 110. In another example, memories 140 and / or 150 may be integrated into processing unit 110.

[0137] Each of memories 140, 150 may include software instructions (i.e., computer-readable and executable instructions) that, when executed by a processor (e.g., application processor 180 and / or image processor 190), may control various aspects of the operation of system 100. Memory units 140 and / or 150 may include various databases and image processing software. Memory units 140 and / or 150 may include random access memory, read-only memory, flash memory, a disk drive, optical storage, tape storage, removable storage, and / or any other suitable type of storage. In some examples, memory units 140 and / or 150 are separate from application processor 180 and / or image processor 190. In other embodiments, memory units 140 and / or 150 may be integrated into application processor 180 and / or image processor 190.

[0138] In some embodiments, system 100 may include a location sensor 130. Location sensor 130 may include any suitable type of device configured to determine a location associated with at least one component of system 100. In some embodiments, location sensor 130 may include a global navigation satellite system (GNSS) receiver, such as, for example, a global positioning system (GPS) receiver. Such a receiver can determine the user's location and velocity by processing signals broadcast by GNSS satellites. Location information from location sensor 130 may be made available to application processor 180 and / or image processor 190.

[0139] In some embodiments, system 100 may be operatively connected to various systems, devices, and / or units on a vehicle in which system 100 is installed. The various components of system 100 may communicate with each other and / or with various systems of the vehicle via any appropriate number and / or type of interfaces (e.g., a communication bus). Examples of vehicle systems with which system 100 may cooperate include a throttle system, a braking system, a steering system, and the like.

[0140] In some embodiments, system 100 may include a user interface 170. User interface 170 may be implemented as any suitable type of device for providing information to one or more users and / or for receiving input from one or more users of system 100. User interface 170 may be implemented, for example, as a touch screen, a microphone, a keyboard, pointer device(s), a track wheel, a camera, knobs, buttons, etc. Information may be provided by system 100 to one or more users of system 100 via presentation through user interface 170.

[0141] In some embodiments, system 100 may include a map database 160. Map database 160 may be implemented as any suitable type of database for storing digital map data. In some examples, map database 160 may include data related to the locations of various items in a reference coordinate system, including roads, water features, geographic features, points of interest, and the like. Map database 160 may store not only the locations of such items, but also descriptors associated with those items, including, for example, names associated with each of the stored features and other information related to them. For example, the database may include the locations and types of known obstacles, information related to the topography of the road, or the slope at certain points along the road. In some embodiments, map database 160 may be physically located with the other components of system 100. Alternatively or additionally, map database 160 or portions thereof may be remotely located relative to the other components of system 100 (e.g., remote from processing unit 110). In such embodiments, information from map database 160 may be downloaded from a network via any suitable type of wired and / or wireless data connection and in accordance with any suitable number and / or type of communication protocols (e.g., via a cellular network and / or the Internet, etc.).

[0142] Image capture devices 122, 124, and 126 may each be implemented as any suitable type of device configured to capture at least one image from an environment. Furthermore, any suitable number of image capture devices 122, 124, and 126 may be implemented by system 100 to acquire images, which may then be input to image processor 190. Some embodiments of the presently disclosed subject matter may be implemented using only a single image capture device, while other embodiments may be implemented using two, three, or even four or more image capture devices. Figures 2B-2E Image capture devices 122, 124, and 126 are further described.

[0143] System 100 may implement or operate in conjunction with any suitable number and / or type of sensors, including, for example, acoustic sensors, RF sensors (e.g., radar transceivers), LIDAR sensors, etc. Such sensors may be used independently of or in conjunction with image acquisition unit 120. For example, data from a radar system (not shown) may be used to validate processed information received from processing images acquired via image acquisition unit 120, e.g., to filter out certain false positives resulting from processing images acquired by image acquisition unit 120. Alternatively, data from a radar system (not shown) may be combined with or otherwise supplement image data from image acquisition unit 120, or some processed variation or derivative of the image data from image acquisition unit 120.

[0144] The system 100 or its various components can be incorporated into any suitable number and / or type of different platforms. In some embodiments, the system 100 can be implemented as an integral part of a vehicle 200, such as Figure 2A For example, vehicle 200 may be equipped with processing unit 110 and any of the other components of system 100, as described above with respect to Figure 1 Although in some embodiments, the vehicle 200 may be equipped with only a single image capture device (e.g., a camera), in some embodiments, the vehicle 200 may be equipped with only a single image capture device (e.g., a camera). Figures 2B-2E In other embodiments of the above embodiment, multiple image capture devices may be implemented. For example, Figure 2A As shown, either of the image capture devices 122 and 124 of vehicle 200 may be part of an ADAS (Advanced Driver Assistance Systems) imaging suite.

[0145] The image capture device included on the vehicle 200 as part of the image acquisition unit 120 may be positioned at any suitable location. Figures 2A-2E and Figure 3 As shown, image capture device 122 can be located near a rearview mirror. This location can provide a similar line of sight to the driver of vehicle 200, which can help determine what is and is not visible to the driver.

[0146] Other locations for the image capture devices of image capture unit 120 may also be used. For example, image capture device 124 may be located on or in the bumper of vehicle 200. This location can be particularly advantageous for image capture devices with a wide field of view. The line of sight of a bumper-positioned image capture device may be different from the driver's line of sight. Image capture devices (e.g., image capture devices 122, 124, and 126) may also be located in other locations. For example, the image capture device may be located on or in one or both of the side mirrors of vehicle 200, on the roof of vehicle 200, on the hood of vehicle 200, on the trunk of vehicle 200, on the side of vehicle 200, mounted on, positioned behind, or positioned in front of any of the windows of vehicle 200, mounted in or near light images on the front and / or rear of vehicle 200, etc. Image capture unit 120, or an image capture device that is one of multiple image capture devices used in image capture unit 120, may have a field of view (FOV) that is different from the driver of the vehicle and may not necessarily see the same objects. In one example, the FOV of image acquisition unit 120 may extend beyond the FOV of a typical driver and, therefore, may image objects outside the driver's FOV. In yet another example, the FOV of image acquisition unit 120 is a portion of the driver's FOV. In some embodiments, the FOV of image acquisition unit 120 corresponds to a sector that covers an area of ​​the road ahead of the vehicle and, possibly, also the surroundings of the road.

[0147] In addition to the image capture device, vehicle 200 may include any of the components of system 100, but for the sake of brevity, not every component of system 100 is shown. For example, processing unit 110 may be included on vehicle 200, integrated with the vehicle's engine control unit (ECU), or separate. Vehicle 200 may also be equipped with a position sensor 130 (e.g., a GNSS receiver), and may also include a map database 160 and memory units 140 and 150.

[0148] Figure 2A An exemplary representation of a vehicle including a system in accordance with one or more embodiments of the present disclosure is shown. Figure 2B Showing one or more embodiments according to the present disclosure, Figure 2A An exemplary representation of the vehicle and systems shown. Figure 2B As shown, the disclosed example may include a vehicle 200 including a system 100 in a vehicle body having a first image capture device 122 positioned near a rearview mirror and / or near a driver of the vehicle 200, a second image capture device 124 positioned on or in a bumper area (e.g., one of the bumper areas 210) of the vehicle 200, and a processing unit 110.

[0149] like Figure 2C As shown, both image capture devices 122 and 124 may be positioned near a rearview mirror and / or near the driver of vehicle 200. Figure 2B and Figure 2C Two image capture devices 122 and 124 are shown in FIG, but it should be understood that other embodiments may include more than two image capture devices. Figure 2D In the illustrated embodiment, first, second, and third image capture devices 122 , 124 , and 126 are included in the system 100 of a vehicle 200 .

[0150] like Figure 2D As shown, image capture devices 122, 124, and 126 may be positioned near rearview mirrors and / or near the driver's seat of vehicle 200. The disclosed examples are not limited to any particular number and configuration of image capture devices, and the image capture devices may be positioned at any suitable location within and / or on vehicle 200.

[0151] It is also understood that the disclosed embodiments are not limited to a particular type of vehicle 200 and may be applicable to all types of vehicles, including automobiles, trucks, trailers, motorcycles, bicycles, self-balancing transporters, and other appropriate types of vehicles.

[0152] First image capture device 122 may include any suitable type of image capture device. Image capture device 122 may include an optical axis. In one example, image capture device 122 may include an Aptina M9V024 wide video graphics array (WVGA) sensor with a global shutter. In another example, a rolling shutter may be implemented. Image acquisition unit 120 and any image capture devices implemented as part of image acquisition unit 120 may have any suitable image resolution. For example, image capture device 122 may provide a resolution of 1280×960 pixels and may include a rolling shutter.

[0153] Image acquisition unit 120 and any image capture device implemented as part of image acquisition unit 120 may include various optical elements. In some embodiments, one or more lenses may be included, for example, to provide a desired focal length and field of view for image acquisition unit 120 and any image capture device implemented as part of image acquisition unit 120. In some examples, an image capture device implemented as part of image acquisition unit 120 may include or be associated with any optical element, such as, for example, a 6 mm lens or a 12 mm lens. In some examples, image capture device 122 may be configured to capture images with a desired (and predetermined) field of view (FOV).

[0154] The first image capture device 122 may have a scan rate associated with the acquisition of each of the first series of image scan lines. The scan rate may represent the rate at which the image sensor is able to acquire image data associated with each pixel included in a particular scan line.

[0155] Figure 2E An exemplary representation of a vehicle control system according to one or more embodiments of the present disclosure is shown. Figure 2E As shown, vehicle 200 may include a throttle system 220, a brake system 230, and a steering system 240. System 100 may provide input (e.g., control signals) to one or more of throttle system 220, brake system 230, and / or steering system 240 via one or more data links (e.g., one or more wired and / or wireless links for transmitting data). For example, based on analysis of images captured by image capture devices 122, 124, and / or 126, system 100 may provide control signals to one or more of throttle system 220, brake system 230, and / or steering system 240 to navigate vehicle 200 (e.g., by inducing acceleration, turning, lane deviation, etc.). In addition, system 100 may receive input from one or more of throttle system 220, brake system 230, and / or steering system 240 indicating operating conditions of vehicle 200 (e.g., speed, whether vehicle 200 is braking and / or turning, etc.).

[0156] Figure 3An exemplary representation of a vehicle interior including a rearview mirror and a user interface for a vehicle imaging system is shown in accordance with one or more embodiments of the present disclosure. Figure 3 As shown, vehicle 200 may also include a user interface 170 for interacting with the driver or passengers of vehicle 200. For example, user interface 170 in a vehicle application may include a touch screen 320, a knob 330, buttons 340, and a microphone 350. The driver or passengers of vehicle 200 may also interact with system 100 using handles (e.g., located on or near the steering column of vehicle 200, including, for example, a turn signal handle), buttons (e.g., located on the steering wheel of vehicle 200), and the like. In some embodiments, microphone 350 may be positioned adjacent to rearview mirror 310. Similarly, in some embodiments, image capture device 122 may be located near rearview mirror 310. In some embodiments, user interface 170 may also include one or more speakers 360 (e.g., speakers of a vehicle audio system). For example, system 100 may provide various notifications (e.g., warnings) via speakers 360.

[0157] Many variations and / or modifications may be made to the embodiments disclosed above. For example, not all components are essential to the operation of system 100. Furthermore, any component may be located in any appropriate portion of system 100, and the components may be rearranged in a variety of configurations while providing the functionality of the disclosed embodiments. Therefore, the configurations described above are examples, and regardless of the configurations described above, system 100 may provide a wide range of functionality for analyzing the surrounding environment of vehicle 200 and navigating and / or otherwise controlling and / or operating vehicle 200 in response to this analysis. Navigation, control, and / or operation of vehicle 200 may include enabling and / or disabling (directly or via an intermediate controller, such as the controller described above) various features, components, devices, modes, systems, and / or subsystems associated with vehicle 200. Alternatively, or in addition, navigation, control, and / or operation may include interacting with a user, driver, passengers, pedestrians, and / or other vehicles or users that may be located inside or outside vehicle 200, for example, by providing visual, audio, tactile, and / or other sensory alerts and / or indications.

[0158] As discussed in more detail below and in accordance with various disclosed embodiments, system 100 can provide a variety of features related to autonomous driving, semi-autonomous driving, and / or driver assistance technologies. For example, system 100 can analyze image data, location data (e.g., GNSS location information), map data, speed data, and / or data from sensors included in vehicle 200. System 100 can collect data for analysis from, for example, image acquisition unit 120, location sensor 130, and / or other sensors. Furthermore, system 100 can analyze the collected data to determine whether vehicle 200 should take a certain action and then automatically take the determined action without human intervention. It will be appreciated that in some cases, the actions automatically taken by vehicle 200 are under human supervision, and that the ability for a human to intervene, adjust, abort, or override the machine's actions is enabled in some cases or at all times. For example, when vehicle 200 is navigating without human intervention, system 100 can automatically control the braking, acceleration, and / or steering of vehicle 200 (e.g., by sending control signals to one or more of throttle system 220, braking system 230, and / or steering system 240). In addition, the system 100 can analyze the collected data and issue warnings, instructions, recommendations, alerts, or instructions to the driver, passengers, users, or others inside or outside the vehicle (or to other vehicles) based on the analysis of the collected data. Additional details regarding various embodiments implemented via the system 100 are provided below.

[0159] B. Additional Prevention of Overwriting of Shared Memory Segments

[0160] Figure 4A 1 shows an example of an apparatus component according to one or more embodiments of the present disclosure. Figure 4A The device 400 shown includes various components, which may be implemented as a SoC, as part of an integrated circuit (IC), as components distributed across several SoCs or ICs, etc. For example, a processing unit (such as the processing unit 110 described above in Section I) may be used to identify the device 400. The various components of the device 400 described herein may be implemented according to the architecture and application of the device 400. As an example, if the device 400 forms the entirety or a portion of a SoC, then the device 400 described herein may be implemented as a separate component. Figure 4A The various components shown may be implemented as functional units (eg, functional components) of a SoC.

[0161] Processing entities (e.g., processors and processing units, such as the first, second, third, and fourth processors 410, 420, 412, 422 and the first and second processing units 450, 452) can be implemented as any suitable number and / or type of processors, processing circuits, hardware, software, or a combination thereof. For example, a processing entity can be implemented as a processor core, such as a microcontroller, a microprocessor (μP), a digital signal processor (DSP), an application-specific instruction set processor (ASIP) core, or the like. As another example, one or more of the processing entities can be implemented as a hardware accelerator, which can include, for example, an image processor, a neural network processor, or any other suitable type of hardware accelerator. For ease of description, processing entities (e.g., processors and processing units, such as the first, second, third, and fourth processors 410, 420, 412, 422 and the first and second processing units 450, 452) can be different types of processors, the same type of processors, or shared components that constitute the same processing entity. Different terms "processor" and "processing unit" have been introduced to clarify that processors 410, 420, 412 and 422 use corresponding coherence structures to communicate, while processing units 450, 452, etc. do not need to communicate via the coherence structures described herein, but can read and / or write data directly to their corresponding shared memories 440, 442.

[0162] The first, second, and third shared memories 440, 442, 470 may be implemented as any suitable type of memory that is shared (i.e., read from and written to) among the various processing entities of the device 400 as described herein. For example, the first, second, and third shared memories 440, 442, 470 may be implemented as semiconductor memory blocks, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM (EEPROM) memory, flash memory, etc.

[0163] Device 400 Figure 4A 4. The apparatus 400 is shown as implementing two processing unit "clusters" by way of example and not limitation. The apparatus 400 may implement any appropriate number of processing unit clusters depending on the particular implementation and application. In embodiments, the architecture of the apparatus 400 and the use of processing unit clusters as described herein may simplify maintaining consistency. Consistency in this context refers to a particular concern when multiple processors share memory and may periodically read from and write to the same location in the shared memory. Thus, data consistency refers to the value currently stored at a particular shared memory address location being the last value written to that shared memory address location by any of the processors that are able to read from and write data to the shared memory.

[0164] The embodiments described herein address issues related to data consistency regarding the use of shared memory by multiple processing entities. To this end, the embodiments described herein introduce a hierarchical structure in which each processing unit cluster maintains its respective data consistency, and additional measures are taken to maintain data consistency between processing unit clusters. This simplifies maintaining data consistency, particularly when there are many processing units accessing the shared memory.

[0165] Continue to refer to Figure 4A , apparatus 400 includes a first processing unit cluster (processing unit cluster 1) including a first processor 410, a second processor 420, a first coherency fabric 430, a first processing unit 450, and a first shared memory 440. The first processing unit cluster may include additional processing entities (e.g., additional processors, processing units, etc.), interconnects, coherency fabrics, shared memories, and / or any suitable number of other components. Figure 4A The arrows shown may represent interconnections between various components and, thus, may be implemented as any appropriate type of wired or wireless links, traces, connections, buses, etc. Various processors, processing units, etc. may read / write data from / to the shared memory as described herein. In embodiments where the apparatus 400 is implemented as a SoC, Figure 4A Arrows between each of the illustrated components may represent inter-module communications between those components.

[0166] The first processor 410 may include a first first-level cache 411, and the second processor 420 may include a second first-level cache 421. The first processor 410 and the second processor 420 operate within a first cache coherence domain. The first and second first-level caches 411, 421 may represent any suitable type and / or size of memory configured as a cache memory.

[0167] The first processing unit cluster also implements a first coherence fabric 430 that is located between (a) the first processor 410 and the second processor 420 and (b) the first shared memory 440. Thus, the first coherence fabric 430 may be configured to function as any suitable type of interconnect fabric that facilitates writing and reading data to and from the shared memory 440 by the first processor 410 and the second processor 420. That is, the first coherence fabric 430 may function as an interconnect to transfer data to and from the first and second processors 410, 420 and the first shared memory 440, as discussed further herein. Thus, the first coherence fabric 430 may be implemented as any suitable type of interconnect fabric based on the particular architecture and implementation of the device 400. As an example, if the device 400 forms all or part of a SoC, the first coherence fabric 430 may be implemented as an on-chip interconnect fabric.

[0168] The first processor 410 and the second processor 420 can each communicate with each other via the use of the first coherence structure 430 using any suitable type of hardware cache coherence protocol. In an embodiment, the first processor 410 and the second processor 420 can each communicate with each other using an enhanced hardware cache coherence protocol. The enhanced hardware cache coherence protocol can be implemented as a hardware cache coherence protocol that is enhanced to maintain dirty bit information (e.g., maintain or save information embedded in the dirty bit) during the exchange of data units within the first cache coherence domain. When a particular processing entity writes (i.e., modifies) the contents of a memory (e.g., caches 411, 421, 413, and 423, shared memories 440 and 442, etc.), the dirty bit as described herein is understood to be set. Therefore, the dirty bit indicates that its associated memory block has been modified and has not yet been saved to an appropriate storage device (e.g., the first shared memory 440, the second shared memory 442, etc.).

[0169] Memory sharing between the two processors again involves assigning different shared memory line segments to different processors so that the different processors can modify their assigned shared memory line segments without overwriting other shared memory line segments assigned to other processors. This is typically achieved through the use of a "dirty bit," which is an integral part of various communication protocols as described herein. The dirty bit is used to indicate which bits are changed for a particular data unit, and also indicates which shared memory line segments can and cannot be written to by a particular processing entity (e.g., the first, second, third, and fourth processors 410, 420, 412, 422), as discussed further herein. Accordingly, an enhanced hardware cache coherence protocol is used to maintain dirty bit information when transferring data units within the first cache coherence domain (e.g., reading data units transferred from the first shared memory 440 to the first first-level cache 411 or the second first-level cache 421).

[0170] The first processing unit 450, the first coherence structure 430, and the first shared memory 440 may communicate with each other using another communication protocol (i.e., an "other" communication protocol as described herein) that is different from the enhanced hardware cache coherence protocol. In particular, the other communication protocol used to implement communication between the first processing unit 450, the first shared memory 440, and the first coherence structure 430 may not support hardware coherence but still maintain dirty bit information. Therefore, the first and second processors 410, 420 may communicate with each other via the first coherence structure 430 using the enhanced hardware cache coherence protocol (i.e., the first communication protocol), and the first and second processors 410, 420 may read / write data units from / to the first shared memory 440 via communication with the first coherence structure 430, which implements another protocol (i.e., the second communication protocol) for this purpose.

[0171] In an embodiment, another protocol may be implemented as an Advanced Extensible Interface (AXI) protocol, and the enhanced hardware consistency protocol may be implemented as an Enhanced AXI Consistency Extension (ACE) protocol. The ACE protocol may support various enhanced consistency commands, such as:

[0172] ReadShared—Requests a read of any cache line in the dirty / shared state (requests the master processing entity typically does not have).

[0173] ReadUnique—Request to read a cache line (which the requesting master typically does not have) that is in unique state (ie, another master does not have a copy of). This is typically the case because the master is expected to write to the cache line.

[0174] CleanUnique—Requests that a cache line (the requesting master processing entity typically already has the cache line in the shared state) be changed to the unique state. This is typically performed because the master processing entity anticipates writing to the cache line.

[0175] Note that the commands described above are examples of those of the example protocol provided and are not dependent upon the specific system shown in the figures.

[0176] The second processing unit cluster (processing unit cluster 2) includes a third processor 412, a fourth processor 422, a second coherence fabric 432, a second processing unit 452, and a second shared memory 442. As described with respect to the first processing unit cluster, the second processing unit cluster may also include additional processing entities (e.g., additional processors, processing units, etc.), interconnects, coherence fabrics, shared memories, and / or any suitable number of other components. The third processor 412, fourth processor 422, second coherence fabric 432, second processing unit 452, and second shared memory 442 included in the second processing unit cluster may operate in a substantially similar or identical manner and may be implemented as the same types of components as the first processor 410, second processor 420, first coherence fabric 430, first processing unit 450, and first shared memory 440, respectively, of the first processing unit cluster described above. Accordingly, for the sake of brevity, further details regarding the components of the second processing unit cluster are not provided herein.

[0177] The third processor 412 may include a third first-level cache 413. The fourth processor 422 may include a fourth first-level cache 423. The third processor 412 and the fourth processor 422 are configured to operate within a second cache coherence domain. A second coherence structure 432 is located between (a) the third processor 412 and the fourth processor 422 and (b) the second shared memory 442. The third and fourth first-level caches 411, 413, 423 may represent any suitable type and / or size of memory configured as a cache memory.

[0178] The third processor 412 and the fourth processor 422 may each communicate with each other using any suitable type of hardware cache coherence protocol via use of the second coherence structure 432. In an embodiment, the third processor 412 and the fourth processor 422 may each communicate with the second coherence structure 432 and the second shared memory 442 using an enhanced hardware cache coherence protocol. The enhanced hardware cache coherence protocol may be implemented as a hardware cache coherence protocol that is enhanced to maintain dirty bit information during exchanges of data units within the second cache coherence domain.

[0179] The second processing unit 452, the second coherence structure 432, and the second shared memory 442 can communicate with each other using the second communication protocol as described above for the first processing unit cluster. Thus, the third and fourth processors 412, 422 can communicate with each other via the second coherence structure 432 using the enhanced hardware cache coherence protocol (i.e., the first communication protocol), and the third and fourth processors 412, 422 can read / write data units from / to the second shared memory 442 via communication with the second coherence structure 432, which implements another protocol (i.e., the second communication protocol) for this purpose.

[0180] like Figure 4A As shown, the first shared memory 440 and the second shared memory 442 are each coupled to a third coherence structure 460, which is further coupled to a third shared memory 470. The first, second, and third shared memories 440, 442, 470 may be any suitable type of memory, such as a cache memory or a non-cache memory. Although shown as separate shared memories in the figures, this is for ease of illustration, and any combination of the first, second, and third shared memories 440, 442, 470 may form part of the same shared memory unit.

[0181] Figure 4B One or more embodiments of the present disclosure are shown. Figure 4A An example process flow of the device components shown. Specifically, Figure 4B Show about Figure 4A Additional details of the operation of the first processing unit cluster are shown.

[0182] In such Figure 4B In the illustrated process flow 450, it is assumed that the dirty bit configuration is such that the first and second processors 410, 421 can update a first shared memory line segment 490.1 of a shared memory line 490, but are not permitted to update a second shared memory line segment 490.2 of the same shared memory line 490. A shared memory line 490 can have any suitable size, which can correspond to a particular address range within the first shared memory 440. For example, a shared memory line 490 can represent two or more bytes of storage (e.g., 32 bytes, 64 bytes, etc.). A shared memory line 490 can represent a range of addresses associated with any suitable number of shared memories (the first shared memory 440 in this example) and is shown in detail for the sake of brevity, although the embodiments described herein are applicable to any suitable number of shared memory lines within the first shared memory 440. Of course, the size of a shared memory line 490, as well as the size of the first shared memory 440, can vary depending on how the first shared memory 440 is formatted, the particular application, the required memory specifications, etc.

[0183] Shared memory line 490 may be from any suitable number of shared memory lines identified using first shared memory 440, and the size of one or more of these shared memory lines and / or shared memory line segments (including shared memory line 490 and / or shared memory line segment 490.1) may be proportionally related to the size of the data unit as described herein. As an example, as for Figures 4A-4B The data unit can be a fraction of the size of any shared memory line and / or shared memory line segment of first shared memory 440 (e.g., shared memory line 490 and / or shared memory line segment 490.1) or some smaller ratio (e.g., 1 / 64, 1 / 32, 1 / 16, 1 / 8, 1 / 4, etc.). This can also be the case for any suitable number of processing unit clusters as described herein. For example, a data unit of a second processing unit cluster can also be a fraction of shared memory line 490 and / or shared memory line segment 490.2. Additionally or alternatively, a data unit of any of the processing unit clusters of apparatus 400 as described herein can also be a fraction of a shared memory line and / or shared memory line segment identified using second shared memory 442 and any other suitable shared memory.

[0184] In an embodiment, the first shared memory line segment 490.1 may be assigned to a first processing unit cluster, and the second shared memory line segment 490.2 may be assigned to a second processing unit cluster, such as Figure 4A As shown. The allocation of first and second shared memory line segments 490.1, 490.2 can be represented by a specific address range identified by a shared memory line 490 that is assigned to the first and second processing unit clusters and identified via the use of dirty bit information as described herein. Thus, the allocation of first and second shared memory line segments 490.1, 490.2 can be fixed or dynamically changed / updated based on the size (e.g., address range) and / or to which of the first and second processing unit clusters the first and second segments 490.1, 490.2 are assigned. Furthermore, the first and second processing unit clusters can be assigned shared memory line segments 490.1, 490.2 of the same or different sizes. The manner in which each of the shared memory line segments of the first shared memory 440 is allocated between the first and second processing unit clusters in this manner can also vary between each of the shared memory lines (e.g., the size of the corresponding shared memory line segment of each shared memory line can vary or remain the same for each of the shared memory lines identified by the first shared memory 440).

[0185] In an embodiment, the first processor 410 may retrieve a previous version of a data unit, DU(n-1) 480, from the first shared memory 440 (or from any other shared memory, including the third shared memory 470). Data unit 480 may be retrieved from the first shared memory line segment 490.1 of the shared memory line 490, as described above. The first processor 410 may then store the data unit 480 retrieved in this manner in the first first-level cache 411. The first processor 410 may then modify the previous version of data unit 480 to provide an updated data unit DU(n) 482. Data units 480, 482 are each smaller than the total size of the shared memory line 490. A dirty bit 488 indicating the modification of data unit 480 to generate updated data unit 482 is generated due to the implementation of the enhanced hardware cache coherence protocol used by the first processor 410, the second processor 420, and the first coherence structure 430, as described herein. Therefore, dirty bit 488 indicates that data unit 480 has been updated / corrected to data unit 482.

[0186] Continuing with this illustrative example, the second processor 420 may then request (eg, via the first coherency structure 430 ) the data unit 482 before the data unit 482 is written to the shared memory 440 (or to any other shared memory—including the third shared memory 470 ).

[0187] In response to this request, the first processor 410 may then transmit (e.g., using an enhanced hardware cache coherence protocol) the updated data unit 482 and the dirty bit 488, which indicates that the data unit 482 was previously updated / corrected. Continuing with this example, the second processor 420 may then modify the data unit 482 to provide another updated / corrected data unit DU(n+1) 483 and update the corresponding dirty bit 488 to reflect this correction. This may be accomplished, for example, by the second processor 420 storing the data unit 482 in the second first-level cache 421 and then performing one or more processing operations that update or correct the value of the data unit 482 to generate the data unit 483.

[0188] The second processor 420 may then write the newly updated data unit 483 to the first shared memory 440 via the first coherence structure 130 as described herein. In particular, the second processor 420 may communicate the data unit 483 to the first coherence structure 430 using a first communication protocol, and the first coherence structure 430 may, in turn, communicate (i.e., write) the updated data unit 483 to the first shared memory line segment 490.1 of the shared memory line 490 using a second communication protocol without overwriting the data in the second shared memory line segment 490.2, wherein the second communication protocol maintains dirty bit information (but does not support hardware coherence). In this way, the most recently updated data unit 483 is written to the first shared memory line segment 490.1 of the shared memory line 490 without modifying the data stored in the second shared memory line segment 490.2. Thus, due to the allocation of the shared memory line 490 as described herein, the first and second processors 410 , 420 are allowed to update only the first shared memory line segment 490 . 1 of the shared memory line 490 , but not the second shared memory line segment 490 . 2 of the shared memory line 490 .

[0189] In addition, embodiments include a resolution of the dirty bit 488 that is finer than the total size of the data units 480, 482, 483. Thus, modification of any appropriate portion of a data unit may be indicated via the dirty bit information. For example, each byte or another appropriate portion of a data unit 480, 482, 483 may be two or more bits long, and each bit identified with each byte or portion of a data unit (as the case may be) may be assigned to any appropriate number of dirty bits from the dirty bit 488 according to a predetermined scheme or protocol. Thus, the dirty bit 488 may include multiple bits assigned to a single data unit. Thus, as described herein, any reference to modifying (i.e., correcting or updating) a data unit may include modification of the data unit in its entirety or, alternatively, modification of any portion thereof (e.g., any number of bits, bytes, or portions thereof), as the case may be.

[0190] It should be noted that applying a hardware cache coherence protocol without the enhanced protocol may result in the loss of dirty bit information. Thus, in this case, the second processor 420 may overwrite the entire shared memory line 490 when writing to the first shared memory 440. This overwrite may delete the contents of other segments written to the shared memory line 490. Thus, the use of the enhanced hardware cache coherence protocol by the first and second processors 410, 420 to communicate with each other and the use of another communication protocol to write data units to the first shared memory via the first coherence structure 430 (which also maintains dirty bit information) ensures that the dirty bit information is preserved and also ensures that the contents of the memory stored in the second shared memory line segment 490.2 are not modified as part of this process.

[0191] Figure 5B An example process flow according to one or more embodiments of the present disclosure is shown. Figure 5B , process 550 may be a computer-implemented method performed by and / or otherwise associated with one or more processors (processing circuits) and / or storage devices. These processors and / or storage devices may be associated with one or more computing components identified using any suitable means (e.g., a SoC, an IC, a processing unit 110, various processing entities identified using means 400 as described herein, etc.).

[0192] The processor as described herein may execute instructions stored on other computer-readable storage media (e.g., memory 140, 150) or alternatively stored on a memory not shown in the figures (the instructions may be locally stored instructions and / or as part of the processing circuit itself). Process 550 may include instructions stored in the following manner for the sake of brevity: Figure 5B Alternative or additional steps not shown in the Figure 5B The steps shown are performed in different orders.

[0193] Process flow 550 may include: Figure 5B The preliminary stage 560 shown. The preliminary stage 560 may include retrieving (block 560A) a previous version of the data unit from the shared memory. This may include, for example, the first processor 410 retrieving the data unit 480 from the first shared memory line segment 490.1 of the shared memory line 490 identified using the first shared memory 440, as described above with respect to Figure 4B As stated.

[0194] The process flow 550 may further include, as part of the preliminary stage 560, modifying (block 560B) the previous version of the data unit to provide an updated data unit. This may include, for example, the first processor 410 modifying the data unit 480 to provide the updated data unit 482, as described above with reference to Figure 4B Shown and described.

[0195] The process flow 550 may further include generating (block 560C) a request to retrieve a data unit as part of the preliminary phase 560. This may include, for example, the steps described above with reference to Figure 4B The request for the data unit 482 is generated via the second processor 420. This request may be performed before the data unit 482 is written to the shared memory 440 (or to any other shared memory - including the third shared memory 470).

[0196] The process flow 550 may further include transferring the data unit from the first processor to the second processor using an enhanced hardware cache coherence protocol (block 570). The enhanced hardware cache coherence protocol may refer to a hardware cache coherence protocol that is enhanced to maintain dirty bit information during an exchange of data units within a cache coherence domain including the first and second processors. This may include, for example, the first processor 410 transferring the data unit 482 to the second processor 420, as referred to herein. Figure 4B The data transfer (block 570) of the data unit 482 may be performed before the first processor 410 sends (ie, transmits) the data unit 482 to the first shared memory 440 via the first coherence structure 430, as described above with reference to FIG. Figure 4B As stated.

[0197] The process flow 550 may further include writing (block 580) the data unit to a first shared memory line segment of a shared memory line of the shared memory using another or second communication protocol. The second communication protocol again implements the maintenance of dirty bit information as described herein, but does not support hardware consistency. This may include, for example, the second processor 420 as described herein with reference to Figure 4B The updated data unit 483 is written to the first shared memory 440 via the first coherency structure 430. Therefore, and because the dirty bit is maintained via the use of the second communication protocol, the updated data unit 483 can be written to the first shared memory line segment 490.1 without overwriting the data contained in the second shared memory line segment 490.2 of the shared memory line 490, as described above with reference to Figure 4B In other words, the transmission of the updated data unit (block 570) may be implemented as the second processor 420 transmitting the updated data unit to the first coherence structure 430, and the updated data unit may then be transmitted from the first coherence structure 430 to a particular segment of the shared memory line (segment 490.1 in this example).

[0198] The first shared memory 440 may again be shared between the first and second processing unit clusters, as described above and Figure 4A As shown. Different segments of the shared memory line can be assigned to different processing entities of the processing unit cluster. Thus, the embodiment includes process flow 550 further comprising writing (block 590) another data unit to another segment of the shared memory line. This process (block 590) can be performed in a manner similar to the process described herein for processing unit cluster 1, but for example, performed by processing unit cluster 2.

[0199] For example, this may be done by a processing entity external to the first cache domain (eg, using a cache memory as described herein with reference to Figure 4A550). The additional data units may be written (block 580) to any other allocated segment of a shared memory line of the first shared memory 440 in parallel with any of the other processes described with respect to the process flow 550.

[0200] As an illustrative example, the process flow 550 may include (a) transferring the second data unit from the third processor 412 to the fourth processor 422 using the enhanced hardware cache coherence protocol, and (b) writing the second data unit to the second segment 490.2 of the shared memory line 490 of the second shared memory 442 using another protocol without overwriting another segment of the shared line, as described above for Figure 4B As stated.

[0201] It is also noted that although the various processes described with respect to process flow 550 are described with respect to specific processors, processing units, or components, process flow 550 may be performed by additional or alternative processing entities or other suitable components. For example, process flow 550 may be performed in parallel or independently of one another for any suitable number of multiple processing unit clusters.

[0202] Example

[0203] The following examples cover other aspects

[0204] An example (e.g., Example 1) is a method for preventing overwriting of a shared line segment of a shared memory, the method comprising: sending a data unit from a first processor to a second processor using a first protocol including an enhanced hardware cache consistency protocol, the enhanced hardware cache consistency protocol maintaining dirty bit information during the exchange of data units within a cache consistency domain, and the size of the data unit is a small fraction of the size of the shared line segment of the shared memory; and writing the data unit to the shared line segment of the shared memory using a second protocol different from the enhanced hardware cache consistency protocol without overwriting another shared line segment of the shared line, the write being based at least in part on the dirty bit information, and wherein the second protocol does not support hardware consistency and maintains the dirty bit information.

[0205] Another example (eg, Example 2) relates to the previously described example (eg, Example 1), further comprising: writing, via a processing entity outside the cache coherence domain, an additional data unit to another shared line segment of the shared line.

[0206] Another example (eg, Example 3) relates to a previously described example (eg, one or more of Examples 1-2), wherein the processing entity is a hardware accelerator.

[0207] Another example (e.g., Example 4) relates to the previously described examples (e.g., one or more of Examples 1-3), wherein the second protocol includes an Advanced Extensible Interface (AXI) protocol, and wherein the first protocol includes an enhanced hardware consistency protocol that is an AXI Consistency Extension (ACE) protocol.

[0208] Another example (eg, Example 5) relates to a previously described example (eg, one or more of Examples 1-4), wherein writing includes: sending the data unit to a first consistency structure; and sending the data unit from the first consistency structure to a shared line segment of a shared line.

[0209] Another example (e.g., Example 6) relates to the previously described examples (e.g., one or more of Examples 1-5), wherein sending a data unit from a first processor to a second processor is preceded by: retrieving a previous version of the data unit from a shared memory by the first processor; modifying the previous version of the data unit by the first processor to provide the data unit; and generating a request to retrieve the data unit by the second processor.

[0210] Another example (eg, Example 7) relates to a previously described example (eg, one or more of Examples 1-6), wherein the shared memory is a shared cache memory.

[0211] Another example (eg, Example 8) relates to a previously described example (eg, one or more of Examples 1-7), wherein sending the data unit from the first processor to the second processor occurs before the first processor sends the data unit to the shared memory.

[0212] Another example (e.g., Example 9) involves the previously described examples (e.g., one or more of Examples 1-8), further including: sending another data unit from the third processor to the fourth processor using an enhanced hardware cache coherence protocol, the size of the another data unit being a fraction of the size of a shared line segment of another shared memory; and writing the another data unit to a shared line segment of a shared line of another shared memory using a second protocol without overwriting another shared line segment of the shared line of another shared memory, the writing being based at least in part on dirty bit information, wherein the first processor and the second processor belong to a first cluster of processing units, and wherein the third processor and the fourth processor belong to a second cluster of processing units.

[0213] Another example (eg, Example 10) relates to the previously described examples (eg, one or more of Examples 1-9), wherein the first shared memory and the second shared memory are coupled to the further memory via a second coherency structure.

[0214] An example (e.g., Example 11) is a device having overwrite prevention capability for a line segment, the device comprising: a shared memory; a first processor; and a second processor, wherein the first processor is configured to send a data unit to the second processor using a first protocol including an enhanced hardware cache consistency protocol, the enhanced hardware cache consistency protocol maintaining dirty bit information during the exchange of the data unit within a cache consistency domain, the cache consistency domain including the first processor and the second processor, and the size of the data unit is a small fraction of the size of a shared line segment of the shared memory; wherein the device is configured to write the data unit to the shared line segment of the shared memory using a second protocol different from the enhanced hardware cache consistency protocol without overwriting another shared line segment of the shared line, the write being based at least in part on the dirty bit information, and wherein the second protocol does not support hardware consistency and maintains the dirty bit information.

[0215] Another example (eg, Example 12) relates to the previously described example (eg, Example 11), wherein the apparatus is configured to write the additional data unit to another shared line segment of the shared line via a processing entity outside the cache coherence domain.

[0216] Another example (eg, Example 13) relates to a previously described example (eg, one or more of Examples 11-12), wherein the processing entity is a hardware accelerator.

[0217] Another example (e.g., Example 14) relates to the previously described examples (e.g., one or more of Examples 11-13), wherein the second protocol includes an Advanced Extensible Interface (AXI) protocol, and wherein the first protocol includes an enhanced hardware consistency protocol that is an AXI Consistency Extension (ACE) protocol.

[0218] Another example (e.g., Example 15) involves the previously described examples (e.g., one or more of Examples 11-14), wherein the device is configured to write data by sending data units to a first consistency structure, and sending the data units from the first consistency structure to a shared line segment of a shared line.

[0219] Another example (e.g., Example 16) relates to the previously described examples (e.g., one or more of Examples 11-15), wherein the first processor and the second processor are configured to, before sending the data unit from the first processor to the second processor: retrieve a previous version of the data unit from a shared memory by the first processor; modify the previous version of the data unit by the first processor to provide the data unit; and generate a request to retrieve the data unit by the second processor.

[0220] Another example (eg, Example 17) relates to a previously described example (eg, one or more of Examples 11-16), wherein the shared memory is a shared cache memory.

[0221] Another example (eg, Example 18) relates to the previously described examples (eg, one or more of Examples 11-17), wherein the first processor is configured to send the data unit from the first processor to the second processor before the first processor sends the data unit to the shared memory.

[0222] Another example (e.g., Example 19) relates to the previously described examples (e.g., one or more of Examples 11-18), further including: the third processor is configured to: send another data unit to the fourth processor using an enhanced hardware cache coherence protocol, the size of the another data unit being a fraction of the size of a shared line segment of another shared memory; and write the other data unit to a shared line segment of a shared line of another shared memory using a second protocol without overwriting another shared line segment of the shared line, the write being based at least in part on dirty bit information, wherein the first processor and the second processor belong to a first cluster of processing units, and wherein the third processor and the fourth processor belong to a second cluster of processing units.

[0223] Another example (eg, Example 20) relates to the previously described examples (eg, one or more of Examples 11-19), wherein the first shared memory and the second shared memory are coupled to the further memory via a second coherency structure.

[0224] Examples (e.g., Example 21) relate to a non-transitory computer-readable medium associated with an apparatus for preventing overwriting of a shared line segment of a shared memory, the non-transitory computer-readable medium storing instructions that, when executed by one or more processors of the apparatus, cause the apparatus to: send a data unit from a first processor to a second processor using a first protocol including an enhanced hardware cache coherence protocol, the enhanced hardware cache coherence protocol maintaining dirty bit information during an exchange of data units within a cache coherence domain, the size of the data unit being a fraction of the size of a shared line segment of the shared memory; and write the data unit to a shared line segment of the shared memory using a second protocol different from the enhanced hardware cache coherence protocol without overwriting another shared line segment of the shared line, the write being based at least in part on the dirty bit information, and wherein the second protocol does not support hardware coherence and maintains the dirty bit information.

[0225] An example (e.g., Example 22) relates to a method for preventing overwriting of a shared memory line segment of a shared memory, comprising: transmitting a data unit from a first processor to a second processor using a first communication protocol including an enhanced hardware cache consistency protocol, the first processor and the second processor being configured to operate within a cache consistency domain, the enhanced hardware cache consistency protocol maintaining dirty bit information during the exchange of data units within the cache consistency domain; writing the data unit to a first shared memory line segment of the first shared memory based on the dirty bit information using a second communication protocol different from the enhanced hardware cache consistency protocol without overwriting a second shared memory line segment of the first shared memory; wherein the second communication protocol does not support hardware consistency and maintains the dirty bit information.

[0226] Another example (eg, Example 23) relates to the previously described example (eg, Example 22), further comprising: writing, via a processing entity outside the cache coherence domain, an additional data unit to a second shared memory line segment of the first shared memory.

[0227] Another example (eg, Example 24) relates to the previously described examples (eg, one or more of Examples 22-23), wherein the size of the data unit is a fraction of the size of the first shared memory line segment of the first shared memory.

[0228] Another example (e.g., Example 25) relates to the previously described examples (e.g., one or more of Examples 22-24), wherein the first communication protocol includes an AXI Coherence Extension (ACE) protocol, and wherein the second communication protocol includes an Advanced Extensible Interface (AXI) protocol.

[0229] Another example (e.g., Example 26) relates to the previously described examples (e.g., one or more of Examples 22-25), wherein the action of writing a data unit includes: transferring the data unit to a first consistency structure; and transferring the data unit from the first consistency structure to a first shared memory line segment of a first shared memory.

[0230] Another example (e.g., Example 27) relates to the previously described examples (e.g., one or more of Examples 22-26), wherein the action of transferring a data unit from a first processor to a second processor is preceded by: retrieving a previous version of the data unit from a first shared memory by the first processor; modifying the previous version of the data unit by the first processor to provide the data unit; and generating a request to retrieve the data unit by the second processor.

[0231] Another example (eg, Example 28) relates to the previously described examples (eg, one or more of Examples 22-27), wherein the first shared memory is a shared cache memory.

[0232] Another example (eg, Example 29) relates to the previously described examples (eg, one or more of Examples 22-28), wherein the act of transferring the data unit from the first processor to the second processor occurs before the first processor transfers the data unit to the first shared memory.

[0233] Another example (e.g., Example 30) relates to the previously described examples (e.g., one or more of Examples 22-29), further including: transferring additional data units from the third processor to the fourth processor using an enhanced hardware cache coherence protocol; and writing the additional data units to a second shared memory line segment of the first shared memory using a second communication protocol based on dirty bit information without overwriting the first shared memory line segment of the first shared memory, wherein the first processor and the second processor belong to a first processing unit cluster, and wherein the third processor and the fourth processor belong to a second processing unit cluster.

[0234] Another example (eg, Example 31) relates to the previously described examples (eg, one or more of Examples 22-30), wherein the first shared memory is coupled to the further shared memory via a coherency structure.

[0235] An example (e.g., Example 32) relates to an apparatus comprising: a first shared memory; a first processor; and a second processor, wherein the first processor and the second processor are configured to operate within a cache coherence domain, wherein the first processor is configured to transmit a data unit to the second processor using a first protocol including an enhanced hardware cache coherence protocol, the enhanced hardware cache coherence protocol maintaining dirty bit information during the exchange of data units within the cache coherence domain, wherein the apparatus is configured to write the data unit to a first shared memory line segment of the first shared memory using a second protocol different from the enhanced hardware cache coherence protocol based on the dirty bit information without overwriting a second shared memory line segment of the first shared memory, and wherein the second protocol does not support hardware coherence and maintains dirty bit information.

[0236] Another example (eg, Example 33) relates to the previously described example (eg, Example 32), wherein the apparatus is configured to write the additional data unit to a second shared memory line segment of the first shared memory via a processing entity outside the cache coherence domain.

[0237] Another example (eg, Example 34) relates to the previously described examples (eg, one or more of Examples 32-33), wherein the size of the data unit is a fraction of the size of the first shared memory line segment of the first shared memory.

[0238] Another example (e.g., Example 35) relates to the previously described examples (e.g., one or more of Examples 32-34), wherein the first protocol includes an AXI Coherence Extension (ACE) protocol, and wherein the second protocol includes an Advanced Extensible Interface (AXI) protocol.

[0239] Another example (e.g., Example 36) relates to the previously described examples (e.g., one or more of Examples 32-35), wherein the device is configured to write the data unit by: (i) transferring the data unit to a first consistency structure; and (ii) transferring the data unit from the first consistency structure to a first shared memory line segment of a first shared memory.

[0240] Another example (e.g., Example 37) relates to the previously described examples (e.g., one or more of Examples 32-36), wherein the first processor and the second processor are configured to, before transmitting the data unit from the first processor to the second processor: retrieve, by the first processor, a previous version of the data unit from a first shared memory; modify, by the first processor, the previous version of the data unit to provide the data unit; and generate, by the second processor, a request to retrieve the data unit.

[0241] Another example (eg, Example 38) relates to the previously described examples (eg, one or more of Examples 32-37), wherein the first shared memory is a shared cache memory.

[0242] Another example (eg, Example 39) relates to the previously described examples (eg, one or more of Examples 32-38), wherein the first processor is configured to transfer the data unit from the first processor to the second processor before the first processor transfers the data unit to the first shared memory.

[0243] Another example (e.g., Example 40) relates to the previously described examples (e.g., one or more of Examples 32-39), further including: the third processor is configured to: transmit additional data units to the fourth processor using an enhanced hardware cache coherence protocol; and write the additional data units to the second shared memory line segment of the first shared memory without overwriting the first shared memory line segment of the first shared memory, wherein the first processor and the second processor belong to a first processing unit cluster, and wherein the third processor and the fourth processor belong to a second processing unit cluster.

[0244] Another example (eg, Example 41) relates to the previously described examples (eg, one or more of Examples 32-40), wherein the first shared memory is coupled to the further shared memory via a coherency structure.

[0245] Apparatus as shown and described.

[0246] As shown and described.

[0247] in conclusion

[0248] Any of the above-mentioned memories or storage units may be implemented using any known technology, such as volatile or non-volatile memory, including semiconductor-based memory units such as flash memory, EEPROM, EPROM, ROM; ferroelectric digital memory; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, DRAM, SRAM, etc.

[0249] Any reference to any of the terms "comprising," "including," and "may include" may apply to any of "consisting of" and "consisting essentially of." For example, any of the methods describing steps may include more steps than shown in the figures, include only the steps shown in the figures, or include essentially only the steps shown in the figures. The same applies to components of an apparatus, processor, or system, and to instructions stored in a non-transitory computer-readable storage medium.

[0250] The present disclosure may also be implemented by a computer program running on a computer system, the computer program including at least a code portion for executing the steps of the method according to the present disclosure or enabling the programmable device to perform the functions of the apparatus or system according to the present disclosure when executed on a programmable device (e.g., a computer system). The computer program may cause the storage system to allocate disk drives to the disk drive group.

[0251] A computer program is a list of instructions, such as for a specific application and / or an operating system. A computer program may include, for example, one or more of the following: a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared library / dynamically loaded library, and / or other sequence of instructions designed to be executed on a computer system.

[0252] The computer program may be stored internally on a non-transitory computer-readable medium. All or some of the computer program may be permanently provided on a computer-readable medium that is removable or remotely coupled to an information processing system. The computer-readable medium may include, for example and without limitation, any number of the following: magnetic storage media, including magnetic disk and tape storage media; optical storage media, such as compact disk media (e.g., CD ROM, CD R, etc.) and digital video disk storage media; non-volatile memory storage media, including semiconductor-based memory cells, such as flash memory, EEPROM, EPROM, ROM; ferroelectric digital memory; MRAM; volatile storage media, including registers, buffers or caches, main memory, RAM, etc.

[0253] A computer process typically consists of an executing (running) program or portion of a program, current program values ​​and state information, and resources used by the operating system to manage the execution of the process. An operating system (OS) is software that manages the sharing of a computer's resources and provides programmers with an interface for accessing those resources. The operating system processes system data and user input and responds by allocating and managing tasks and internal system resources as services to the system's users and programs.

[0254] A computer system may include, for example, at least one processing unit, associated memory, and a plurality of input / output (I / O) devices. When executing a computer program, the computer system processes information according to the computer program and generates output information via the I / O devices.

[0255] In the foregoing specification, the disclosure has been described with reference to specific examples of embodiments thereof. It will be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the disclosure as set forth in the appended claims.

[0256] Furthermore, the terms "front," "back," "top," "bottom," "above," "below," etc., as used in the description and claims, if any, are used for descriptive purposes and not necessarily to describe permanent relative positions. It is to be understood that any terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in orientations other than those shown or described herein.

[0257] The connections described herein may be any type of connection suitable for transmitting signals from / to respective nodes, units, or devices, for example, via an intermediate device. Accordingly, unless otherwise implied or indicated, the connection may be, for example, a direct connection or an indirect connection. Connections may be shown or described with reference to being a single connection, multiple connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connection. For example, an independent unidirectional connection may be used instead of a bidirectional connection, and vice versa. In addition, a single connection may be used to transmit multiple signals sequentially or in a time-multiplexed manner instead of multiple connections. Similarly, a single connection carrying multiple signals may be separated into various different connections carrying subsets of these signals. Therefore, many options exist for transmitting signals.

[0258] Although specific conductivity types or polarities of potentials have been described in the examples, it will be understood that the conductivity types and polarities of the potentials may be reversed.

[0259] Each of the signals described herein can be designed as either positive or negative logic. In the case of a negative logic signal, the signal is active low, where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high, where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Thus, in alternative embodiments, those signals described as positive logic signals can be implemented as negative logic signals, and those signals described as negative logic signals can be implemented as positive logic signals.

[0260] Furthermore, the terms "assertion" or "setting" and "negation" (or "de-assertion" or "clearing") are used herein when referring to causing a signal, status bit, or the like to enter its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

[0261] Those skilled in the art will appreciate that the boundaries between logic blocks are merely illustrative, and that alternative embodiments may merge logic blocks or circuit elements, or impose alternative decompositions of functionality on various logic blocks or circuit elements. It is therefore understood that the architectures shown herein are merely exemplary, and that in fact many other architectures may be implemented that achieve the same functionality.

[0262] Any arrangement of components that achieve the same functionality is effectively "associated" such that the intended functionality is achieved. Thus, any two components herein combined to achieve a particular functionality can be considered to be "associated" with each other such that the intended functionality is achieved, regardless of architectures or intermediary components. Likewise, any two components so associated can also be considered to be "operatively connected" or "operatively coupled" to each other such that the intended functionality is achieved.

[0263] Furthermore, those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed at least partially overlapping in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may vary in various other embodiments.

[0264] For another example, in one embodiment, the illustrated examples may be implemented as circuits located on a single integrated circuit or within the same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

[0265] As another example, the examples or portions thereof may be implemented as soft or code representations of physical circuitry or may be converted into logical representations of physical circuitry, such as by any appropriate type of hardware description language.

[0266] In addition, the present disclosure is not limited to physical devices or units implemented by non-programmable hardware, but can also be applied to programmable devices or units that can perform the intended device functions by operating according to appropriate program codes, such as mainframe computers, minicomputers, servers, workstations, personal computers, notebooks, personal digital assistants, electronic games, automobiles and other embedded systems, cellular phones and various other wireless devices, generally referred to as "computer systems" in this application.

[0267] However, other modifications, changes, and alternatives are possible.The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0268] In the claims, any reference numerals placed between parentheses should not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in the claim. In addition, the term "a" as used herein is defined as one or more than one. In addition, the use of introductory words such as "at least one" and "one or more" in the claims should not be understood as implying that the introduction of another claim element by the indefinite article "a" will limit any particular claim containing such introduced claim element to embodiments containing only one such element, even when the same claim includes the introductory words "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The fact that certain measures are stated in different claims does not mean that combinations of these measures cannot be used to produce good results.

[0269] While certain features of the disclosure have been illustrated and described herein, numerous modifications, permutations, changes, and equivalents will now occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the disclosure.

Claims

1. A method for preventing overwriting of a shared memory segment of a shared memory, comprising: communicating a data unit from a first processor to a second processor using a first communication protocol including an enhanced hardware cache coherence protocol, the first processor and the second processor being configured to operate within a cache coherence domain, the enhanced hardware cache coherence protocol maintaining dirty bit information during exchanges of the data unit within the cache coherence domain; writing the data unit to a first shared memory line segment of a first shared memory using a second communication protocol different from the enhanced hardware cache coherence protocol based on the dirty bit information without overwriting a second shared memory line segment of the first shared memory; The second communication protocol does not support hardware consistency and maintains the dirty bit information.

2. The method according to claim 1, wherein The size of the data unit is a fraction of the size of the first shared memory line segment of the first shared memory.

3. The method according to claim 1 or 2, wherein The action of writing the data unit includes: transferring the data unit to a first coherence structure; and The data unit is transferred from the first coherency structure to the first shared memory line segment of the first shared memory.

4. The method according to claim 1 or 2, wherein The first communication protocol includes the Advanced Extensible Interface Coherence Extension Protocol, and The second communication protocol includes the Advanced Extensible Interface Protocol.

5. The method according to claim 4, wherein: The act of transferring the data unit from the first processor to the second processor is preceded by: retrieving, by the first processor, a previous version of the data unit from the first shared memory; modifying, by the first processor, the previous version of the data unit to provide the data unit; as well as A request to retrieve the data unit is generated by the second processor.

6. The method according to claim 1 or 2, wherein: The first shared memory is a shared cache memory.

7. The method according to claim 1 or 2, wherein: The act of transferring the data unit from the first processor to the second processor is performed before the first processor transfers the data unit to the first shared memory.

8. The method of claim 1 or 2, further comprising: transferring additional data units from the third processor to the fourth processor using the enhanced hardware cache coherence protocol; as well as writing the additional data unit to the second shared memory line segment of the first shared memory using the second communication protocol based on the dirty bit information without overwriting the first shared memory line segment of the first shared memory, wherein the first processor and the second processor belong to a first processing unit cluster, and The third processor and the fourth processor belong to a second processing unit cluster.

9. The method of claim 8, wherein: The first shared memory is coupled to a further shared memory via a coherency structure.

10. The method of claim 1 or 2, further comprising: A further unit of data is written to the second shared memory line segment of the first shared memory via a processing entity external to the cache coherence domain.

11. A device comprising: a first shared memory; a first processor; as well as Second processor, wherein the first processor and the second processor are configured to operate within a cache coherence domain, wherein the first processor is configured to transmit data units to the second processor using a first protocol including an enhanced hardware cache coherence protocol, the enhanced hardware cache coherence protocol maintaining dirty bit information during exchanges of the data units within the cache coherence domain, wherein the apparatus is configured to write the data unit to a first shared memory line segment of the first shared memory using a second protocol different from the enhanced hardware cache coherence protocol based on the dirty bit information without overwriting a second shared memory line segment of the first shared memory, and The second protocol does not support hardware consistency and maintains the dirty bit information.

12. The device according to claim 11, wherein The size of the data unit is a fraction of the size of the first shared memory line segment of the first shared memory.

13. The device according to claim 11 or 12, wherein: The apparatus is configured to write the data unit by (i) transferring the data unit to a first coherence structure and (ii) transferring the data unit from the first coherence structure to the first shared memory line segment of the first shared memory.

14. The device according to claim 11 or 12, wherein: The first protocol includes the Advanced Extensible Interface Coherence Extension Protocol, and The second protocol includes the Advanced Extensible Interface Protocol.

15. The apparatus of claim 14, wherein: The first processor and the second processor are configured to, before transmitting the data unit from the first processor to the second processor: retrieving, by the first processor, a previous version of the data unit from the first shared memory; modifying, by the first processor, the previous version of the data unit to provide the data unit; as well as A request to retrieve the data unit is generated by the second processor.

16. The device according to claim 11 or 12, wherein The first shared memory is a shared cache memory.

17. The device according to claim 11 or 12, wherein The first processor is configured to transfer the data unit from the first processor to the second processor before the first processor transfers the data unit to the first shared memory.

18. The apparatus of claim 11 or 12, further comprising: The third processor is configured as follows: transmitting the additional data unit to a fourth processor using the enhanced hardware cache coherence protocol; as well as writing the additional data unit to the second shared memory line segment of the first shared memory without overwriting the first shared memory line segment of the first shared memory, wherein the first processor and the second processor belong to a first processing unit cluster, and The third processor and the fourth processor belong to a second processing unit cluster.

19. The apparatus of claim 18, wherein: The first shared memory is coupled to a further shared memory via a coherency structure.

20. The device according to claim 11 or 12, wherein The apparatus is configured to write, via a processing entity external to the cache coherence domain, a further unit of data to the second shared memory line segment of the first shared memory.

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