Encoding-Storage-Decoding Circuit Based on a Ternary Memristor Crossbar Array

Abstract

The present invention discloses an encoding - storage - decoding circuit based on a ternary memristor cross - array. The present invention includes four parts, among which: the ternary encoder circuit includes an encoder operating voltage source, three input ternary memristors, three voltage - controlled switches, and three setting voltage sources. The ternary memristor cross - array includes multiple array units. The structure of each row includes an input control voltage source, a transistor control voltage source, a switch, and n array units. The structure of each column includes a bidirectional switch, a resistor, and m array units. The ternary signal conversion circuit includes two setting voltage sources, two voltage - controlled switches, one ternary memristor, and a grounding switch. The ternary decoder circuit includes a decoder operating voltage source, three output ternary memristors, six voltage - controlled switches, a setting voltage source, an auxiliary resistor, and a decoding control switch. The structure of the present invention is clear and simple, easy to implement, and has important significance for the application research in the field of memristor - based non - volatile storage.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and relates to a non-volatile storage application circuit design based on a ternary memristor cross array, and specifically relates to an encoding-storage-decoding circuit based on a ternary memristor cross array. Background Art

[0002] In recent years, in the von Neumann architecture, the storage and processing of data are independent of each other, and the information transmission between the processor and the memory consumes a large amount of time and power. However, the performance of current processors is increasing at an alarming rate, while the growth of the memory access speed is much slower, which causes the "memory wall" problem of computers. The key to solving the "memory wall" problem lies in integrating the "computing" of the processor and the "storage" of the memory into one. Due to its small size, low power consumption, and non-volatile characteristics, the memristor has natural advantages as a storage unit, and the memristor is expected to replace traditional CMOS transistor devices for digital logic operations. Therefore, the memory based on the memristor can integrate "computing" and "storage" into one, realizing the integration of storage and computing.

[0003] A large number of memristors can be interconnected in a microscopic space to form a memristor cross array structure. This structure combines the natural storage advantages of the memristor and the characteristics of large-scale parallel processing and computing of the cross array, and will have significant advantages in the integration of storage and computing, including a huge storage capacity, ultra-high storage density, and access speed. Currently, the studied memristor cross arrays are mainly implemented based on binary memristors, with less information that can be stored in the array and only binary logic can be realized. While the cross array based on ternary memristors can store ternary signals, which can not only effectively improve the storage density of non-volatile memories, but also be used to realize ternary digital logic circuits. Since most of the signals in actual circuits are binary signals, directly storing them into the cross array requires consuming more array units. Therefore, constructing a circuit structure that can convert multiple binary signals into one ternary signal and then store it into the ternary memristor cross array, and can restore the ternary signal taken out from the array to a binary signal can further improve the storage function of the non-volatile memory based on the memristor, which has a certain promoting effect on the development of modern information circuits. Summary of the Invention

[0004] The object of the present invention is to propose an encoding-storage-decoding circuit based on a ternary memristor cross array.

[0005] The specific technical solution of the present invention is as follows:

[0006] It includes four parts: a ternary encoder circuit, a ternary memristor cross array, a ternary signal conversion circuit, and a ternary decoder circuit.

[0007] The described ternary encoder circuit includes an encoder operating voltage source, three input ternary memristors, three voltage-controlled switches, and three setting voltage sources.

[0008] The positive pole of the encoder operating voltage source V Run1 is connected to the positive pole of the first encoder input ternary memristor M in1 and the negative pole of the first encoder voltage-controlled switch S En1 ; the negative pole of the first encoder input ternary memristor M in1 is connected to the positive pole of the first encoder voltage-controlled switch S En1 , the negative pole of the second encoder voltage-controlled switch S En2 , and the positive pole of the second encoder input ternary memristor M in2 ; the negative pole of the second encoder input ternary memristor M in2 is connected to the positive pole of the second encoder voltage-controlled switch S En2 , the negative pole of the third encoder voltage-controlled switch S En3 , and the positive pole of the third encoder input ternary memristor M in3 ; the negative pole of the third encoder input ternary memristor M in3 is connected to the positive pole of the third encoder voltage-controlled switch S En3 ; the positive pole of the encoder reset voltage source V Set0 is connected to a control terminal of the first encoder voltage-controlled switch S En1 ; the positive pole of the encoder set-to-1 voltage source V Set1 is connected to a control terminal of the second encoder voltage-controlled switch S En2 ; the positive pole of the encoder set-to-2 voltage source V Set2 is connected to a control terminal of the third encoder voltage-controlled switch S En3 ; the other control terminals of the first encoder voltage-controlled switch S En1 , the second encoder voltage-controlled switch S En2 , and the third encoder voltage-controlled switch S En3 are connected and used as the output terminal of the ternary encoder circuit, which is connected to the negative pole of the input control voltage source V in the first row of the ternary memristor crossbar array; the negative pole of the encoder operating voltage source V Run1 , the negative pole of the encoder reset voltage source V Set0 , the negative pole of the encoder set-to-1 voltage source V Set1 , the negative pole of the encoder set-to-2 voltage source V Set2 , and the negative pole of the third encoder input ternary memristor M in3 are grounded.

[0009] The described ternary memristor crossbar array includes m×n array units, and the structure of each row includes an input control voltage source V and a transistor control voltage source V dd, a switch S, and n array units; each array unit includes a ternary memristor M and a PMOS transistor T, the drain of the PMOS transistor is connected to the positive electrode of the ternary memristor M; the gates of the PMOS transistors of each array unit in the same row are connected in series and connected to the positive electrode of the transistor control voltage source V dd The positive electrodes of the PMOS transistors of each array unit in the same row are connected in series and then connected to the positive electrode of the input control voltage source V through the switch S.

[0010] Each column structure includes a bidirectional switch K, a resistor R, and m array units. The negative electrodes of the ternary memristors M in each array unit in the same column are connected in series and then connected to the normally closed end of the bidirectional switch K. One switching end of the bidirectional switch K is used as the read circuit selection end and grounded through the resistor R, and the other switching end of the bidirectional switch K is used as the write circuit selection end and directly grounded.

[0011] The negative electrodes of the input control voltage sources V of adjacent two-row structures are connected through the isolation switch Z. The negative electrode of the input control voltage source V of the first row is connected to the output end of the ternary encoder circuit, and the negative electrode of the input control voltage source V of the last row is grounded through the isolation switch Z. The negative electrodes of the transistor control voltage sources V of each row structure are connected in series and then grounded. dd

[0012] The described ternary signal conversion circuit includes two setting voltage sources, two voltage-controlled switches, a ternary memristor, and a grounding switch J. The positive electrode of the first conversion voltage-controlled switch S T1 and the positive electrode of the second conversion voltage-controlled switch S T2 are connected to the read circuit selection end of the bidirectional switch K in the first column of the ternary memristor cross array. The negative electrode of the first conversion voltage-controlled switch S T1 and the negative electrode of the second conversion voltage-controlled switch S T2 are grounded; one control end of the first conversion voltage-controlled switch S T1 and one control end of the second conversion voltage-controlled switch S T2 are connected in series and then connected to the positive electrode of the conversion output ternary memristor M in , the negative electrode of the conversion output ternary memristor M in is grounded through the grounding switch J; the other control end of the first conversion voltage-controlled switch S T1 is connected to the positive electrode of the conversion set 1 voltage source V T1 , the other control end of the second conversion voltage-controlled switch S T2 is connected to the positive electrode of the conversion set 2 voltage source V T2 , and the negative electrodes of the conversion set 1 voltage source V T1 and the conversion set 2 voltage source V T2 are grounded.

[0013] The described ternary decoder circuit includes a decoder operating voltage source, three output ternary memristors, six voltage-controlled switches, a setting voltage source, an auxiliary resistor, and a decoding control switch.

[0014] The negative electrode of the first decoder voltage-controlled switch S De1 , the negative electrode of the second decoder voltage-controlled switch S De2 , the negative electrode of the third decoder voltage-controlled switch S De3 , the positive electrode of the fourth decoder voltage-controlled switch S De4 , the positive electrode of the fifth decoder voltage-controlled switch S De5 , and the positive electrode of the sixth decoder voltage-controlled switch S De6 are connected and then connected to the negative electrode of the conversion output ternary memristor M in in the ternary signal conversion circuit and one end of the auxiliary resistor R'; the positive electrode of the first decoder voltage-controlled switch S De1 , the positive electrode of the second decoder voltage-controlled switch S De2 , and the positive electrode of the third decoder voltage-controlled switch S De3 are connected and then connected to the positive electrode of the conversion output ternary memristor M in in the ternary signal conversion circuit, and are connected to the positive electrode of the decoder operating voltage source V De through the decoding control switch K Run2 ; the negative electrodes of the fourth decoder voltage-controlled switch S De4 , the fifth decoder voltage-controlled switch S De5 , and the sixth decoder voltage-controlled switch S De6 are grounded.

[0015] The positive electrode of the first decoder output ternary memristor M out1 is connected to a control terminal of the first decoder voltage-controlled switch S De1 , and the other control terminal of the first decoder voltage-controlled switch S De1 is connected to a control terminal of the fourth decoder voltage-controlled switch S De4 ; the positive electrode of the second decoder output ternary memristor M out2 is connected to a control terminal of the second decoder voltage-controlled switch S De2 , and the other control terminal of the second decoder voltage-controlled switch S De2 is connected to a control terminal of the fifth decoder voltage-controlled switch S De5 ; the positive electrode of the third decoder output ternary memristor M out3 is connected to a control terminal of the third decoder voltage-controlled switch S De3 , and the other control terminal of the third decoder voltage-controlled switch S De3 is connected to a control terminal of the sixth decoder voltage-controlled switch S De6a control terminal; the fourth decoder voltage-controlled switch S De4 another control terminal, the fifth decoder voltage-controlled switch S De5 another control terminal, the sixth decoder voltage-controlled switch S De6 After connecting another control terminal, it is connected to the decoder set-1 voltage source V Set1 positive electrode. The first decoder outputs the three-valued memristor M out1 negative electrode, the second decoder outputs the three-valued memristor M out2 negative electrode, the third decoder outputs the three-valued memristor M out3 negative electrode, the decoder operating voltage source V Run2 negative electrode, the decoder set-1 voltage source V Set1 negative electrode, the other end of the auxiliary resistor R' is grounded.

[0016] The operation process of the encoding-storage-decoding circuit based on the three-valued memristor cross array is divided into four steps:

[0017] The first step is to read the initial state of the encoder input three-valued memristor M in1 -M in3 to determine the input signal of the circuit;

[0018] The second step is to perform encoding and storage operations simultaneously, encoding three binary signals into one three-valued signal and storing it in the storage unit of the three-valued memristor cross array.

[0019] The third step is to perform signal reading and conversion operations simultaneously. The signal read from the cross array is a voltage signal. In this step, it is necessary to convert the voltage signal into a resistance signal of the three-valued memristor while reading the voltage signal.

[0020] The fourth step is the decoding operation, restoring the read one three-valued signal back to three binary signals.

[0021] The present invention realizes the function of encoding three binary signals into one three-valued signal for storage and restoring them to three binary signals through a decoder. The present invention can realize the access of three binary signals only through one array storage unit, which can effectively save the storage space of the memory. The structure of the present invention is clear and simple, easy to implement, and has important significance for the application research in the field of memristor-based non-volatile storage. Description of the Drawings

[0022] Figure 1 is the schematic diagram of the three-valued encoder circuit in the present invention;

[0023] Figure 2 is the schematic diagram of a row of array units in the three-valued memristor cross array in the present invention;

[0024] Figure 3Schematic diagram of a column of array units in the ternary memristor cross array of the present invention;

[0025] Figure 4 Schematic diagram of the ternary signal conversion circuit of the present invention;

[0026] Figure 5 Schematic diagram of the ternary decoder circuit of the present invention. Detailed implementation manners

[0027] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings.

[0028] In the ternary encoder, ternary memristor cross array, ternary signal conversion circuit, and ternary decoder of the present invention, the resistance value of the memristor is used as a logical variable. A ternary memristor can store one bit of ternary signal, and its resistance state can be represented by R H , R M and R L , corresponding to "0", "1", and "2" in ternary logic respectively.

[0029] The first part of the circuit is as shown in Figure 1 , with the input being the resistance states of M in1 , M in2 and M in3 , and the output being the setting voltage of the encoder setting voltage source. This voltage will be directly applied to the array unit M 1,1 of the ternary memristor cross array. S En1 -S En3 are voltage-controlled switches, and the switch conducts only when the applied control voltage exceeds its threshold voltage. In the circuit, the voltage dividers of the three input memristors are respectively used as the control voltages of the three voltage-controlled switches to ensure that only one voltage-controlled switch is conducted under different inputs. The voltage sources V Set0 -V Set2 output the set-0, set-1, and set-2 voltages respectively. After the voltage-controlled switch is conducted, the setting operation of the array unit M 1,1 is completed. The three-way binary signals input after being encoded by the encoder will be encoded into one-way ternary signal and stored in the array unit M 1,1 .

[0030] The row and column structures of the second part of the circuit are respectively as shown in Figure 2 and Figure 3 , and a ternary memristor cross array can be formed through this row and column structure for storing ternary signals. The array unit of the cross array consists of a ternary memristor M in series with a transistor T. The transistor acts as a switch. As long as the transistor is off, no current will flow through the array unit, which can effectively suppress the leakage current generated in the cross array. The conduction voltage of the transistor is V DD, whether each row of transistors is turned on or off is controlled by a voltage source V dd Control. A bidirectional switch K is connected to the negative electrode of each ternary memristor in the crossbar array, which is used to select the read circuit or the write circuit to complete the corresponding read and write operations. Among them, the write operation is completed by grounding the negative electrode of the ternary memristor and applying a write voltage. The read operation is to measure the partial voltage V R on the auxiliary resistor R and compare it with the discrimination voltage to obtain the logic state of the measured unit. The discrimination voltage for the array read operation in the circuit is set to V JUDGE1 and V JUDGE2 . When V R >V JUDGE2 , it is determined that the selected unit is logic "2". When V JUDGE1 <V R <V JUDGE2 , it is determined that the selected unit is logic "1". When V R <V JUDGE1 , it is determined that the selected unit is logic "0".

[0031] The third part of the circuit is as shown in Figure 4 . As can be seen from the above analysis, the signals in the crossbar array exist in the form of voltage after being read out, while the input of the ternary decoder is the resistance value of the ternary memristor. Therefore, it is necessary to convert the read voltage signal into the resistance value of the ternary memristor M in through a ternary signal conversion circuit. M in acts as the output memristor in the ternary signal conversion circuit and as the input memristor in the ternary decoder circuit. The ternary signal conversion circuit mainly uses the read voltage V R of the crossbar array to control the conduction of the voltage-controlled switches S T1 and S T2 to realize the conversion of the voltage signal to the resistance value of the ternary memristor. The threshold voltages of S T1 and S T2 in the figure are set to V JUDGE1 and V JUDGE2 respectively. The initial resistance value of the ternary memristor M in is R H . If the state of the array unit M 1,1 is logic "0", then V R <V JUDGE1 . At this time, neither switch S T1 nor S T2 conducts; if the state of M 1,1 is logic "1", then V JUDGE1 <V R <V JUDGE2 . At this time, switch S T1 conducts, S T2 does not conduct, and the voltage source V T1 outputs a "1" voltage to make Min The resistance state of H switches from R M to R 1,1 ; if the state of M R is logic "2", then V JUDGE2 > V T1 and S T2 are both turned on, and the voltage source V T2 outputs a "2" voltage to make the resistance state of M in switch from R H to R L .

[0032] The fourth part of the circuit is as Figure 5 shown, with the input being the resistance state of M in , and the outputs being the resistance states of M out1 , M out2 and M out3 , all of whose initial resistances are R H . The voltage source V Set1 outputs a "1" voltage to perform a "1" operation on the output memristor, and the auxiliary resistor R is used to cooperate with the input memristor for voltage division. Each output memristor in the circuit is connected to two voltage-controlled switches, which is to ensure that only one output memristor is connected to the voltage source V Set1 under different inputs. This decoder circuit can restore a three-valued signal read from the array back to three two-valued signals.

[0033] A total of four operation steps are required to implement one encoding-storage-decoding process of three two-valued signals. The specific implementation process is as shown in the following table:

[0034]

[0035] Step 1: 0 - 10 ms, all switches are turned off, and the voltage source V Run1 outputs a read voltage of 1.5 V. This stage is used to read the initial states of the three-valued memristors M in1 , M in2 and M in3 .

[0036] Step 2: 10 - 20 ms, the voltage source V Run1 outputs an encoder operating voltage of 1 V, and V Set0 , V Set1 and V Set2 output the corresponding set-0, set-1, and set-2 voltages respectively. In addition, the storage unit M 1,1 needs to be selected, switch S1 is closed, and K1 is thrown to the "Write" terminal. At the same time, make V dd1 output V DD。These two operations, encoding and storing, are carried out synchronously in this stage, and the encoded ternary signal is written into M 1,1 in the meantime.

[0037] Step 3: At 20 - 30 ms, close switch S1, throw K1 to the "Read" terminal, and voltage source V dd1 outputs V DD , and V1 outputs a read voltage of 0.5 V to perform the read operation on the crossbar array. Meanwhile, close switch J, and set voltage sources V T1 and V T2 to output 1.1 V and 1.3 V respectively. In this stage, the operations of signal reading and conversion are carried out synchronously, and the read voltage signal is converted into the input memristor resistance value of the ternary decoder.

[0038] Step 4: At 30 - 40 ms, close switch K DE , disconnect all other switches, voltage source V Run2 outputs a decoder operating voltage of 1.2 V, and at the same time make V Set1 output a set - to - 1 voltage of 1 V. In this stage, the decoding operation of the ternary signal is completed, and the output signals are respectively stored in output memristors M out1 , M out2 and M out3 in the meantime.

[0039] Those of ordinary skill in the art should recognize that the above embodiments are only used to verify the present invention, rather than as a limitation to the present invention. As long as it is within the scope of the present invention, changes and deformations of the above embodiments will fall within the protection scope of the present invention.

Claims

1. A coding-storing-decoding circuit based on a three-valued memristor cross array, characterized in that Comprising: It includes four parts: a ternary encoder circuit, a ternary memristor crossbar array, a ternary signal conversion circuit, and a ternary decoder circuit; The described ternary encoder circuit includes an encoder operating voltage source, three input ternary memristors, three voltage-controlled switches, and three set voltage sources; Encoder operating voltage source V Run1 The positive pole of is connected to the positive pole of the first encoder input ternary memristor M in1 And the negative pole of the first encoder voltage-controlled switch S En1 The negative pole of the first encoder input ternary memristor M in1 The negative pole is connected to the positive pole of the first encoder voltage-controlled switch S En1 The positive pole, the negative pole of the second encoder voltage-controlled switch S En2 And the positive pole of the second encoder input ternary memristor M in2 The positive pole of the second encoder input ternary memristor M in2 The negative pole is connected to the positive pole of the second encoder voltage-controlled switch S En2 The positive pole, the negative pole of the third encoder voltage-controlled switch S En3 And the positive pole of the third encoder input ternary memristor M in3 The positive pole of the third encoder input ternary memristor M in3 The negative pole is connected to the positive pole of the third encoder voltage-controlled switch S En3 The positive pole; the encoder reset to 0 voltage source V Set0 The positive pole is connected to a control terminal of the first encoder voltage-controlled switch S En1 The positive pole of the encoder set to 1 voltage source V Set1 The positive pole is connected to a control terminal of the second encoder voltage-controlled switch S En2 The positive pole of the encoder set to 2 voltage source V Set2 The positive pole is connected to a control terminal of the third encoder voltage-controlled switch S En3 A control terminal of the first encoder voltage-controlled switch S En1 The second encoder voltage-controlled switch S En2 And the third encoder voltage-controlled switch S En3 The other control terminal is connected as the output terminal of the ternary encoder circuit and is connected to the negative pole of the input control voltage source V in the first row of the ternary memristor cross array; the encoder operating voltage source V Run1 The negative pole, the negative pole of the encoder reset to 0 voltage source V Set0 The negative pole, the negative pole of the encoder set to 1 voltage source V Set1 The negative pole, the negative pole of the encoder set to 2 voltage source V Set2 The negative pole and the negative pole of the third encoder input ternary memristor M in3 The negative pole is grounded; The described ternary memristor crossbar array includes m×n array units. The structure of each row includes an input control voltage source V, a transistor control voltage source V dd , a switch S, and n array units; each array unit includes a ternary memristor M and a PMOS transistor. The drain of the PMOS transistor is connected to the positive electrode of the ternary memristor M; the gates of the PMOS transistors of each array unit in the same row are connected in series and connected to the positive electrode of the transistor control voltage source V dd . After the sources of the PMOS transistors of each array unit in the same row are connected in series, they are connected to the positive electrode of the input control voltage source V through the switch S; Each column structure includes a bidirectional switch K, a resistor R, and m array units. The negative electrodes of the ternary memristors M in each array unit of the same column are connected in series and then connected to the normally closed end of the bidirectional switch K. One switching end of the bidirectional switch K is used as the read circuit selection end and grounded through the resistor R, and the other switching end of the bidirectional switch K is used as the write circuit selection end and directly grounded; The negative poles of the input control voltage sources V of two adjacent rows of structures are connected through the isolation switch Z. The negative pole of the input control voltage source V of the first row is connected to the output terminal of the ternary encoder circuit. The negative pole of the input control voltage source V of the last row is grounded through the isolation switch Z. The negative poles of the transistor control voltage sources V of each row of structures are connected in series and then grounded; dd are connected in series and then grounded; The described three-valued signal conversion circuit includes two setting voltage sources, two voltage-controlled switches, a three-valued memristor, and a grounding switch J; the positive pole of the first conversion voltage-controlled switch S T1 and the positive pole of the second conversion voltage-controlled switch S T2 are connected to the read circuit selection terminal of the bidirectional switch K in the first column of the three-valued memristor cross array. The negative pole of the first conversion voltage-controlled switch S T1 and the negative pole of the second conversion voltage-controlled switch S T2 are grounded; one control terminal of the first conversion voltage-controlled switch S T1 and one control terminal of the second conversion voltage-controlled switch S T2 are connected in series and then connected to the positive pole of the conversion output three-valued memristor M in . The negative pole of the conversion output three-valued memristor M in is grounded through the grounding switch J; the other control terminal of the first conversion voltage-controlled switch S T1 is connected to the positive pole of the conversion set-1 voltage source V T1 . The other control terminal of the second conversion voltage-controlled switch S T2 is connected to the positive pole of the conversion set-2 voltage source V T2 . The negative poles of the conversion set-1 voltage source V T1 and the conversion set-2 voltage source V T2 are grounded; The described ternary decoder circuit includes a decoder operating voltage source, three output ternary memristors, six voltage-controlled switches, a set voltage source, an auxiliary resistor, and a decoding control switch; The negative electrode of the first decoder voltage-controlled switch S De1 The negative electrode of the second decoder voltage-controlled switch S De2 The negative electrode of the third decoder voltage-controlled switch S De3 The negative electrode of the fourth decoder voltage-controlled switch S De4 The positive electrode of the fifth decoder voltage-controlled switch S De5 The positive electrode of the sixth decoder voltage-controlled switch S De6 After being connected, the positive electrode is connected to the negative electrode of the three-valued memristor M output by conversion in the three-valued signal conversion circuit in And one end of the auxiliary resistor R'; the positive electrode of the first decoder voltage-controlled switch S De1 The positive electrode of the second decoder voltage-controlled switch S De2 The positive electrode of the third decoder voltage-controlled switch S De3 After being connected, the positive electrode is connected to the positive electrode of the three-valued memristor M output by conversion in the three-valued signal conversion circuit in And is connected to the positive electrode of the decoder operating voltage source V De Through the decoder control switch K Run2 The negative electrode of the fourth decoder voltage-controlled switch S De4 The negative electrode of the fifth decoder voltage-controlled switch S De5 The negative electrode of the sixth decoder voltage-controlled switch S De6 The negative electrode is grounded The positive pole of the first decoder output ternary memristor M out1 is connected to a control terminal of the first decoder voltage-controlled switch S De1 ; another control terminal of the first decoder voltage-controlled switch S De1 is connected to a control terminal of the fourth decoder voltage-controlled switch S De4 ; the positive pole of the second decoder output ternary memristor M out2 is connected to a control terminal of the second decoder voltage-controlled switch S De2 ; another control terminal of the second decoder voltage-controlled switch S De2 is connected to a control terminal of the fifth decoder voltage-controlled switch S De5 ; the positive pole of the third decoder output ternary memristor M out3 is connected to a control terminal of the third decoder voltage-controlled switch S De3 ; another control terminal of the third decoder voltage-controlled switch S De3 is connected to a control terminal of the sixth decoder voltage-controlled switch S De6 ; another control terminal of the fourth decoder voltage-controlled switch S De4 , another control terminal of the fifth decoder voltage-controlled switch S De5 and another control terminal of the sixth decoder voltage-controlled switch S De6 are connected and then connected to the positive pole of the decoder set-to-1 voltage source V Set1 ; the negative pole of the first decoder output ternary memristor M out1 , the negative pole of the second decoder output ternary memristor M out2 , the negative pole of the third decoder output ternary memristor M out3 , the negative pole of the decoder operating voltage source V Run2 , the negative pole of the decoder set-to-1 voltage source V Set1 and the other end of the auxiliary resistor R' are grounded.

Images