Semiconductor test chip with electrically connected pads having adjustable energy states and method for fabricating the same

Abstract

A semiconductor test chip with an electrically connected pad having an adjustable energy state for use in wire bonding reliability testing of semiconductor components, comprising a semiconductor substrate, and at least one test chip disposed on the semiconductor substrate. The at least one test chip has a top surface away from the semiconductor substrate and an electrically connected pad exposed from the top surface. The electrically connected pad has a metal layer and an energy state layer formed on the surface layer of the metal layer. Among them, the energy state layer is combined with the metal layer and has an energy gap different from that of the metal layer. In addition, the present invention also provides a method for manufacturing the semiconductor test chip. By simulating the oxidation and corrosion damage conditions of semiconductor components in different environments through the energy state layer, the reaction during the reliability test using the semiconductor test chip can be accelerated, so as to reduce the time of the reliability test.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip and a manufacturing method thereof, and particularly to a semiconductor test chip for wire bonding reliability testing and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor manufacturing technology, the size of semiconductor chips has become increasingly miniaturized. Among them, wire bonding is an important technology that enables miniaturized semiconductor chips to be externally electrically connected. Therefore, how to ensure the wire bonding reliability of semiconductor chips is an important issue that relevant industries actively pay attention to.

[0003] The metal layer used for external electrical connection of semiconductor chips is generally composed of aluminum or copper. However, aluminum or copper is prone to adsorbing foreign ions in the external environment, and the adsorbed foreign ions on the surface (such as chloride ions, nitrogen ions, etc.) are prone to causing corrosion of the metal layer or reacting with the metal layer to form intermetallic compounds due to different surface energy states from the metal layer. Therefore, when the metal layer is subsequently used for wire bonding or forming copper bumps for soldering to make external electrical connections and the semiconductor components are packaged, the corrosion of the metal layer caused by the adsorbed foreign ions over time, or the galvanic corrosion between the metal layer and the wire bonding / copper bumps becomes more and more serious, thereby affecting the conductivity of the metal layer or the adhesion between the wire bonding / copper bumps and the metal layer, causing the wire bonding / copper bumps to peel off or fall off during the use of the semiconductor components, and having an adverse impact on the reliability of the components.

[0004] Therefore, in order to ensure the reliability and yield of semiconductor chips, the wire bonding reliability test of semiconductor components is generally carried out before packaging. However, since the reliability test needs to simulate different environmental conditions and requires long-term testing, the relevant tests are extremely time-consuming. Summary of the Invention

[0005] The purpose of the present invention is to provide a semiconductor test chip with an electrically connectable pad having an adjustable energy state for wire bonding reliability testing of semiconductor components.

[0006] The semiconductor test chip of the present invention includes a semiconductor substrate and at least one test chip.

[0007] The at least one test chip is disposed on the semiconductor substrate, including a top surface opposite to the semiconductor substrate, and at least one electrically connectable pad exposed outward from the top surface. The electrically connectable pad includes a metal layer and an energy state layer formed on the surface layer of the metal layer, wherein the energy state layer is combined with the metal layer and has an energy gap different from that of the metal layer.

[0008] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the energy state layer includes a metal compound containing at least one element such as halogen, nitrogen, oxygen, and hydrogen.

[0009] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the material of the metal layer is aluminum, aluminum alloy, copper, or copper alloy. When the metal layer is copper or copper alloy, the energy state layer is selected from at least one of CuClxOHy, CuxOHy, CuxNy, CuxNyOHz, and CuxOyNz, where x > 0, y > 0, z > 0; when the metal layer is aluminum or aluminum alloy, the energy state layer is selected from at least one of AlClx, AlClxOHy, AlOHx, AlxNy, AlxNyOHz, and AlxOyNz, where x > 0, y > 0, z > 0.

[0010] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the at least one test chip further includes a test circuit, a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening, and the at least one electrically connectable pad is connected to the redistribution line and exposed to the outside through the opening.

[0011] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the semiconductor test chip includes several test chips arrayed on the semiconductor substrate, and the test chips arrayed on the semiconductor substrate can be connected in series through the electrically connectable pads to form at least one conductive circuit that can be independently externally electrically connected.

[0012] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the energy state layer is formed by subjecting the metal layer to plasma or corrosive gas aeration treatment.

[0013] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the energy state layer is obtained by subjecting the metal layer to plasma treatment containing at least one element of halogen, nitrogen, oxygen, and hydrogen.

[0014] Another object of the present invention is to provide a method for manufacturing a semiconductor test chip with an electrically connectable pad having an adjustable energy state for use in wire bonding reliability testing of semiconductor components.

[0015] The method for manufacturing the semiconductor test chip of the present invention includes the following steps:

[0016] Provide a semiconductor component semi-finished product, the semiconductor component semi-finished product having a semiconductor substrate and at least one chip disposed on the semiconductor substrate, and the at least one chip having a metal layer exposed from its top surface to the outside.

[0017] The metal layer is surface-treated with plasma or corrosive gas to form an energy state layer bonded to the surface of the metal layer and having an energy gap different from that of the metal layer, so as to obtain the semiconductor test chip.

[0018] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the material of the metal layer is selected from aluminum, aluminum alloy, copper, or copper alloy.

[0019] Preferably, for the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention, the energy state layer is obtained by plasma-treating the metal layer with at least one element containing halogen, nitrogen, oxygen, or hydrogen.

[0020] The beneficial effect of the present invention is that: the metal layer of the semiconductor component semi-finished product for external electrical connection is surface-treated with plasma or corrosive gas, and an energy state layer having an energy gap different from that of the metal layer is formed on the metal layer, so that the oxidation and corrosion damage conditions of the semiconductor component in different environments can be simulated and induced through the energy state layer, and the reaction during the reliability test using the semiconductor test chip can be accelerated, so as to reduce the time of the reliability test. Description of the Drawings

[0021] Figure 1 is a top view schematic diagram of an embodiment of the semiconductor test chip of the present invention;

[0022] Figure 2 is a cross-sectional structural schematic diagram of one of the test chips in the embodiment;

[0023] Figure 3 is the XPS measurement result of different energy state layers obtained after oxygen plasma treatment. Detailed Embodiments

[0024] The present invention will be described in detail below with reference to the drawings and embodiments.

[0025] It should be noted that the drawings of the present invention only represent the structural and / or positional relative relationship between components, and are not directly related to the actual sizes of the components.

[0026] The semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention is used for the wire bonding reliability test of semiconductor components.

[0027] Refer to Figure 1 、 2 , an embodiment of the semiconductor test chip with an electrically connectable pad having an adjustable energy state according to the present invention includes a semiconductor substrate 2 and several test chips 3.

[0028] The semiconductor substrate 2 can be selected from silicon, compound semiconductors (such as silicon carbide (SiC)), group III-IV semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), or group II-VI semiconductor materials such as zinc oxide (ZnO) and cadmium telluride (CdTe).

[0029] The test chips 3 are arranged on the semiconductor substrate 2 in an array arrangement. For example, the test chips 3 can be arranged on the semiconductor substrate 2 in a 9×9 array, and each test chip 3 has a top surface opposite to the semiconductor substrate 2 and at least one electrical connection pad 34 exposed outward from its top surface. The test chips 3 can be connected in series through the electrical connection pads 34 to form at least one conductive circuit that can be independently externally electrically connected.

[0030] Each test chip 3 has a test circuit 31, a redistribution line 32 located above the test circuit 31 and electrically connected to the test circuit 31, a dielectric layer 33 covering the redistribution line 32 and having a plurality of openings 331, and a plurality of electrical connection pads 34. The electrical connection pads 34 are respectively connected to the redistribution line 32 and are respectively exposed outward from a corresponding one of the openings 331 of the dielectric layer 33.

[0031] Specifically, the test circuit 31 has a plurality of dielectric insulating layers 311, metal wiring layers 312, and a plurality of conductive vias 313 that are alternately stacked on the semiconductor substrate 2. The conductive vias 313 penetrate through the dielectric insulating layers 311 to electrically connect the metal wiring layers 312 in different ways, so as to form different conduction loops. Among them, in order to simulate the circuit of a general functional chip, the number of layers, thickness, and electrical connection relationship of the dielectric insulating layer 311 and the metal wiring layer 312 of the test circuit 31 can also fully simulate the circuit structure of the functional chip. In this way, the circuit test results of the test chip 3 can also be fed back to the fully functional chip to correspondingly adjust the circuit design of the functional chip. The aforementioned dielectric insulating layer 311 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer materials, and the metal wiring layer 312 and the conductive vias 313 can be respectively selected from conductive materials such as tungsten, aluminum, copper, aluminum alloy, or copper alloy. Since the related manufacturing processes and materials used for this test electrical structure are well known to those skilled in the semiconductor technology field, no further elaboration will be provided.

[0032] The redistribution line 32 is disposed above the test circuit 31 and electrically connected to the test circuit 31. The dielectric layer 33 covers the redistribution line 32 and has a plurality of openings 331. The electrical connection pads 34 are connected to the redistribution line 32 and are respectively exposed to the outside from the corresponding openings 331 of the dielectric layer 33, for subsequent wire bonding or forming solder or copper bumps, so that the metal wiring layers 312 are connected in series to form at least one independent conductive loop and can be electrically connected to the outside. The redistribution line 32 can be selected from conductive materials such as aluminum, aluminum alloy, copper or copper alloy, and the dielectric layer 33 can be selected from silicon dioxide, silicon nitride, silicon oxynitride, or polymer insulating materials, etc.

[0033] Each electrical connection pad 34 has a metal layer 341 electrically connected to the redistribution line 32, and an energy state layer 342 covering at least a part of the surface of the metal layer 341. The metal layer 341 is made of materials such as aluminum, aluminum alloy, copper or copper alloy, is connected to the redistribution line 32 and can be exposed to the outside from one of the openings 331. The energy state layer 342 covers at least a part of the surface of the metal layer 341, and the band gap or binding energy of the energy state layer 342 can be greater than or less than the band gap or binding energy of the metal layer 341, and has a different band gap or binding energy from the metal layer 341. Among them, the energy state layer 342 includes a metal compound containing at least one of elements such as halogen, nitrogen, oxygen, hydrogen, etc., and the metal compound is obtained by the reaction of at least one of elements such as halogen, nitrogen, oxygen, hydrogen, etc. with the metal of the metal layer 341.

[0034] It should be noted that the energy state layer 342 is different according to the composition material of the metal layer 341 and the types of gases or plasmas used for treatment. For example, when the material of the metal layer 341 is copper or copper alloy, the energy state layer 342 can include at least one of CuClxOHy, CuxOHy, CuxNy, CuxNyOHz, and CuxOyNz by the selection of plasmas or corrosive gases containing at least one of elements such as halogen, nitrogen, oxygen, hydrogen, etc., where x>0, y>0, z>0; when the material of the metal layer 341 is aluminum or aluminum alloy, the energy state layer 342 can include at least one of AlClx, AlClxOHy, AlOHx, AlxNy, AlxNyOHz, and AlxOyNz by the selection of the types of plasmas or corrosive gases containing at least one of elements such as halogen, nitrogen, oxygen, hydrogen, etc., where x>0, y>0, z>0.

[0035] The aforementioned energy state layer 342 can be formed on the surface of the metal layer 341 by surface treatment of the metal layer 341 using selected plasmas or corrosive gases.

[0036] The surface of the metal layer 341 is treated by selecting different plasmas or corrosive gases to form an energy state layer 342 with a desired energy gap on the metal layer 341, so as to obtain a semiconductor test chip with an adjustable energy state for the electrical connection pad 34.

[0037] A method for manufacturing a semiconductor test chip with an electrical connection pad having an adjustable energy state according to the present invention includes:

[0038] Providing a semiconductor component semi-finished product, the semiconductor component semi-finished product having the semiconductor substrate 2 and at least one chip disposed on the semiconductor substrate 2, and the at least one chip having a metal layer 341 exposed outward from its top surface; and

[0039] Using a plasma or a corrosive gas to perform a surface treatment on the metal layer 341 to form an energy state layer 342 combined with the surface of the metal layer 341 and having an energy gap different from that of the metal layer 341, so as to manufacture the semiconductor test chip.

[0040] Refer to Table 1 below and Figure 3 , Figure 3 is an XPS energy spectrum diagram of different energy state layers 342 obtained by treating the metal layer 341 with oxygen plasma for different times (20 to 70 seconds (sec)). Table 1 is Figure 3 the binding energy shift result of the metal layer 341 and the energy state layer 342 at the position indicated by the dashed line in Figure 3 The material of the metal layer 341 is platinum (Pt) in order to avoid the influence of the metal layer 341 material on the XPS measurement of the energy state layer 342.

[0041] Table 1

[0042] Plasma treatment time (sec.) Binding energy difference (eV) 70 +0.1 60 +0.1 50 +0.2 40 +0.3 30 +0.5 20 +0.6

[0043] It can be clearly seen from the foregoing Table 1 and Figure 3 that an energy state layer 342 with an energy gap different from that of the metal layer 341 can be formed on the surface of the metal layer 341 after oxygen plasma treatment for different times. Therefore, subsequent wire bonding is performed using the semiconductor test chip with the electrical connection pad 34 having an adjustable energy state and applied to a wire bonding reliability test for simulating different environmental conditions. The oxidation and corrosion damage conditions of the semiconductor component in different environments can be simulated through the energy state layer 342, so as to accelerate the reaction during the reliability test and reduce the time of the reliability test.

[0044] In summary, the present invention uses plasma or corrosive gas to perform surface treatment on the metal layer 341 of the semiconductor component semi-finished product, and a energy state layer 342 with an energy gap different from that of the metal layer 341 is formed on the metal layer 341, thereby obtaining a semiconductor test chip with an adjustable energy state electrical connection pad. Therefore, when performing reliability tests such as wire bonding or forming copper bumps for wire bonding on the electrical connection pad 34 of the semiconductor test piece subsequently, the oxidation and corrosion damage conditions of the semiconductor component in different environments can be simulated and induced through the energy state layer 342, so as to accelerate the reaction of performing reliability tests using the semiconductor test chip, reduce the time of reliability tests, and thus can indeed achieve the purpose of the present invention.

Claims

1. A semiconductor test chip with an electrically connectable pad having an adjustable energy state for use in wire bonding reliability testing of semiconductor components, the semiconductor test chip comprising: a semiconductor substrate; and at least one test chip disposed on the semiconductor substrate, characterized in that: the at least one test chip includes: a top surface opposite to the semiconductor substrate; and at least one electrical connection pad exposed outward from the top surface, including a metal layer and an energy state layer formed on the surface layer of the metal layer, wherein the energy state layer is combined with the metal layer and has an energy gap different from that of the metal layer; wherein the constituent material of the metal layer is aluminum, aluminum alloy, copper, or copper alloy. When the metal layer is copper or copper alloy, the energy state layer is selected from at least one of CuClxOHy, CuxOHy, CuxNyOHz, and CuxOyNz, where x > 0, y > 0, z > 0; when the metal layer is aluminum or aluminum alloy, the energy state layer is selected from at least one of AlClxOHy, AlOHx, AlxNyOHz, and AlxOyNz, where x > 0, y > 0, z > 0; By selecting different plasmas or corrosive gases to perform surface treatment on the metal layer, the energy state layer with the required energy gap is formed on the metal layer, so that the semiconductor test chip with the electrically connectable pad having adjustable energy state can be obtained; by simulating the oxidation and corrosion damage conditions of the semiconductor component in different environments through the energy state layer, the semiconductor test chip is applied to the wire bonding reliability test under different environmental conditions.

2. The semiconductor test chip with an electrically connectable pad having an adjustable energy state according to claim 1, characterized in that: The at least one test chip further includes a test circuit, a redistribution line located above the test circuit and electrically connected to the test circuit, and a dielectric layer covering the redistribution line and having at least one opening, and the at least one electrical connection pad is connected to the redistribution line and exposed outward from the opening.

3. The semiconductor test chip with an electrically connectable pad having an adjustable energy state according to claim 2, wherein: The semiconductor test chip includes several test chips arrayed on the semiconductor substrate, and the test chips arrayed on the semiconductor substrate can be connected in series through the electrical connection pads to form at least one conductive circuit that can be independently externally electrically connected.

4. A method for fabricating a semiconductor test chip with an electrically connected pad having an adjustable energy state, characterized in that: It includes: providing a semiconductor component semi-finished product having a semiconductor substrate and at least one chip disposed on the semiconductor substrate, and the at least one chip has a metal layer exposed outward from its top surface, wherein the material of the metal layer is selected from aluminum, aluminum alloy, copper, or copper alloy; and using plasma or corrosive gas to perform surface treatment on the metal layer to form an energy state layer combined with the surface of the metal layer and having an energy gap different from that of the metal layer to obtain the semiconductor test chip, when the metal layer is copper or copper alloy, the energy state layer is selected from at least one of CuClxOHy, CuxOHy, CuxNyOHz, and CuxOyNz, where x > 0, y > 0, z > 0; when the metal layer is aluminum or aluminum alloy, the energy state layer is selected from at least one of AlClxOHy, AlOHx, AlxNyOHz, and AlxOyNz, where x > 0, y > 0, z > 0; The surface of the metal layer is treated by selecting different plasmas or corrosive gases to form the energy state layer with the required energy gap on the metal layer, so that the semiconductor test chip with the adjustable energy state electrical connection pads can be obtained; by simulating the oxidation and corrosion damage conditions of the semiconductor component in different environments through the energy state layer, the semiconductor test chip is applied to the wire bonding reliability test for simulating different environmental conditions.

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