Common-mode Inductor Package Structure and Manufacturing Method

Abstract

The present invention provides a common-mode inductor packaging structure and a manufacturing method. The common-mode inductor packaging structure includes: a substrate, the substrate includes opposite first and second surfaces; a first stacked structure, the first stacked structure is disposed on the first surface, the first stacked structure includes at least one first conductive layer and at least one first dielectric layer, and each of the first conductive layers and each of the first dielectric layers are alternately stacked; a first encapsulation layer, the first encapsulation layer is disposed on the surface of the first stacked structure away from the substrate, and the first encapsulation layer covers the first stacked structure; and a second stacked structure, the second stacked structure is disposed on the surface of the first encapsulation layer away from the first stacked structure, and the second stacked structure includes at least one second conductive layer and at least one second dielectric layer, and each of the second conductive layers and each of the second dielectric layers are alternately stacked.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a common-mode inductor packaging structure and a manufacturing method thereof. Background Art

[0002] A common-mode inductor, also called a common-mode choke coil, is often used to filter common-mode electromagnetic interference signals. In the design of circuit boards, the common-mode inductor also plays the role of EMI filtering, which is used to suppress the electromagnetic waves generated by high-speed signal lines from radiating outward. Substantially, the common-mode inductor is a two-way filter: on the one hand, it is necessary to filter out the common-mode electromagnetic interference on the signal line, and on the other hand, it is necessary to suppress itself from emitting electromagnetic interference outward to avoid affecting the normal operation of other electronic devices in the same electromagnetic environment. In actual circuit design, a multi-stage common-mode circuit can also be used to better filter out electromagnetic interference.

[0003] As Figure 1 shown, the manufacturing of the existing common-mode inductor packaging structure generally includes: fabricating multiple layers of dielectric layers 2 and metal wiring layers 3 that are alternately stacked on one side surface of a silicon substrate 1; a cutting jig 5 cuts in a cutting groove 1a reserved on the silicon substrate 1 to obtain a common-mode inductor packaging structure 4.

[0004] During the manufacturing process of the above-mentioned common-mode inductor packaging structure 4, 1) since it is necessary to fabricate multiple layers of dielectric layers 2 and multiple layers of metal wiring layers 3, and the thermal expansion coefficients of the multiple layers of dielectric layers 2 and the multiple layers of metal wiring layers 3 are different from that of the silicon substrate 1, therefore, the silicon substrate 1 is prone to warping; 2) each dielectric layer 2 and each metal wiring layer 3 are alternately stacked, and as the number of stacked layers increases, the phenomenon of undulation is likely to occur between the film layers, which affects the electrical signal transmission of the metal wiring layer 3; 3) the dielectric layer 2 needs to reserve a gap in the area corresponding to the cutting groove 1a reserved on the silicon substrate 1, that is, the dielectric layer 2 should not cover the cutting groove 1a to avoid the silicon substrate 1 below it from chipping during the cutting process; 4) since the dielectric layer 2 does not cover the cutting groove 1a, a large height difference d appears between the edge of the packaging structure 4 and the silicon substrate 1, and this height difference d is likely to cause problems such as photolithography residual glue, coating bubbles, and electroplating leakage; 5) only the lowermost dielectric layer 2 among the multiple layers of dielectric layers 2 is in contact with the silicon substrate 1, and the other upper dielectric layers 2 are not in contact with the silicon substrate 1. Among them, there is a large stress in the multi-layer structure of the upper stacked dielectric layers 2 and metal wiring layers 3, and this large stress is likely to cause delamination between the lowermost dielectric layer 2 and the silicon substrate 1, resulting in the failure of the packaging structure 4.

[0005] In view of this, it is necessary to propose a common-mode inductor packaging structure and a manufacturing method that can overcome the delamination problem between the dielectric layer and the silicon substrate, reduce the warping of the silicon substrate, reduce the manufacturing difficulty of the common-mode inductor packaging structure, and reduce the interference of the common-mode inductor packaging structure on electrical signal transmission. Summary of the Invention

[0006] The problem to be solved by the present invention is how to improve the delamination between the edge of the dielectric layer and the silicon substrate, reduce the warping of the silicon substrate, reduce the manufacturing difficulty of the common-mode inductor packaging structure, and reduce the interference of the common-mode inductor packaging structure on the transmission of electrical signals.

[0007] To solve the above problems, the technical solution of the present invention provides a common-mode inductor packaging structure, which includes: a substrate including opposite first and second surfaces; a first stacked structure disposed on the first surface, the first stacked structure including at least one first conductive layer and at least one first dielectric layer, with each first conductive layer and each first dielectric layer alternately stacked; a first encapsulation layer disposed on the surface of the first stacked structure away from the substrate, the first encapsulation layer covering the first stacked structure; and a second stacked structure disposed on the surface of the first encapsulation layer away from the first stacked structure, the second stacked structure including at least one second conductive layer and at least one second dielectric layer, with each second conductive layer and each second dielectric layer alternately stacked.

[0008] As an optional technical solution, the surface of the first encapsulation layer facing the second stacked structure is a first flat surface, and the second stacked structure is disposed on the first flat surface.

[0009] As an optional technical solution, the first encapsulation layer includes a first sidewall protruding from the first flat surface toward the first surface; the first sidewall surrounds the periphery of the first stacked structure, and the first sidewall is connected to the first surface.

[0010] As an optional technical solution, it further includes a conduction column embedded in the first encapsulation layer, with opposite ends of the conduction column respectively connected to the first conductive layer and the second conductive layer.

[0011] As an optional technical solution, it further includes solder balls disposed on the surface of the second stacked structure away from the first encapsulation layer, and the solder balls are electrically connected to one of the second conductive layers in the second stacked structure.

[0012] As an optional technical solution, the number of layers of the first dielectric layer and the number of layers of the first conductive layer are respectively 2-3 layers.

[0013] As an alternative technical solution, it further includes: a third stacked structure and a second encapsulation layer; the second encapsulation layer is disposed on a side of the second stacked structure away from the first encapsulation layer, and the second encapsulation layer covers the second stacked structure; the third stacked structure is disposed on a surface of the second encapsulation layer away from the second stacked structure, and the third stacked structure includes at least one third dielectric layer and at least one third conductive layer, and each of the third dielectric layers and each of the third conductive layers are alternately stacked.

[0014] As an alternative technical solution, a surface of the second encapsulation layer facing the third stacked structure is a second flat surface, and the third stacked structure is disposed on the second flat surface.

[0015] As an alternative technical solution, each of the third conductive layers in the third stacked structure is electrically connected in sequence through vias in the third dielectric layer.

[0016] As an alternative technical solution, the second encapsulation layer includes second sidewalls, and the second sidewalls protrude from the second flat surface toward the first surface; the second sidewalls surround a periphery of the second stacked structure and are connected to the first surface.

[0017] As an alternative technical solution, after at least one first dielectric layer, at least one first conductive layer, at least one second dielectric layer, and at least one second conductive layer are stacked, they have a total film thickness, wherein the first encapsulation layer is disposed at 1 / 3 of the total film thickness, and the first encapsulation layer is stacked above the first dielectric layer or the first conductive layer.

[0018] As an alternative technical solution, each of the second conductive layers in the second stacked structure is electrically connected in sequence through vias in the second dielectric layer.

[0019] The present invention also provides a method for manufacturing a common mode inductor package structure, and the manufacturing method includes:

[0020] Providing a substrate, the substrate includes opposite first and second surfaces, and a dicing lane is provided on the first surface;

[0021] Forming at least one first dielectric layer and at least one first conductive layer on the first surface, and each of the first dielectric layers and each of the first conductive layers are alternately stacked, and at least one first dielectric layer and at least one first conductive layer form a first stacked structure;

[0022] Coating a first encapsulation material above the first stacked structure to form a first encapsulation layer, and the first encapsulation layer covers the first stacked structure and a part of the first surface exposed from the dicing lane;

[0023] Form at least one second dielectric layer and at least one second conductive layer on the first encapsulation layer, with each second dielectric layer and each second conductive layer stacked alternately, and at least one second dielectric layer and at least one second conductive layer constituting a second stacked structure; and

[0024] Cut along the dicing channel to obtain the common mode inductor package structure.

[0025] As an alternative technical solution, the step of providing the substrate further includes: forming an anti-warpage layer on the second surface of the substrate;

[0026] The step of cutting along the dicing channel to obtain the common mode inductor package structure further includes: peeling off the anti-warpage layer on the second surface and cutting along the dicing channel to obtain the common mode inductor package structure.

[0027] Compared with the prior art, the present invention provides a common mode inductor package structure and a manufacturing method. An encapsulation layer is provided between two stacked structures that jointly form a common mode inductor. After curing, the encapsulation layer has the advantages of high hardness and good dimensional stability. Therefore, by virtue of the flat surface provided by the encapsulation layer, the manufacturing difficulty of the multi-layer stacked structure can be reduced, the height fluctuations of each film layer in the multi-layer stacked structure can be improved, the flatness of the film layer can be enhanced, and the interference to signal transmission caused by the unevenness of the film layer can be overcome; and by covering the stacked structure with a flat layer, the delamination between dielectric layers in the stacked structure can be overcome, and the packaging yield can be improved.

[0028] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. Description of the Drawings

[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is a cross-sectional schematic diagram of an existing common mode inductor package structure.

[0031] Figure 2 It is a cross-sectional schematic diagram of the common mode inductor package structure provided in the first embodiment of the present invention.

[0032] Figure 3 It is a cross-sectional schematic diagram of the common mode inductor package structure provided in the second embodiment of the present invention.

[0033] Figure 4Flow chart of the manufacturing method of the common mode inductor packaging structure provided by the present invention.

[0034] Figure 5 Partial cross-sectional schematic diagram of the manufacturing process of the warpage prevention layer in the common mode inductor packaging structure provided by the present invention.

[0035] Figure 6 Partial cross-sectional schematic diagram of the manufacturing process of the first stacked structure in the common mode inductor packaging structure provided by the present invention.

[0036] Figure 7 Partial cross-sectional schematic diagram of the manufacturing of the conduction posts in the common mode inductor packaging structure provided by the present invention.

[0037] Figure 8 Partial cross-sectional schematic diagram of the manufacturing process of the first encapsulation layer in the common mode inductor packaging structure provided by the present invention.

[0038] Figure 9 Partial cross-sectional schematic diagram of the manufacturing process of the second stacked structure in the common mode inductor packaging structure provided by the present invention.

[0039] Figure 10 Partial cross-sectional schematic diagram of the manufacturing of the solder balls in the common mode inductor packaging structure provided by the present invention.

[0040] Figure 11 Partial cross-sectional schematic diagram of the peeling of the warpage prevention layer in the common mode inductor packaging structure provided by the present invention.

[0041] Figure 12 Partial cross-sectional schematic diagram of the common mode inductor packaging structure obtained by cutting the substrate and the first encapsulation layer in the common mode inductor packaging structure provided by the present invention.

[0042] Figure 13 Partial cross-sectional schematic diagram of the manufacturing process of the first encapsulation layer in the common mode inductor packaging structure provided by another embodiment of the present invention. Detailed implementation manners

[0043] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0044] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0045] The present invention provides a common mode inductor packaging structure, which includes a substrate and a first stacking structure, a first encapsulation layer, and a second stacking structure stacked on the first surface of the substrate. The first encapsulation layer covers the first stacking structure, and the second stacking structure is stacked on the first encapsulation layer. Among them, the first stacking structure includes at least one first conductive layer and at least one first dielectric layer, and each first conductive layer and each first dielectric layer are alternately laminated; the second stacking structure includes at least one second conductive layer and at least one second dielectric layer, and each second conductive layer and each second dielectric layer are alternately laminated. The first encapsulation layer is sandwiched between the first stacking structure and the second stacking structure, and the first encapsulation layer covers the first stacking structure. On the one hand, the first encapsulation layer can provide a flat surface, reduce the problem of height fluctuations of each film layer in each stacking structure, reduce the manufacturing difficulty of the stacking structure in the common mode inductor packaging structure, and reduce the interference of the common mode inductor packaging structure on the transmission of electrical signals; on the other hand, the first encapsulation layer covers the first stacking structure, and the edge of the first encapsulation layer protrudes from the edge of the first stacking structure and is connected to the first surface of the substrate, so that the first stacking structure is completely covered by the first encapsulation layer, thereby being able to overcome the delamination problem between the first dielectric layer in the first stacking structure and the first surface of the substrate, and improving the manufacturing yield of the common mode inductor packaging structure.

[0046] In addition, the first encapsulation layer is made of a resin material, which has lower brittleness compared to the substrate, such as a silicon substrate. Therefore, in the cutting process, the first encapsulation layer can absorb part of the stress and prevent the silicon wafer from chipping.

[0047] As Figure 2 shown, in the first embodiment of the present invention, a common mode inductor packaging structure 100 is provided, which includes a substrate 10, a first stacking structure 20, a first encapsulation layer 30, and a second stacking structure 40. The substrate 10 includes opposite first surface 11 (as Figure 5 shown) and second surface 12 (as Figure 5 shown); the first stacking structure 20 is disposed on the first surface 11, and the first stacking structure 20 includes at least one first dielectric layer 21 and at least one first conductive layer 22, and each first dielectric layer 21 and each first conductive layer 22 are alternately laminated; the first encapsulation layer 30 is disposed on the side of the first stacking structure 20 away from the substrate 10, and the first encapsulation layer 30 covers the first stacking structure 20; the second stacking structure 40 is disposed on the side of the first encapsulation layer 30 away from the first stacking structure 20, and the second stacking structure 40 includes at least one second dielectric layer 41 and at least one second conductive layer 42, and each second dielectric layer 41 and each second conductive layer 42 are alternately laminated.

[0048] In this embodiment, the surface 301 of the first encapsulation layer 30 facing the second stacked structure 40 is a first flat surface, and the second stacked structure 40 is disposed on the first flat surface.

[0049] The material of the first encapsulation layer 30 is, for example, selected from insulating resins. It covers the upper part of the first stacked structure 20 and provides the first flat surface, which helps to make the film layers of the second dielectric layer 41 and the second conductive layer 42 in the subsequently formed second stacked structure 40 relatively flat without obvious undulations. In addition, since the first stacked structure 20 and the second stacked structure 40 are separated by the first encapsulation layer 30, the influence of the manufacturing process of the second stacked structure 40 on the first dielectric layer 21 and the first conductive layer 22 in the first stacked structure 20 is reduced. Therefore, the film layers of the first dielectric layer 21 and the first conductive layer 22 in the first stacked structure 20 are also relatively flat.

[0050] Continue to refer to Figure 2 , the first encapsulation layer 30 includes a first sidewall 302 that protrudes from the first flat surface toward the first surface 11 (as Figure 5 shown); the first sidewall 302 surrounds the periphery of the first stacked structure 20, and the first sidewall 302 is connected to the first surface 11. Since the first sidewall 302 is connected to the first surface 11, it improves the connection stability between the first stacked structure 20 and the first surface 11 and overcomes the delamination problems between the first dielectric layers 21 in the first stacked structure 20 and between the first dielectric layer 21 and the substrate 11.

[0051] Continue to refer to Figure 2 , the first stacked structure 20 includes two layers of first dielectric layers 21 and two layers of first conductive layers 22, where the first dielectric layer 21 is disposed on the first surface 11 (as Figure 5 shown); the first conductive layer 22 is stacked on the first dielectric layer 21; then the first dielectric layer 21 and the first conductive layer 22 are stacked in sequence; at this time, the first encapsulation layer 30 is, for example, disposed above the first conductive layer 22. The second stacked structure 40 includes three layers of second dielectric layers 41 and three layers of second conductive layers 42, where the second dielectric layer 41 is disposed on the surface 301 of the first encapsulation layer 30, and the second conductive layer 42 is stacked on the second dielectric layer 41; then the second dielectric layer 41 and the second conductive layer 42 are stacked in sequence.

[0052] It should be noted that the surface 301 of the first encapsulation layer 30 is located between the first conductive layer 22 and the second dielectric layer 41, but not limited thereto. In other embodiments of the present invention, the surface of the first encapsulation layer may also be located between the first dielectric layer and the second dielectric layer, or between the first dielectric layer and the second conductive layer.

[0053] In a preferred embodiment, in the common-mode inductor package structure 100, the total thickness of the film layers after stacking the first dielectric layer 21, the first conductive layer 22, the second dielectric layer 41, and the second conductive layer 42 is D (not shown), wherein the first encapsulation layer 30 is disposed at 1 / 3 of the total thickness D of the film layers.

[0054] In addition, in other embodiments of the present invention, if the total thickness of the film layers of the common-mode inductor package structure is relatively thick, multiple encapsulation layers can also be provided.

[0055] As Figure 2 shown, in the common-mode inductor package structure 100, in the first stacking structure 20, the two first conductive layers 22 can be electrically connected or non-electrically connected, which can be determined according to the actual functional requirements of the common-mode inductor package. In the second stacking structure 40, the three second conductive layers 42 are sequentially electrically connected through vias on the second dielectric layer 41.

[0056] As Figure 2 shown, a conduction post 31 is embedded in the first encapsulation layer 30, and the opposite ends of the conduction post 31 are respectively connected to the first conductive layer 22 and the second conductive layer 42, so that the first stacking structure 20 and the second stacking structure 40 are electrically connected to each other.

[0057] In the present invention, for the convenience of description, the common-mode inductor package structure 100 is divided into a first stacking structure 20 and a second stacking structure 40 with the first encapsulation layer 30 as the separator. It should be noted that in an actual product, the first stacking structure 20 and the second stacking structure 40 together form a common-mode inductor. In addition, the first conductive layer 22 and the second conductive layer 42 are the same or similar in function and material; the first dielectric layer 21 and the second dielectric layer 41 are also the same or similar in function and material.

[0058] In a preferred embodiment, the first conductive layer 22 and the second conductive layer 42 are respectively metal redistribution layers, and the metal redistribution layers are, for example, spiral metal coils in a top view; the first dielectric layer 21 and the second dielectric layer 41 are respectively polyimide layers.

[0059] Continuing to refer to Figure 2 , the uppermost second conductive layer 42 in the second stacking structure 40 is electrically connected to the solder ball 50. In other embodiments of the present invention, when the number of solder balls is multiple, some solder balls can also be electrically connected to the first conductive layer in the first stacking structure.

[0060] As Figure 3 shown, in the second embodiment of the present invention, a common-mode inductor package structure 200 is also provided, and the difference between it and the common-mode inductor structure 100 is that the common-mode inductor package structure 200 further includes a third stacking structure 70 and a second encapsulation layer 60.

[0061] In addition,Figure 3 in the Figure 2 The same reference numerals as those in the

[0062] The second encapsulation layer 60 is disposed on a side of the second stacked structure 40 away from the first encapsulation layer 30 and covers the second stacked structure 40 and the first encapsulation layer; the third stacked structure 70 is disposed on a surface of the second encapsulation layer 60 on a side away from the second stacked structure 40; wherein, the third stacked structure 70 includes at least one third dielectric layer 71 and at least one third conductive layer 72, and each third dielectric layer 71 and each third conductive layer 72 are alternately arranged.

[0063] A surface 601 of the second encapsulation layer 60 facing the third stacked structure 70 is a second flat surface, and the third stacked structure 70 is disposed on the second flat surface.

[0064] The material of the second encapsulation layer 60 is, for example, selected from insulating resins, which covers the second stacked structure 40 and provides the second flat surface, helping to make the film layers of the third dielectric layer 71 and the third conductive layer 72 in the subsequently formed third stacked structure 70 relatively flat without obvious undulations. In addition, since the second stacked structure 40 and the third stacked structure 70 are separated by the second encapsulation layer 60, the influence of the manufacturing process of the third stacked structure 70 on the second dielectric layer 41 and the second conductive layer 42 in the second stacked structure 40 is reduced. Therefore, the film layers of the second dielectric layer 41 and the second conductive layer 42 in the second stacked structure 40 are also relatively flat.

[0065] Continue to refer to Figure 3 , the second encapsulation layer 60 includes a second sidewall 602, and the second sidewall 602 protrudes from the second flat surface toward the first surface 11 (as Figure 5 shown); the second sidewall 602 surrounds the periphery of the second stacked structure 40 and the outside of the first encapsulation layer 30, and the second sidewall 602 is connected to the first surface 11. Among them, the second sidewall 602 is located outside the first sidewall 302. Since the second sidewall 602 is connected to the first surface 11, it overcomes the delamination problem between the second dielectric layers 41 in the upper part of the second stacked structure 40.

[0066] In the third stacked structure 70, three layers of the third conductive layers 72 are electrically connected in sequence through vias in the third dielectric layer 71.

[0067] As Figure 3 shown, a via plug 61 is buried in the second encapsulation layer 60, and opposite ends of the via plug 61 are respectively connected to the second conductive layer 42 and the third conductive layer 72 to electrically conduct the second stacked structure 40 and the third stacked structure 70 to each other.

[0068] Continue to refer to Figure 3, the topmost third conductive layer 72 in the third stacked structure 70 is electrically connected to the solder ball 50.

[0069] As can be seen from the above, in the common mode inductor package structure provided by the present invention, an encapsulation layer is provided between two stacked structures that jointly form a common mode inductor. Since the encapsulation layer has high hardness and good dimensional stability after curing, the process difficulty of the multi-layer stacked structure can be reduced by means of the flat surface provided by the encapsulation layer, the undulation of each film layer in the multi-layer stacked structure can be improved, the flatness of the film layer can be enhanced, and the interference to signal transmission caused by the unevenness of the film layer can be overcome; and by covering the stacked structure with the flat layer, the delamination between the dielectric layers in the stacked structure can be overcome, and the packaging yield can be improved.

[0070] As Figure 4 shown, the present invention also provides a manufacturing method 1000 of a common mode inductor package structure, which includes:

[0071] Providing a substrate, the substrate includes opposite first and second surfaces, and a scribe line is provided on the first surface;

[0072] Forming at least one first dielectric layer and at least one first conductive layer on the first surface, each first dielectric layer and each first conductive layer are alternately stacked, and each first dielectric layer and each first conductive layer are alternately stacked to form a first stacked structure;

[0073] Coating a first encapsulation material onto the first stacked structure to form a first encapsulation layer, the first encapsulation layer covering the first stacked structure and the first surface exposed from the scribe line;

[0074] Forming at least one second dielectric layer and at least one second conductive layer on the flat surface of the first encapsulation layer, each second dielectric layer and each second conductive layer are alternately stacked, and at least one second dielectric layer and at least one second conductive layer form a second stacked structure; and

[0075] Cutting along the scribe line to obtain the common mode inductor package structure.

[0076] In a preferred embodiment, the step of providing the substrate further includes: forming an anti-warpage layer on the second surface of the substrate.

[0077] In a preferred embodiment, the step of cutting along the scribe line to obtain the common mode inductor package structure further includes: peeling off the anti-warpage layer on the second surface and cutting along the scribe line to obtain the common mode inductor package structure.

[0078] Hereinafter, taking the common mode package structure 100 shown in Figure 2 as an example, in combination with Figures 5 to 13 it will be described in detail Figure 4 the manufacturing process of the manufacturing method 1000 in

[0079] AsFigure 5 As shown, a substrate 10 is provided, such as a wafer-level silicon substrate, which includes opposite first surface 11 and second surface 12; an anti-warpage layer 80 is fabricated on the second surface 12.

[0080] The anti-warpage layer 80 can be formed by coating a polymer material onto the second surface 12 and curing the polymer material to form a polymer anti-warpage layer; alternatively, the anti-warpage layer 80 can be formed by evaporating a metal material onto the second surface 12 to form a metal anti-warpage layer.

[0081] In a preferred embodiment, the anti-warpage layer 80 can cause the edge of the substrate 10 to bend toward the second surface 12 side (from a Figure 5 depicted perspective, the edge of the substrate 10 bends downward), thereby balancing the upward warping of the substrate 10 during subsequent processes and avoiding the inability to perform wafer dicing due to warping problems.

[0082] As Figure 6 shown, a plurality of first stacked structures 20 are fabricated on the first surface 11 of the wafer-level silicon substrate. Among them, Figure 6 only two first stacked structures 20 are shown, but not limited thereto.

[0083] As Figure 5 and Figure 6 shown, on the first surface 11, a first dielectric layer 21 and a first conductive layer 22 are alternately stacked in sequence. Among them, the multiple alternately stacked first dielectric layers 21 and first conductive layers 22 constitute the first stacked structure 20.

[0084] Continuing to refer to as Figure 5 and Figure 6 , the scribing lane 10a on the first surface 11 is located in the recess 20a between any two adjacent first stacked structures 20. In other words, the first dielectric layer 21 and the first conductive layer 22 in the first stacked structure 20 are patterned in the region corresponding to the scribing lane 10a, and due to the mutual lamination of the dielectric layer and the conductive layer, a recess 20a is formed between adjacent first stacked structures 20.

[0085] As Figure 7 shown, a via pillar 31 is fabricated on the uppermost first conductive layer 22 of the first stacked structure 20. The via pillar 31 is made of, for example, a copper-containing metal material.

[0086] As Figure 5 , Figure 7 and Figure 8As shown, a first encapsulation material is coated above a first stacked structure 20 on a first surface 11. The first encapsulation material covers the first stacked structure 20, fills depressions 20a between adjacent first stacked structures 20, and covers a portion of the first surface 11 exposed from the depressions 20a. The first encapsulation material is cured to form a first encapsulation layer 30.

[0087] The surface 301 of the first encapsulation layer 30 is thinned to form a first flat surface, wherein the upper ends of the via posts 31 are exposed from the first flat surface.

[0088] In this embodiment, the method of thinning the upper surface of the first encapsulation layer 30 includes, but is not limited to, grinding or lithography.

[0089] As Figure 9 shown, a second dielectric layer 41 and a second conductive layer 42 are alternately stacked in sequence on the first flat surface of the first encapsulation layer 30. Among them, the multi-layer alternately stacked second dielectric layer 41 and second conductive layer 42 constitute a second stacked structure 40.

[0090] As Figure 10 shown, solder balls 50 are fabricated on the uppermost second conductive layer 42 of the second stacked structure 40.

[0091] As Figure 10 and Figure 11 shown, the anti-warpage layer 80 on the second surface 12 is peeled off.

[0092] As Figure 1 and Figure 12 shown, cutting is performed along the cutting channel 10a to obtain a common-mode inductor package structure.

[0093] As Figure 13 shown, in another embodiment of the present invention, a groove 13 may also be provided in the cutting channel 10a' on the first surface 11' of the substrate 10'. Among them, a part of the first encapsulation layer 30' is embedded in the groove 13 to increase the bonding strength between the first encapsulation layer 30' and the substrate 10'. In addition, Figure 13 the same reference numerals in Figure 8 represent the same components and have similar functions, and will not be described in detail again.

[0094] In summary, the present invention provides a common-mode inductor package structure and a manufacturing method. An encapsulation layer is provided between two stacked structures that jointly form a common-mode inductor. Since the encapsulation layer has high hardness and good dimensional stability after curing, the process difficulty of the multi-layer stacked structure can be reduced by means of the flat surface provided by the encapsulation layer, the height fluctuations of each film layer in the multi-layer stacked structure can be improved, the flatness of the film layer can be enhanced, and the interference to signal transmission caused by the unevenness of the film layer can be overcome; and by covering the stacked structure with a flat layer, delamination between dielectric layers in the stacked structure can be overcome, and the packaging yield can be improved.

[0095] The present invention has been described by the above related embodiments. However, the above embodiments are only examples for implementing the present invention. In addition, the technical features involved in different embodiments of the present invention described above can be combined with each other as long as they do not conflict with each other. It must be pointed out that the present invention can also have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A common-mode inductor package structure, characterized in that, The common-mode inductor packaging structure includes: a substrate, the substrate including opposite first and second surfaces; a first stacked structure disposed on the first surface, the first stacked structure including at least one first conductive layer and at least one first dielectric layer, each of the first conductive layers and each of the first dielectric layers being alternately stacked; a first encapsulation layer disposed on the surface of the first stacked structure away from the substrate, the first encapsulation layer covering the first stacked structure; and a second stacked structure disposed on the surface of the first encapsulation layer away from the first stacked structure, the second stacked structure including at least one second conductive layer and at least one second dielectric layer, each of the second conductive layers and each of the second dielectric layers being alternately stacked; a first flat surface on the side of the first encapsulation layer facing the second stacked structure, the second stacked structure being disposed on the first flat surface.

2. The common-mode inductor packaging structure according to claim 1, wherein, The first encapsulation layer includes a first sidewall protruding from the first flat surface toward the first surface; the first sidewall surrounds the periphery of the first stacked structure, and the first sidewall is connected to the first surface.

3. The common-mode inductor package structure according to claim 1, wherein It further includes a conduction post embedded in the first encapsulation layer, opposite ends of the conduction post being respectively connected to the first conductive layer and the second conductive layer.

4. The common-mode inductor package structure according to claim 2 or 3, characterized in that, It further includes solder balls disposed on the surface of the second stacked structure away from the first encapsulation layer, the solder balls being electrically connected to one of the second conductive layers in the second stacked structure.

5. The common mode inductor package structure according to claim 1, characterized in that, The number of layers of the first dielectric layer and the number of layers of the first conductive layer are respectively 2 - 3 layers.

6. The common mode inductor package structure according to claim 1, characterized in that, It further includes: a third stacked structure and a second encapsulation layer; the second encapsulation layer is disposed on the side of the second stacked structure away from the first encapsulation layer, the second encapsulation layer covering the second stacked structure; the third stacked structure is disposed on the surface of the second encapsulation layer away from the second stacked structure, the third stacked structure including at least one third dielectric layer and at least one third conductive layer, each of the third dielectric layers and each of the third conductive layers being alternately stacked; a second flat surface on the side of the second encapsulation layer facing the third stacked structure, the third stacked structure being disposed on the second flat surface.

7. The common-mode inductor package structure according to claim 6, characterized in that, The second encapsulation layer includes a second sidewall protruding from the second flat surface toward the first surface; the second sidewall surrounds the periphery of the second stacked structure and is connected to the first surface.

8. The common mode inductor package structure according to claim 6, wherein, Each of the third conductive layers in the third stacked structure is electrically connected in sequence through vias in the third dielectric layer.

9. The common-mode inductor package structure according to claim 1, wherein At least one first dielectric layer, at least one first conductive layer, at least one second dielectric layer, and at least one second conductive layer are stacked to have a total film thickness, wherein the first encapsulation layer is disposed at 1 / 3 of the total film thickness, and the first encapsulation layer is stacked above the first dielectric layer or the first conductive layer.

10. The common-mode inductor package structure according to claim 1, characterized in that, Each of the second conductive layers in the second stacked structure is electrically connected in sequence through vias in the second dielectric layer.

11. A manufacturing method of a common-mode inductor packaging structure, characterized in that, The manufacturing method includes: providing a substrate, the substrate including opposite first and second surfaces, with a dicing channel provided on the first surface; forming at least one first dielectric layer and at least one first conductive layer on the first surface, each of the first dielectric layers and each of the first conductive layers being alternately stacked, at least one of the first dielectric layers and at least one of the first conductive layers constituting a first stacked structure; coating a first encapsulation material above the first stacked structure to form a first encapsulation layer, the first encapsulation layer covering the first stacked structure and a part of the first surface exposed from the dicing channel; forming at least one second dielectric layer and at least one second conductive layer on the first encapsulation layer, each of the second dielectric layers and each of the second conductive layers being alternately stacked, at least one of the second dielectric layers and at least one of the second conductive layers constituting a second stacked structure, a surface of the first encapsulation layer facing the second stacked structure side being a first flat surface, and the second stacked structure being disposed on the first flat surface; and cutting along the dicing channel to obtain the common-mode inductor package structure.

12. The manufacturing method of the common-mode inductor package structure according to claim 11, wherein the step of providing the substrate further includes: forming an anti-warpage layer on the second surface of the substrate; the step of cutting along the dicing channel to obtain the common-mode inductor package structure further includes: peeling off the anti-warpage layer on the second surface and cutting along the dicing channel to obtain the common-mode inductor package structure.

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