Packaging structure and electronic devices

Abstract

The embodiment of the present application provides a packaging structure and an electronic device, wherein the first conductive layer of the packaging structure is connected to the first substrate through a first conductive member located outside the chip body, and a slot is provided on the chip body, a second conductive member is provided in the slot, and the first conductive layer is connected to the first substrate through the second conductive member. By providing two parallel channels between the first conductive layer and the substrate to achieve grounding, the grounding parasitic parameters are reduced, the power consumption is reduced, and thus the output efficiency of the electronic device is improved to a certain extent.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a packaging structure and an electronic device. Background Art

[0002] Base stations are key equipment for wireless communications and are generally composed of baseband chips, RF power amplifiers (PAs), filters, heat sinks, power supplies, and other components. Their main function is to process control signaling, voice calls, and data services from the core network through baseband and RF processing, and then send them to the antenna for transmission to achieve wireless coverage. Among them, the PA (RF power amplifier) ​​is a key chip in base stations, amplifying milliwatt (mW)-level RF power to hundreds of watts. It is one of the chips with the highest power consumption in base stations and, to a certain extent, determines the efficiency and power consumption of base stations. Therefore, improving PA efficiency and reducing its power consumption are long-standing requirements for RF power amplifiers in base stations and are also important research directions in the industry.

[0003] In the prior art, the main packaging form of PA (radio frequency power amplifier) ​​is to bond the chip to a first substrate. The input and output ends of the chip are then connected to pins via bonding wires. The chip is then grounded via the bonding wires to conduct heat away from the chip as quickly as possible, reducing the temperature of the chip surface. The chip is generally a laterally-diffused metal-oxide semiconductor (LDMOS) or gallium nitride (GaN), and the first substrate is generally a metal with a thermal expansion coefficient (CTE) that matches the chip, such as CuMoCu, WCu, Cu, diamond Cu, and other materials.

[0004] However, the above-mentioned packaging structure has high parasitic parameters such as parasitic inductance and parasitic resistance, which will increase the power consumption of the PA and thus affect the output efficiency of the PA. Summary of the Invention

[0005] The embodiments of the present application provide a packaging structure and an electronic device, which can reduce parasitic parameters and power consumption, thereby improving the output efficiency of the electronic device to a certain extent.

[0006] A first aspect of an embodiment of the present application provides a packaging structure, which includes: a first substrate and a chip arranged on the first substrate; the chip includes: a chip body and a first conductive layer located above the chip body, the first conductive layer and the first substrate are connected through a first conductive member; a slot is also provided on the chip body, a second conductive member is provided in the slot, and the first conductive layer is connected to the first substrate through the second conductive member.

[0007] In the package structure provided by the present application, a first conductive layer is electrically connected to a first substrate via a first conductive member located outside the chip body. Furthermore, a slot is provided in the chip body, and a second conductive member is located within the slot. The first conductive layer is electrically connected to the first substrate via the second conductive member. By providing two parallel paths between the first conductive layer and the substrate for grounding, grounding parasitic parameters are reduced, power consumption is minimized, and thus the output efficiency of the electronic device is improved to a certain extent.

[0008] In a possible implementation, the device further includes: a second conductive layer; the second conductive layer is located at least between the chip body and the first substrate, and the second conductive layer is electrically connected to the first conductive layer and the first substrate respectively.

[0009] By arranging a second conductive layer between the chip body and the first substrate, and the second conductive layer being electrically connected to the first conductive layer and the first substrate respectively, the electrical contact area between the chip and the first substrate is increased, thereby further reducing the ground parasitic parameters.

[0010] In one possible implementation, the second conductive layer extends toward the slot near the slot to form an extended conductive layer, one end of the extended conductive layer is electrically connected to the first conductive layer, and the second conductive layer is electrically connected to the first conductive layer through the extended conductive layer.

[0011] An extended conductive layer is formed by extending the second conductive layer toward the slot near the slot, and one end of the extended conductive layer is electrically connected to the first conductive layer, thereby increasing the conductive path between the first conductive layer and the second conductive layer and further achieving via grounding.

[0012] In a possible implementation, the thickness of the extended conductive layer is greater than 0.1 μm. The thicker the extended conductive layer, the stronger the flow capacity of the via hole.

[0013] In a possible implementation, the second conductive layer and the extended conductive layer are made of any one or more of gold, copper, titanium, tungsten, nickel, or vanadium.

[0014] In a possible implementation manner, the second conductive layer is in electrical contact with the second conductive member, and the second conductive layer is electrically connected to the first conductive layer through the second conductive member.

[0015] The second conductive layer is in electrical contact with the second conductive member, so that the second conductive layer can be electrically connected to the first conductive layer through the second conductive member. In this way, the channel formed by the first conductive layer and the substrate is grounded through the second conductive member, which reduces the grounding parasitic parameters and the power consumption, thereby improving the output efficiency of the electronic device to a certain extent.

[0016] In a possible implementation manner, the first conductive member is a bonding wire.

[0017] In a possible implementation manner, the second conductive member is a bonding wire.

[0018] In a possible implementation, the second conductive member is a metal layer disposed in the slot.

[0019] In a possible implementation, at least one pad portion is provided on the first conductive layer, one end of the first conductive member is electrically connected to the pad portion, and the other end of the first conductive member is electrically connected to the first substrate.

[0020] By providing a pad portion on the first conductive layer, one end of the first conductive member is electrically connected to the pad portion on the first conductive layer, and the other end of the first conductive member is electrically connected to the first substrate, thereby achieving conduction between the first conductive layer and the substrate.

[0021] In a possible implementation, a bonding area is provided on the first substrate, and two ends of the first conductive member are electrically connected to the bonding area and the pad portion, respectively.

[0022] By providing a bonding area on the first substrate, one end of the first conductive member is electrically connected to the bonding area on the first substrate, and the other end of the first conductive member is electrically connected to the pad portion on the first conductive layer, thereby achieving conduction between the first conductive layer and the substrate.

[0023] In one possible implementation, each of the pad portions includes a first pad area and a second pad area; the projection of the slot in the vertical direction is located within the first pad area, and the two ends of the first conductive member are electrically connected to the second pad area and the bonding area, respectively.

[0024] The pad portion includes a first pad area and a second pad area, the projection of the slot in the vertical direction is located in the first pad area, and the two ends of the first conductive member are electrically connected to the second pad area and the bonding area respectively, that is, the first pad area is used to achieve conduction between the first conductive layer and the substrate through the second conductive member in the slot, and the second pad area is used to achieve conduction between the first conductive layer and the substrate through the first conductive member. The same pad portion can achieve different conduction channels through two different pad areas.

[0025] In one possible implementation, the number of the pad portions is at least two; the projection of the slot in the vertical direction is located within the first pad portion of the at least two pad portions, and the two ends of the first conductive member are respectively electrically connected to the second pad portion of the at least two pad portions and the bonding area.

[0026] By setting the number of pad portions to at least two, the projection of the slot in the vertical direction is located in one of the at least two pad portions, and the two ends of the first conductive member are electrically connected to the other of the at least two pad portions and the bonding area respectively. In this way, one of the at least two pad portions is used to achieve conduction between the first conductive layer and the substrate through the second conductive member in the slot, and the other of the at least two pad portions is used to achieve conduction between the first conductive layer and the substrate through the first conductive member. That is to say, the at least two pad portions on the first conductive layer are set to achieve different functions, that is, different conduction channels are achieved through two different pad portions.

[0027] In a possible implementation, the inner diameter of the slot is 10-150 μm.

[0028] In a possible implementation, the diameter of the bonding wire is greater than 25 μm. The larger the diameter of the bonding wire, the greater the current flow capacity.

[0029] In a possible implementation, the first substrate is further provided with pins, and the input end and the output end of the chip are electrically connected to the pins through a third conductive member respectively; and the pins are electrically connected to an external device.

[0030] By providing pins electrically connected to external devices on the first substrate, and electrically connecting the pins to the input and output ends of the chip, signal conduction between the chip on the first substrate and the external devices can be achieved.

[0031] In a possible implementation, the device further includes an insulating layer located between the pins and the first substrate. The insulating layer is used to isolate the first substrate from the pins to prevent electrical connection between the first substrate and the pins.

[0032] In a possible implementation, the third conductive member is a bonding wire.

[0033] In a possible implementation, the input end and the output end of the chip are electrically connected to the second substrate of the external device through a third conductive member.

[0034] By electrically connecting the input and output terminals of the chip to the second substrate of the external device respectively, signal conduction between the chip located on the first substrate and the external device located on the second substrate can be achieved.

[0035] In one possible implementation, the device further includes an adhesive layer positioned between the chip and the first substrate, and the adhesive layer is made of a conductive material. The adhesive layer is used to bond the chip and the first substrate to prevent separation between the chip and the first substrate. Furthermore, the conductive material of the adhesive layer facilitates current conduction.

[0036] In a possible implementation, the adhesive layer is any one or more of a gold-tin alloy, a gold-silicon alloy, a nanosilver material, or a silver paste.

[0037] A second aspect of an embodiment of the present application provides an electronic device, comprising at least: the packaging structure described above.

[0038] An electronic device provided in an embodiment of the present application includes at least a packaging structure, wherein a first conductive layer of the packaging structure is electrically connected to a first substrate via a first conductive member located outside a chip body. Furthermore, a slot is provided in the chip body, and a second conductive member is located within the slot. The first conductive layer is electrically connected to the first substrate via the second conductive member. By providing two parallel paths between the first conductive layer and the substrate for grounding, grounding parasitic parameters are reduced, power consumption is reduced, and thus, the output efficiency of the electronic device is improved to a certain extent.

[0039] These and other aspects, implementations, and advantages of the exemplary embodiments will become apparent from the embodiments described below in conjunction with the accompanying drawings. However, it should be understood that the description and drawings are for illustration only and do not constitute a definition of limitations on the embodiments of the present application, as detailed in the appended claims. Other aspects and advantages of the embodiments of the present application will be set forth in the following description, and in part will be apparent from the description or learned through practice of the embodiments of the present application. In addition, various aspects and advantages of the embodiments of the present application may be realized and obtained by the means and combinations particularly pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0041] Figure 2 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0042] Figure 3A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0043] Figure 4 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0044] Figure 5 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0045] Figure 6 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0046] Figure 7 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0047] Figure 8 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0048] Figure 9 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0049] Figure 10 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0050] Figure 11 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0051] Figure 12 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0052] Figure 13 A cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0053] Figure 14 A top view of a packaging structure provided in one embodiment of the present application;

[0054] Figure 15 A top view of a packaging structure provided in one embodiment of the present application;

[0055] Figure 16 A top view of a packaging structure provided in one embodiment of the present application;

[0056] Figure 17 A top view of a packaging structure provided in one embodiment of the present application;

[0057] Figure 18 A curve diagram showing changes in efficiency versus output power when a packaging structure in the prior art is applied to an electronic device;

[0058] Figure 19 This is a curve diagram showing how the efficiency of the packaging structure provided in an embodiment of the present application changes with the output power value when applied to an electronic device.

[0059] Description of reference numerals:

[0060] 100-packaging structure; 1-chip; 10-chip body; 101-slot; 20-first conductive layer; 201-pad portion; 2011-first pad area; 2012-second pad area; 2013-first pad portion; 2014-second pad portion; 202-source; 203-drain; 204-gate; 30-first conductive member; 40-second conductive member; 50-second conductive layer; 501-extended conductive layer; 60-third conductive member; 2-first substrate; 21-pin; 3-insulating layer; 4-second substrate; 5-adhesive layer. DETAILED DESCRIPTION

[0061] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application. The implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0062] Chips are the core structure of semiconductor devices. Currently, the development trend of semiconductor devices is to increase output power and reduce size. High output efficiency can improve the signal coverage area of ​​semiconductor devices, while small size facilitates installation. However, the pursuit of high-quality semiconductor devices has also further increased the requirements for chips, requiring increasingly higher chip output efficiency. The output efficiency of a chip is closely related to its operating junction temperature, which is determined by its thermal resistance and power consumption. Therefore, reducing power consumption and improving output efficiency are long-standing requirements for chips and semiconductor devices, and are also important research directions in the industry.

[0063] In the prior art, the chip is typically bonded to a substrate (or flange), and then the chip's input and output terminals are connected to the pins of external devices via bonding wires. The signal terminal is grounded via the bonding wires to conduct heat away from the chip as quickly as possible, reducing the chip surface temperature. However, since the parasitic parameters of the bonding wires themselves (parasitic parameters include parasitic inductance parameters, parasitic resistance parameters, etc.) are relatively high, generally reaching 0.1 to 0.5 nH or more, using bonding wires for grounding will increase power consumption, thereby affecting the chip's output power and further worsening the device's operating temperature. Alternatively, in the prior art, vias are provided under the chip's source to conduct heat away from the chip, reduce the chip surface temperature, and improve heat dissipation performance. However, in actual applications, when vias are provided under the active area, the number that can be provided is limited due to area restrictions, and the parasitic parameters are still relatively high. For example, when the chip body is 100 μm thick and the metal plating thickness in the via is 5 μm, the parasitic inductance parameter of a single via can reach 0.2 nH or more. Moreover, the current via process is still immature and easily leads to reliability issues caused by production and market batches, such as via metal delamination and perforation.

[0064] Based on this, embodiments of the present application provide a packaging structure in which, on the one hand, a first conductive layer is electrically connected to a first substrate via a first conductive member located outside the chip body. On the other hand, a slot is provided in the chip body, and a second conductive member is located within the slot. The first conductive layer is electrically connected to the first substrate via the second conductive member. By providing two parallel grounding paths, parasitic grounding parameters are reduced, power consumption is reduced, and thus, the output efficiency of the electronic device is improved to a certain extent.

[0065] The specific structure of the packaging structure is introduced below with reference to the accompanying drawings.

[0066] Example 1

[0067] Reference Figure 1 or Figure 2 As shown, an embodiment of the present application provides a packaging structure 100, which may include: a first substrate 2 and a chip 1 arranged on the first substrate 2, wherein the chip 1 may include: a chip body 10 and a first conductive layer 20 located above the chip body 10. In an embodiment of the present application, two channels are formed between the first conductive layer 20 and the first substrate 2, one of which is: the first conductive layer 20 and the first substrate 2 are connected through the first conductive member 30, and the other channel is: a slot 101 is opened on the chip body 10, and a second conductive member 40 is provided in the slot 101, and the first conductive layer 20 is connected to the first substrate 2 through the second conductive member 40.

[0068] By providing two parallel paths between the first conductive layer 20 and the substrate for grounding, grounding parasitic parameters (including parasitic inductance and resistance) are reduced, thereby lowering power consumption and, to a certain extent, improving the output efficiency of the electronic device. Furthermore, reliability issues such as via metal delamination and perforation can be reduced or mitigated.

[0069] It should be noted that if the distance L1 between the connection point of the first conductive member 30 on the first conductive layer 20 and the projection of the slot 101 of the chip body 10 on the first conductive layer 20 (see Figure 1 If the distance L1 between the connection point of the first conductive member 30 on the first conductive layer 20 and the projection of the slot 101 of the chip body 10 on the first conductive layer 20 is not too large, the specific distance L1 can be flexibly set according to the size of the chip 1 in the actual application scenario, and the embodiment of the present application does not limit this.

[0070] In addition, in the embodiment of the present application, the first conductive member 30 may be a bonding wire. Figure 1 or Figure 2 As shown, the first conductive layer 20 is electrically connected to the first substrate 2 via bonding wires located outside the chip body 10 .

[0071] In the embodiment of the present application, the configuration of the second conductive member 40 includes but is not limited to the following two possible implementations:

[0072] One possible implementation is: Figure 1 As shown, the second conductive member 40 is a bonding wire. Specifically, a slot 101 is opened on the chip body 10, and a bonding wire is arranged in the slot 101. The first conductive layer 20 is connected to the first substrate 2 through the bonding wire.

[0073] Another possible implementation is: Figure 2 As shown, the second conductive member 40 is a metal layer disposed in the slot 101. Specifically, the chip body 10 is provided with a slot 101, and a metal layer is disposed in the slot 101. The first conductive layer 20 is connected to the first substrate 2 through the metal layer.

[0074] It's important to note that bonding wire is a core material used in semiconductor packaging. It connects pins to silicon wafers and transmits electrical signals, making it an indispensable core material in semiconductor production. Specifically, bonding wire can be categorized by material: gold bonding wire, silver bonding wire, copper bonding wire, and aluminum bonding wire. Gold bonding wire is an inner lead material with excellent electrical, thermal, and mechanical properties, as well as chemical stability. It is primarily used as a key semiconductor packaging material (bonding wire, frame, molding compound, solder balls, high-density packaging substrates, conductive adhesives, etc.). It serves as a signal connection in PA packaging, connecting the chip surface electrodes to the pins. When current is applied, it flows through the gold wire into the chip, enabling operation. Copper bonding wire has emerged in the industry over the past two years as an alternative to traditional gold wire. Due to the rising price of gold over the past two years, the price of gold wire used for packaging has also increased. At the same time, product prices have continued to decline. Consequently, the use of copper alloy wire, a lower-cost alternative, has gradually increased.

[0075] In addition, when the second conductive member 40 is a metal layer disposed in the slot 101, the metal layer may be disposed in the following ways, but is not limited to:

[0076] The first possible implementation is: Figure 2 As shown, the metal layer is located in the slot 101 of the chip body 10 , one end of the metal layer is electrically connected to the first conductive layer 20 , and the other end of the metal layer is electrically connected to the first substrate 2 .

[0077] The second possible implementation is: Figure 3As shown, the metal layer is located on the slot wall of the slot hole 101 of the chip body 10 , one end of the metal layer is electrically connected to the first conductive layer 20 , and the other end of the metal layer is electrically connected to the first substrate 2 .

[0078] The third possible implementation is: Figure 4 As shown, a metal layer is provided inside the slot 101 of the chip body 10 and on the slot wall of the slot 101 . One end of the metal layer is electrically connected to the first conductive layer 20 , and the other end of the metal layer is electrically connected to the first substrate 2 .

[0079] The fourth possible implementation is: refer to Figure 5 As shown, the metal layer is filled in the slot 101 of the chip body 10, that is, the entire slot 101 of the chip body 10 has a metal layer, one end of the metal layer is electrically connected to the first conductive layer 20, and the other end of the metal layer is electrically connected to the first substrate 2.

[0080] In one possible implementation, the metal layer may be formed within the slot 101 of the chip body 10 in multiple steps. For example, a layer of metal, such as gold or titanium, may be first sputtered onto the inner wall of the slot 101, followed by electroplating of gold or copper onto the sputtered metal to form the metal layer. It should be noted that the thickness of a sputtered metal layer is typically in the nanometer range, while the thickness of an electroplated metal layer is typically in the micrometer range.

[0081] As an optional implementation, Figure 1 As shown, the inner diameter R1 of the slot 101 can be 10-150 μm. For example, the inner diameter R1 of the slot 101 can be 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, etc., which is not limited to the above examples in the present application.

[0082] As an optional implementation, the diameter of the bonding wire (the first conductive member 30 or the second conductive member 40) may be greater than 25 μm. The larger the diameter of the bonding wire, the greater the current carrying capacity.

[0083] In addition, it should be noted that the first conductive layer 20 in the embodiment of the present application may include multiple transistors disposed above the chip body 10, metal wiring connecting the transistors together, and dielectric layers between the metal wiring layers. In other words, the first conductive layer 20 may specifically include multiple conductive layers (generally made of metal, such as gold, copper, aluminum, etc.) and dielectric layers located between the conductive layers, wherein the dielectric layers are used to isolate the conductive layers.

[0084] These transistors are used for detection, rectification, amplification, switching, voltage regulation, signal modulation, and many other functions. As a variable switch, they control the outgoing current based on the input voltage. Therefore, transistors can be used as current switches. Unlike conventional mechanical switches (such as relays and switches), transistors are controlled by electrical signals and can switch very quickly, with switching speeds exceeding 100 GHz in laboratories.

[0085] Furthermore, it's easy to understand that the chip body, which serves as the chip carrier, can contain both epitaxial material and back metal material, i.e., the metal material grown on the back of the body. This material can be a single material, such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), quartz (SiO2), diamond, lithium niobate (LiNbO3), lithium tantalate (LiTaO3), gallium nitride (GaN), gallium arsenide (GaAs), gallium oxide (GaO), aluminum nitride (AlN), etc.; or two different materials, such as gallium nitride on silicon carbide (GaN on SiC), gallium nitride on sapphire (GaN on Al2O3), gallium nitride on silicon (GaN on Si), gallium nitride on diamond (GaN on Diamond), lithium niobate on silicon (LiNbO3 on Si), etc.; or a combination of multiple materials, such as Si+AlN+AlGaN+GaN, Si+SiO2+LiTaO3, etc. In other words, the chip body can be a combination of multiple layers of materials.

[0086] like Figure 6 As shown, the package structure 100 provided in the embodiment of the present application may further include: a second conductive layer 50, wherein the second conductive layer 50 is located at least between the chip body 10 and the first substrate 2, and the second conductive layer 50 is electrically connected to the first conductive layer 20 and the first substrate 2 respectively. By providing the second conductive layer 50 between the chip body 10 and the first substrate 2, and the second conductive layer 50 is electrically connected to the first conductive layer 20 and the first substrate 2 respectively, the electrical contact area between the chip 1 and the first substrate 2 is increased, thereby further reducing the ground parasitic parameters.

[0087] Specifically, refer to Figure 6 As shown, the second conductive layer 50 may be located between the chip body 10 and the first substrate 2, and the second conductive layer 50 is electrically connected to the first conductive layer 20 and the first substrate 2 respectively through bonding wires. Alternatively, referring to Figure 7 As shown, the second conductive layer 50 can be located between the chip body 10 and the first substrate 2, and the second conductive layer 50 is electrically connected to the first conductive layer 20 and the first substrate 2 respectively through the metal layer located in the slot 101 of the chip body 10. Alternatively, referring to Figure 8As shown, the second conductive layer 50 may be located between the chip body 10 and the first substrate 2 , and the second conductive layer 50 is electrically connected to the first conductive layer 20 and the first substrate 2 respectively through the metal layer located on the slot wall of the slot 101 of the chip body 10 .

[0088] In the embodiment of the present application, the second conductive layer 50 is in electrical contact with the second conductive member 40, and the second conductive layer 50 is electrically connected to the first conductive layer 20 through the second conductive member 40. The electrical contact between the second conductive layer 50 and the second conductive member 40 enables the second conductive layer 50 to be electrically connected to the first conductive layer 20 through the second conductive member 40. In this way, the channel formed by the first conductive layer 20 and the substrate is grounded through the second conductive member 40, reducing grounding parasitic parameters and power consumption, thereby improving the output efficiency of the electronic device to a certain extent.

[0089] In one possible implementation, when forming the second conductive layer 50 on the side of the chip body 10 of the chip 1 away from the first conductive layer 20, a metal layer, such as gold or titanium, may be first sputtered on the side of the chip body 10 away from the first conductive layer 20, and then one or more layers of gold, copper, aluminum, or other metals may be electroplated or evaporated on the sputtered metal layer. In addition, a dielectric layer may be grown between the metal layers to isolate electrical signals. Finally, one or more dielectric layers are generally grown as chip protection layers to form the second conductive layer 50. It should be noted that the thickness of the second conductive layer 50 may be 0.1-20 μm. For example, the thickness of the second conductive layer 50 may be 2 μm, 3 μm, 4 μm, 5 μm, etc. This is not limited in the present embodiment and is not limited to the above examples.

[0090] In some embodiments, as Figure 9 As shown, the second conductive layer 50 near the slot 101 can extend into the slot 101 to form an extended conductive layer 501, wherein one end of the extended conductive layer 501 is electrically connected to the first conductive layer 20, so that the second conductive layer 50 is electrically connected to the first conductive layer 20 through the extended conductive layer 501. By extending the extended conductive layer 501 from the second conductive layer 50 near the slot 101 toward the slot 101, and electrically connecting one end of the extended conductive layer 501 to the first conductive layer 20, a conductive path between the first conductive layer 20 and the second conductive layer 50 is increased, further achieving via grounding.

[0091] Specifically, refer to Figure 9As shown, the bonding wire is located in the slot 101 of the chip body 10, one end of the bonding wire is electrically connected to the first conductive layer 20, and the other end of the bonding wire is electrically connected to the first substrate 2. The second conductive layer 50 is close to the slot 101 and extends toward the slot 101 to form an extended conductive layer 501. One end of the extended conductive layer 501 is electrically connected to the first conductive layer 20, and the other end of the extended conductive layer 501 is electrically connected to the first substrate 2 through the second conductive layer 50. In this way, the first conductive layer 20 can be conductively connected to the first substrate 2 through the bonding wire and the extended conductive layer 501.

[0092] Or, refer to Figure 10 As shown, the metal layer is located in the slot 101 of the chip body 10, one end of the metal layer is electrically connected to the first conductive layer 20, and the other end of the metal layer is electrically connected to the first substrate 2. The second conductive layer 50 is close to the slot 101 and extends toward the slot 101 to form an extended conductive layer 501. One end of the extended conductive layer 501 is electrically connected to the first conductive layer 20, and the other end of the extended conductive layer 501 is electrically connected to the first substrate 2 through the second conductive layer 50. In this way, the first conductive layer 20 can be conductively connected to the first substrate 2 through the metal layer and the extended conductive layer 501.

[0093] As an optional implementation, Figure 10 As shown, the thickness L2 of the extended conductive layer 501 can be greater than 0.1 μm. For example, the thickness L2 of the extended conductive layer 501 can be 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, etc. This embodiment of the present application is not limited to this and is not limited to the above examples. It should be noted that the greater the thickness of the extended conductive layer 501, the greater the flow capacity of the via.

[0094] In one possible implementation, the second conductive layer 50 and the extended conductive layer 501 may be made of any one or more of gold, copper, titanium, tungsten, nickel, or vanadium. For example, the second conductive layer 50 may be made of gold, copper, or a composite material of gold and copper. Similarly, the extended conductive layer 501 may be made of gold, copper, or a composite material of gold and copper.

[0095] Next, refer to Figure 11 As shown, the package structure 100 provided in the embodiment of the present application may further include an adhesive layer 5, wherein the adhesive layer 5 is located between the chip 1 and the first substrate 2, and the adhesive layer 5 may be made of a conductive material. The adhesive layer 5 is used to bond the chip 1 and the first substrate 2 to prevent separation between the chip 1 and the first substrate 2. At the same time, by setting the adhesive layer 5 to be a conductive material, it can also play a role in current conduction.

[0096] As an optional embodiment, the bonding layer 5 can be any one or more of gold-tin alloy (AuSn), gold-silicon alloy (AuSi), nanosilver material (Nano-Ag), or silver paste (Epoxy). Of course, the bonding layer 5 can also be other conductive materials. The present embodiment of the application does not limit the specific material of the bonding layer 5, nor is it limited to the above examples. As long as it can perform a conductive function while bonding, it can be used.

[0097] It should be noted that the area of ​​the adhesive layer 5 can be larger or smaller than the chip body 10 , and can be appropriately selected according to different application scenarios. This embodiment of the present application does not limit this.

[0098] In addition, when the package structure 100 needs to be electrically connected to an external device to achieve signal conduction, the connection between the package structure 100 and the external device includes but is not limited to the following two possible implementations:

[0099] One possible implementation is: refer to Figure 12 As shown, pins 21 may be provided on the first substrate 2. The input and output of the chip 1 are electrically connected to the pins 21 via third conductive members 60, and the pins 21 are electrically connected to external devices. Thus, by providing pins 21 electrically connected to external devices on the first substrate 2, and by electrically connecting the pins 21 to the input and output of the chip 1, signal conduction between the chip 1 on the first substrate 2 and the external device can be achieved.

[0100] An insulating layer 3 may be provided between the pins 21 and the first substrate 2. The insulating layer 3 is used to isolate the first substrate 2 from the pins 21 to prevent electrical connection between the first substrate 2 and the pins 21.

[0101] At this time, the packaging form is a cavity packaging form.

[0102] Another possible implementation is: Figure 13 As shown, the input and output terminals of the chip 1 are electrically connected to the second substrate 4 of the external device through the third conductive member 60. By electrically connecting the input and output terminals of the chip 1 to the second substrate 4 of the external device, signal conduction can be achieved between the chip 1 located on the first substrate 2 and the external device located on the second substrate 4.

[0103] In this case, the package is a Quad Flat No-lead Package (QFN). The QFN is a commonly used surface mount package, typically square or rectangular in shape. It features a large exposed pad at the center of the bottom of the package for heat conduction. Surrounding the large pad are conductive pads (also known as leads in the industry) for electrical connections around the periphery of the package. Because the QFN package lacks gull-wing leads, the conductive path between the internal pins and pads is short, resulting in low parasitic coefficients and low wiring resistance within the package, enabling excellent electrical performance. Furthermore, it provides excellent heat dissipation through the exposed lead frame pad, which provides a direct heat dissipation path to release heat within the package. The heat dissipation pad is typically soldered directly to the circuit board, and thermal vias in the board help dissipate excess power dissipation to the copper ground plane, resulting in higher thermal conductivity.

[0104] As an optional implementation, the third conductive member 60 may be a bonding wire.

[0105] In addition, refer to Figure 14 As shown, at least one pad portion 201 may be provided on the first conductive layer 20, wherein one end of the first conductive member 30 is electrically connected to the pad portion 201, and the other end of the first conductive member 30 is electrically connected to the first substrate 2. By providing the pad portion 201 on the first conductive layer 20, one end of the first conductive member 30 is electrically connected to the pad portion 201 on the first conductive layer 20, and the other end of the first conductive member 30 is electrically connected to the first substrate 2, electrical connection between the first conductive layer 20 and the substrate is achieved.

[0106] The first substrate 2 may also be provided with a bonding area (not shown in the figure), and the two ends of the first conductive member 30 are respectively electrically connected to the bonding area and the pad portion 201. By providing the bonding area on the first substrate 2 and the pad portion 201 on the first conductive layer 20, one end of the first conductive member 30 is electrically connected to the bonding area on the first substrate 2, and the other end of the first conductive member 30 is electrically connected to the pad portion 201 on the first conductive layer 20, thereby achieving electrical conduction between the first conductive layer 20 and the substrate.

[0107] It should be noted that the upper surface of the chip 1 generally includes a source 202, a gate 204 and a drain 203, which together form a field effect transistor. Figures 14 to 17Only some transistors are shown; in actual applications, chip 1 may include more transistors. Furthermore, the transistors are not limited to field-effect transistors and may also include metal oxide semiconductor (MOS) transistors, bipolar junction transistors (BJTs), and the like. Furthermore, chip 1 may also include other chip components besides transistors, such as resistors, capacitors, inductors, diodes, and transistors. Furthermore, chip 1 may also be a type of chip other than transistors.

[0108] The gate 204 is a mesh-shaped or spiral electrode composed of metal lines, that is, one or more electrodes arranged between the source and the drain, which plays a role in controlling the working state of the transistor.

[0109] In the embodiment of the present application, the pad portion 201 is generally located inside the source 202, such as Figure 14 As shown, the pad portion 201 may be located on a side of the source 202 away from the drain 203, or, as shown in FIG. Figure 15 As shown, the pad portion 201 can be located on one side of the source 202 close to the drain 203, or, as shown in FIG. Figure 16 As shown, the pad portion 201 can be located at multiple locations within the source electrode 202. The pad 201 is generally located within the source electrode 202. At the same time, multiple pad portions 201 can be placed within a source electrode 202. It should be noted that the embodiments of the present application do not limit the specific location of the pad portion 201, nor are they limited to the above examples.

[0110] Specifically, in some embodiments, Figure 14 As shown, each pad portion 201 may include a first pad area 2011 and a second pad area 2012, wherein the projection of the slot 101 in the vertical direction is located within the first pad area 2011, and the two ends of the first conductive member 30 are electrically connected to the second pad area 2012 and the bonding area, respectively. By including the first pad area 2011 and the second pad area 2012, the projection of the slot 101 in the vertical direction is located within the first pad area 2011, and the two ends of the first conductive member 30 are electrically connected to the second pad area 2012 and the bonding area, respectively, that is, the first pad area 2011 is used to achieve electrical conduction between the first conductive layer 20 and the substrate through the second conductive member 40 in the slot 101, and the second pad area 2012 is used to achieve electrical conduction between the first conductive layer 20 and the substrate through the first conductive member 30. The same pad portion 201 can achieve different conductive channels through the two different pad areas.

[0111] In some other embodiments, the number of pad portions 201 is at least two, the projection of the slot 101 in the vertical direction is located within the first pad portion 2013 of the at least two pad portions 201, and the two ends of the first conductive member 30 are electrically connected to the second pad portion 2014 and the bonding area of ​​the at least two pad portions 201, respectively. By setting the number of pad portions 201 to at least two, the projection of the slot 101 in the vertical direction is located in one of the at least two pad portions 201, and the two ends of the first conductive member 30 are electrically connected to the other of the at least two pad portions 201 and the bonding area, respectively. In this way, one of the at least two pad portions 201 is used to achieve conduction between the first conductive layer 20 and the substrate through the second conductive member 40 in the slot 101, and the other of the at least two pad portions 201 is used to achieve conduction between the first conductive layer 20 and the substrate through the first conductive member 30. That is to say, the at least two pad portions 201 on the first conductive layer 20 are set to achieve different functions, that is, different conduction channels are achieved through two different pad portions 201.

[0112] For example, Figure 17 As shown, the number of pad portions 201 can be set to two, the vertical projection of the slot 101 can be located within the first pad portion 2013, and the two ends of the first conductive member 30 can be electrically connected to the second pad portion 2014 and the bonding area, respectively. By setting the number of pad portions 201 to two, the vertical projection of the slot 101 is located within one of the two pad portions 201, and the two ends of the first conductive member 30 are electrically connected to the other of the two pad portions 201 and the bonding area, respectively, one of the two pad portions 201 is used to achieve electrical connection between the first conductive layer 20 and the substrate through the second conductive member 40 within the slot 101, and the other of the two pad portions 201 is used to achieve electrical connection between the first conductive layer 20 and the substrate through the first conductive member 30. In other words, the two pad portions 201 on the first conductive layer 20 are configured to achieve different functions, that is, different conductive channels are achieved through the two different pad portions 201.

[0113] Figure 18 FIG. 1 is a graph showing changes in efficiency versus output power when the packaging structure 100 in the prior art is applied to an electronic device. Figure 19 This graph shows the efficiency of the package structure 100 provided in an embodiment of the present application as a function of output power when used in an electronic device. In actual application scenarios, modeling and simulation of the novel package structure 100 provided in an embodiment of the present application showed that its grounding parasitic parameters can be reduced by over 30% and its efficiency can be increased by 1.7%. Furthermore, the device's current capacity can be doubled, and even if all vias are disconnected, the device will not burn out.

[0114] For example, Figure 18As shown, when the packaging structure in the prior art and the packaging structure 100 provided in the embodiment of the present application are respectively applied to electronic devices, when the output power values ​​are the same, the efficiency m1 of the packaging structure in the prior art is 35.1%, and the efficiency m2 of the packaging structure 100 provided in the embodiment of the present application is 36.8%, that is, compared with the prior art, the efficiency of the packaging structure 100 provided in the embodiment of the present application can be improved by 1.7%.

[0115] Example 2

[0116] An embodiment of the present application provides an electronic device, comprising at least: the packaging structure 100 in the above-mentioned embodiment 1.

[0117] The electronic device includes at least a package structure 100. A first conductive layer 20 of the package structure 100 is electrically connected to a first substrate 2 via a first conductive member 30 located outside a chip body 10. Furthermore, a slot 101 is defined in the chip body 10, and a second conductive member 40 is disposed within the slot 101. The first conductive layer 20 is electrically connected to the first substrate 2 via the second conductive member 40. By providing two parallel paths between the first conductive layer 20 and the substrate for grounding, grounding parasitic parameters are reduced, power consumption is reduced, and thus, the output efficiency of the electronic device is improved to a certain extent.

[0118] It should be noted that the electronic devices provided in the embodiments of the present application may include but are not limited to semiconductor devices, which can be applied to the field of high-power density electronic components, such as metal-oxide-semiconductor field-effect transistors (metal oxide semiconductor, MOS), insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), power supply chips, etc., so as to achieve a high-efficiency, low-thermal resistance, and highly reliable grounding solution for the device.

[0119] In the description of the embodiments of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to a fixed connection, an indirect connection via an intermediate medium, internal communication between two components, or an interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of this application based on specific circumstances.

[0120] In the embodiments of the present application, any device or element referred to or implied must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present application. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless otherwise specifically specified.

[0121] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging structure, characterized in that: include: A first substrate and a chip disposed on the first substrate; The chip comprises: a chip body and a first conductive layer located above the chip body, wherein the first conductive layer is conductively connected to the first substrate via a first conductive member; The chip body is also provided with a slot, a second conductive member is provided in the slot, and the first conductive layer is electrically connected to the first substrate through the second conductive member; It also includes: a second conductive layer; the second conductive layer is at least located between the chip body and the first substrate, and the second conductive layer is electrically connected to the first conductive layer and the first substrate respectively; It also includes: an adhesive layer; the adhesive layer is located between the chip and the first substrate; and the adhesive layer is a conductive material.

2. The packaging structure according to claim 1, characterized in that: The second conductive layer is close to the slot and extends into the slot to form an extended conductive layer. One end of the extended conductive layer is electrically connected to the first conductive layer. The second conductive layer is electrically connected to the first conductive layer through the extended conductive layer.

3. The packaging structure according to claim 2, characterized in that: The thickness of the extended conductive layer is greater than 0.1 um.

4. The packaging structure according to claim 2 or 3, characterized in that: The second conductive layer and the extended conductive layer are made of any one or more materials selected from the group consisting of gold, copper, titanium, tungsten, nickel and vanadium.

5. The packaging structure according to claim 1, characterized in that: The second conductive layer is in electrical contact with the second conductive member, and the second conductive layer is electrically connected to the first conductive layer through the second conductive member.

6. The packaging structure according to any one of claims 1 to 3 and 5, characterized in that: The first conductive member is a bonding wire.

7. The packaging structure according to any one of claims 1 to 3 and 5, characterized in that: The second conductive member is a bonding wire.

8. The packaging structure according to any one of claims 1 to 3 and 5, characterized in that: The second conductive member is a metal layer disposed in the slot.

9. The packaging structure according to any one of claims 1 to 3 and 5, characterized in that: At least one pad portion is disposed on the first conductive layer, one end of the first conductive member is electrically connected to the pad portion, and the other end of the first conductive member is electrically connected to the first substrate.

10. The packaging structure according to claim 9, characterized in that: A bonding area is provided on the first substrate, and two ends of the first conductive member are electrically connected to the bonding area and the pad portion respectively.

11. The packaging structure according to claim 10, characterized in that: Each of the pad portions includes a first pad area and a second pad area; The projection of the slot in the vertical direction is located in the first pad area, and two ends of the first conductive member are electrically connected to the second pad area and the bonding area respectively.

12. The packaging structure according to claim 10, characterized in that: The number of the pad portions is at least two; The projection of the slot in the vertical direction is located in the first pad portion of the at least two pad portions, and two ends of the first conductive member are electrically connected to the second pad portion of the at least two pad portions and the bonding area respectively.

13. The packaging structure according to any one of claims 1-3, 5, 10-12, characterized in that: The inner diameter of the slot is 10-150um.

14. The packaging structure according to claim 6, characterized in that: The wire diameter of the bonding wire is greater than 25 um.

15. The packaging structure according to claim 7, characterized in that: The wire diameter of the bonding wire is greater than 25 um.

16. The packaging structure according to any one of claims 1-3, 5, 10-12, 14-15, characterized in that: The bonding layer is any one or more of gold-tin alloy, gold-silicon alloy, nano silver material or silver paste.

17. The packaging structure according to any one of claims 1-3, 5, 10-12, 14-15, characterized in that: The first substrate is also provided with pins, and the input end and the output end of the chip are electrically connected to the pins through a third conductive member respectively; The pins are electrically connected to external devices.

18. The packaging structure according to claim 17, characterized in that: Also includes: Insulation layer; The insulating layer is located between the pins and the first substrate.

19. The packaging structure according to claim 17, characterized in that: The third conductive element is a bonding wire.

20. The packaging structure according to any one of claims 1-3, 5, 10-12, 14-15, 18-19, characterized in that: The input end and the output end of the chip are electrically connected to the second substrate of the external device through the third conductive member.

21. An electronic device, characterized in that: At least: The packaging structure described in any one of claims 1 to 20.

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