Display panel and manufacturing method thereof

Abstract

The application provides a display panel and a manufacturing method thereof. The display panel comprises a thin film transistor layer and a passivation layer on the thin film transistor layer. The passivation layer comprises a first passivation layer in a first region and a second passivation layer in a second region. The display panel further comprises a planarization layer on the first passivation layer, a roughness improvement layer on the planarization layer, and an anode on the roughness improvement layer. The application forms the roughness improvement layer on the planarization layer to improve the roughness of the surface of the planarization layer, and then improves the roughness of the anode, so as to improve the efficiency and the service life of the electroluminescent device.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and its manufacturing method. Background Technology

[0002] Organic light-emitting diodes (OLEDs) include thin-film transistor (TFT) devices and OLED devices. OLED devices include a passivation layer, a planarization layer, an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode.

[0003] In the manufacturing process of OLED devices, the surface roughness of the planarization layer may deteriorate. Since the anode is deposited on the planarization layer, for electroluminescent devices, the surface roughness of the anode, as a component of the electroluminescent device, will cause light scattering, resulting in a decrease in the emitted light brightness. Therefore, the roughness of the planarization layer directly affects the roughness distribution of the anode.

[0004] Therefore, how to improve the roughness of the planarization layer is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a display panel and a method for manufacturing the same, which aims to improve the roughness of the planarization layer and enhance the efficiency and lifespan of electroluminescent devices.

[0006] In one aspect, the present invention provides a display panel, comprising:

[0007] Thin-film transistor layer;

[0008] A passivation layer is located on the thin-film transistor layer, the passivation layer comprising a first passivation layer located in a first region and a second passivation layer located in a second region;

[0009] A planarization layer is located on the first passivation layer;

[0010] A roughness-improving layer is located on the planarization layer;

[0011] The anode is located on the roughness improvement layer.

[0012] Furthermore, the roughness improvement layer is a conductive material with fluidity.

[0013] Furthermore, the roughness-improving layer is a nano-silver film or a conductive polymer film.

[0014] Furthermore, the thin-film transistor layer includes a source and a drain, and the roughness improvement layer is electrically connected to the source through a conductive pillar, which penetrates the planarization layer and the passivation layer.

[0015] Furthermore, the first region has the flattening layer, while the second region does not have the flattening layer.

[0016] Furthermore, the anode includes an indium tin oxide layer located on the roughness improvement layer.

[0017] Furthermore, the display panel also includes a metal reflective layer located between the roughness improvement layer and the anode.

[0018] On the other hand, the present invention provides a method for manufacturing a display panel, comprising:

[0019] Forming a thin-film transistor layer;

[0020] A passivation layer is formed on the thin-film transistor layer, the passivation layer comprising a first passivation layer located in a first region and a second passivation layer located in a second region;

[0021] A planar layer is formed on the first passivation layer;

[0022] A roughness-improving layer is formed on the planarization layer;

[0023] An anode is formed on the roughness improvement layer.

[0024] Furthermore, the step of forming a planarization layer on the first passivation layer includes:

[0025] An initial planarization layer is deposited on the passivation layer, the initial planarization layer comprising a first initial planarization layer located in the first region and a second initial planarization layer located in the second region;

[0026] A halftone mask is used to perform a photolithography process on the initial planarization layer to form a first opening in the first initial planarization layer and remove part of the second initial planarization layer, so that the height of the first initial planarization layer is greater than the height of the second initial planarization layer.

[0027] The initial planarization layer is subjected to an ashing process to remove the second initial planarization layer, while retaining a portion of the first initial planarization layer as the planarization layer.

[0028] Furthermore, the thin-film transistor layer includes a source and a drain; prior to the step of ashing the initial planarization layer, the fabrication method further includes:

[0029] A second opening corresponding to the first opening is formed in the passivation layer using an etching process, and the second opening is located on the source electrode;

[0030] After the step of forming a roughness-improving layer on the planar layer, the roughness-improving layer further fills the first opening and the second opening.

[0031] The beneficial effects of this invention are: it provides a display panel and a method for manufacturing the same, comprising a thin-film transistor layer and a passivation layer on the thin-film transistor layer, the passivation layer comprising a first passivation layer in a first region and a second passivation layer in a second region. The display panel further comprises a planarization layer on the first passivation layer, a roughness improvement layer on the planarization layer, and an anode on the roughness improvement layer. This invention improves the surface roughness of the planarization layer by forming a roughness improvement layer on the planarization layer, thereby improving the roughness of the anode, and thus enhancing the efficiency and lifespan of the electroluminescent device. Attached Figure Description

[0032] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of the present invention;

[0034] Figure 2 This is a flowchart illustrating the manufacturing method of the display panel provided in an embodiment of the present invention;

[0035] Figures 3a-3f This is a structural schematic diagram of the manufacturing process of the display panel provided in the embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0039] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0040] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel is an organic light-emitting diode device, also known as an electroluminescent device.

[0041] The display panel includes a substrate 10, a thin-film transistor layer 11, a passivation layer 12, a planarization layer 131, a roughness improvement layer 14, and an anode 15. The substrate 10 can be a flexible substrate or a glass substrate. The thin-film transistor layer 11 is located on the substrate 10 and can be a top-gate structure or a bottom-gate structure. In this embodiment, the thin-film transistor layer 11 includes a light-shielding layer 111, a buffer layer 112, an active layer 113, a gate insulating layer 114, a gate 115, a source 116, a drain 117, and an interlayer dielectric layer 118. The buffer layer 112 covers the light-shielding layer 111, the active layer 113 is located on the buffer layer 112, the gate insulating layer 114 is located on the active layer 113, and the gate 115 is located on the gate insulating layer 114. The interlayer dielectric layer 118 covers the active layer 113, the gate insulating layer 114, and the gate 115, and the interlayer dielectric layer 118 has first vias 1181 at both ends of the active layer 113. The source 116 and drain 117 are located on the inner wall of the first via 1181 and part of the interlayer dielectric layer 118, respectively, and are electrically connected to the active layer 113.

[0042] The display panel also includes a second through-hole 1182 penetrating the interlayer dielectric layer 118. The second through-hole 1182 extends into the buffer layer 112 and connects to the light-shielding layer 111. The source electrode 116 also fills the second through-hole 1182 to achieve electrical connection with the light-shielding layer 111.

[0043] The light-shielding layer 111 can be a metal layer. The buffer layer 112 is a single-layer structure made of one of SiOx, SiNx, and SiNO, or a stacked structure made of SiNx / SiOx. The active layer 113 is made of indium gallium zinc oxide or low-temperature polycrystalline silicon, or any other material that can be used as an active layer. The gate insulating layer 114 and the interlayer dielectric layer 118 can both be made of inorganic materials, namely one of SiOx, SiNx, and SiNO. The gate 115 can be one of metals and their alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu.

[0044] Passivation layer 12 is located on thin-film transistor layer 11 and fills the first via 1181 of interlayer dielectric layer 118. The material of passivation layer 12 can be polymethyl methacrylate. Passivation layer 12 can be divided into a first region 12a and a second region 12b. The first region 12a is a region with a planarization layer 131, such as a display area. The second region 12b is a region without a planarization layer 131, such as a capacitor area or a package clearance area. Passivation layer 12 may include a first passivation layer 121 located in the first region 12a and a second passivation layer 122 located in the second region 12b.

[0045] Planarization layer 131 is located on the first passivation layer 121, but not on the second passivation layer 122. The material of planarization layer 131 can be an inorganic insulating material such as silicon nitride or silicon oxide, or an organic insulating material.

[0046] A roughness-improving layer 14 is located on the planarization layer 131 and is used to improve the roughness of the planarization layer 131. In one embodiment, the roughness-improving layer 14 can be formed on the planarization layer 131 by a coating process, possessing a certain degree of fluidity, thereby filling in the rough terrain on the surface of the planarization layer 131. Moreover, the roughness-improving layer 14 is also a conductive material. Specifically, the roughness-improving layer 14 is a nano-silver film or a conductive polymer film. Among them, the conductive polymer generally has conjugated π bonds and is doped with p-type or n-type ions.

[0047] In one embodiment, the roughness of the roughness improvement layer 14 can be in the range of 0.5 to 5 nm.

[0048] The anode 15 is located on the roughness improvement layer 14, and the anode 15 may include an indium tin oxide layer. The display panel also includes a plurality of pixel definition layers 16 located on the anode 15, with the blank areas between the pixel definition layers 16 serving as light-emitting areas. In one embodiment, the display panel further includes a metal reflective layer 17 located between the roughness improvement layer 14 and the anode 15. The metal reflective layer 17 may be made of metallic silver, and it is used to reflect light emitted from the light-emitting areas upwards to improve upward light extraction efficiency. When the roughness improvement layer 14 is a silver nanofilm, the silver nanofilm can also provide some reflectivity.

[0049] The display panel also includes a light-emitting functional layer on the anode 15 and a cathode (not shown) on the light-emitting functional layer. The light-emitting functional layer includes, from bottom to top, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer.

[0050] The display panel also includes a conductive post 18 penetrating the planarization layer 131 and the passivation layer 12. One end of the conductive post 18 is electrically connected to the source electrode 116, and the other end is electrically connected to the roughness improvement layer 14, thereby enabling the source electrode 116 to drive the anode 15. The material of the conductive post 18 is the same as the material of the roughness improvement layer 14.

[0051] The display panel provided in this embodiment of the invention forms a planarization layer 131 on a first passivation layer 121 and a roughness improvement layer 14 on the planarization layer 131 to improve the roughness of the planarization layer 131, thereby improving the roughness of the anode 15 and thus improving the efficiency and lifespan of the electroluminescent device.

[0052] Please see Figure 2 , Figure 2 This is a schematic flowchart illustrating the manufacturing method of the display panel provided in an embodiment of the present invention. Please also refer to... Figures 3a-3f , Figures 3a-3f This is a structural schematic diagram of the manufacturing process of the display panel provided in an embodiment of the present invention. The manufacturing method of the display panel includes the following steps S1-S5.

[0053] Please see Figure 1 Steps S1-S2 and Figure 3a .

[0054] Step S1: Form thin film transistor layer 11.

[0055] A thin-film transistor layer 11 can be formed on the substrate 10. Specifically, the steps for forming the thin-film transistor layer 11 may include the following: 1) First, a light-shielding layer 111 is formed on the substrate 10 through deposition and etching processes. This light-shielding layer 111 is a metal layer. 2) Then, a buffer layer 112 covering the substrate 10 and the light-shielding layer 111 is formed. A silicon nitride layer and a silicon oxide layer are deposited sequentially by chemical vapor deposition (CVD) to obtain a stacked buffer layer 112. 3) Next, an active layer 113 is formed on the buffer layer 112. A metal oxide, including indium gallium zinc oxide or aluminum gallium tin oxide, is deposited on the buffer layer 112 by physical vapor deposition (PVD). In one embodiment, the two ends of the active layer 113 may be conductive materials, while the middle may be a semiconductor material. 4) A gate insulating layer 114 is formed on the active layer 113. The gate insulating layer 114 can be deposited by plasma enhanced chemical vapor deposition (PECVD). Oxides, nitrides or oxynitrides, such as SiOx or SiNx materials can be selected. The reaction gas can be a mixture of SiH4, HN3 and N2. 5) A gate electrode 115 is formed on the gate insulating layer 114. A metal, such as Cr, W, Ti, Ta, Mo, Al, Cu, or their alloys, can be deposited using PVD. The gate electrode 115 is then obtained through processes such as photoresist coating, exposure, development, and etching. 6) An interlayer dielectric layer 118 is formed covering the active layer 113, the gate insulating layer 114, the gate electrode 115, and the buffer layer 112. A silicon nitride layer can be coated on top as the interlayer dielectric layer 118 using CVD. 7) A first via 1181 is formed in the interlayer dielectric layer 118 through an etching process. The first via 1181 is located at both ends of the active layer 113. A source electrode 116 and a drain electrode 117 are then formed on the inner wall of the first via 1181 and a portion of the interlayer dielectric layer 118.

[0056] Step S2: Form a passivation layer 12 on the thin film transistor layer 11, the passivation layer 12 including a first passivation layer 121 located in a first region 12a and a second passivation layer 122 located in a second region 12b.

[0057] Specifically, a passivation layer 12 can be deposited on the interlayer dielectric layer 118. The passivation layer 12 also fills the first via 1181 and covers a portion of the source 116 and drain 117 located on the interlayer dielectric layer 118. The passivation layer 12 can be divided into a first region 12a and a second region 12b. The first region 12a is a region with a planarization layer 131, such as a display area. The second region 12b is a region without a planarization layer 131, such as a capacitor area or a package clearance area. The passivation layer 12 may include a first passivation layer 121 located in the first region 12a and a second passivation layer 122 located in the second region 12b.

[0058] Please see Figure 1 Step S3 and Figures 3a-3c .

[0059] Step S3: Form a planarization layer 131 on the first passivation layer 121.

[0060] like Figure 3a As shown, an initial planarization layer 13 is first deposited on the passivation layer 12 (including a first region 12a and a second region 12b). The initial planarization layer 13 includes a first initial planarization layer 13a located in the first region 12a and a second initial planarization layer 13b located in the second region 12b. Then, a halftone mask is used to perform a photolithography process on the initial planarization layer 13 to form a first opening 132 in the first initial planarization layer 13a and remove a portion of the second initial planarization layer 13b, so that the height of the first initial planarization layer 13a is greater than the height of the second initial planarization layer 13b.

[0061] Specifically, the photomask has an opening (allowing light to pass through completely) at the location of the first aperture 132 corresponding to the first initial planarization layer 13a, is completely blocked (allowing no light to pass through at all) at other locations corresponding to the first initial planarization layer 13a, and is semi-transparent at the location corresponding to the second initial planarization layer 13b, meaning that some light can pass through. Therefore, during the photolithography process, the depth of the first aperture 132 is greater than the thickness of the removed portion of the second initial planarization layer 13b, meaning that the height of the remaining second initial planarization layer 13b is less than the height of the first initial planarization layer 13a.

[0062] like Figure 3b As shown, the passivation layer 12 or the first passivation layer 121 is then etched based on the first opening 132 to form a second opening 133 corresponding to the first opening 132 in the passivation layer 12. The second opening 133 is located on the source electrode 116.

[0063] like Figure 3cAs shown, the initial planarization layer 13 is ashed to remove the second initial planarization layer 13b, while retaining a portion of the first initial planarization layer 13a as planarization layer 131. The ashing process involves attacking the initial planarization layer 13 with ions. The purpose of this process is to remove the second initial planarization layer 13b from the second region 12b. During the process, the first initial planarization layer 13a is also thinned overall, and the thickness of the thinning of the first initial planarization layer 13a and the second initial planarization layer 13b is generally the same.

[0064] This halftone photolithography process can create patterns of varying shades, reducing the number of photomasks compared to conventional photomasks. Combined with an ashing process, the halftone photolithography process allows for the formation of a planarization layer 131 in the first region 12a and the removal of the second initial planarization layer 13b in the second region 12b, since the second region 12b does not require a planarization layer.

[0065] The inventors discovered that thinning the initial planarization layer 13 inevitably leads to a deterioration in the surface roughness of the initial planarization layer 13 (e.g., ...). Figure 3c As shown in the figure, before the ashing process, the roughness of the initial planarization layer 13 is 2-4 nm, and after the ashing process, the roughness of the initial planarization layer 13 is 6-11 nm. Of course, the roughness will vary under different ashing conditions.

[0066] Please see Figure 1 Step S4 and Figure 3d .

[0067] Step S4: Form a roughness improvement layer 14 on the flattening layer 131.

[0068] After the ashing process, a coating process is performed on the planarization layer 131 to form the roughness improvement layer 14, which also fills the first opening 132 and the second opening 133.

[0069] Please see Figure 1 Step S5 and Figure 3e .

[0070] Step S5: Form an anode 15 on the roughness improvement layer 14.

[0071] In one embodiment, a metal reflective layer 17 (e.g., silver) may be deposited on the roughness improvement layer 14, and then an indium tin oxide layer may be deposited on the metal reflective layer 17 as an anode 15.

[0072] Please see Figure 3e-3f and Figure 1 The manufacturing method of this display panel also includes: 1) such as Figure 3e As shown, a patterned photoresist 19 is formed on the anode 15; 2) as Figure 3f As shown, the anode 15 is etched using the patterned photoresist 19, and then a self-aligned process is used, i.e., the metal reflective layer 17 and the roughness improvement layer 14 are etched sequentially with the anode 15 as the reference to form the opening 151. Therefore, adding the roughness improvement layer 14 does not increase the number of photomasks; 3) As Figure 1 As shown, a pixel definition layer 16 is filled in the opening 151, and the area between the pixel definition layers 16 is a light-emitting area; 4) A light-emitting functional layer and a cathode are formed sequentially in the light-emitting area, which can be done by vapor deposition or by inkjet printing.

[0073] The method for manufacturing a display panel provided in this embodiment of the invention employs a halftone mask and an ashing process to form a planarization layer 131 in the first region 12a, and removes the second initial planarization layer 13b in the second region 12b. This process can reduce the number of photomasks. In addition, coating a roughness improvement layer 14 on the planarization layer 131 can improve the roughness of the planarization layer 131 (regardless of the cause of roughness degradation), thereby improving the roughness of the anode 15 and enhancing the efficiency and lifespan of the electroluminescent device.

[0074] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Thin-film transistor layer; A passivation layer is located on the thin-film transistor layer; A planarization layer is located on the passivation layer; A roughness improvement layer is located on the planarization layer. The roughness of the roughness improvement layer is less than that of the planarization layer. The roughness improvement layer is a nano-silver film with a roughness of 0.5 nm to 5 nm. The anode is located on the roughness improvement layer.

2. The display panel according to claim 1, characterized in that, The thin-film transistor layer includes a source and a drain. The roughness improvement layer is electrically connected to the source through a conductive pillar, which penetrates the planarization layer and the passivation layer.

3. The display panel according to claim 1, characterized in that, The passivation layer includes a first passivation layer located in a first region and a second passivation layer located in a second region, wherein the first region has the planarization layer and the second region does not have the planarization layer.

4. The display panel according to claim 1, characterized in that, The anode includes an indium tin oxide layer located on the roughness improvement layer.

5. A method for manufacturing a display panel, characterized in that, include: Forming a thin-film transistor layer; A passivation layer is formed on the thin-film transistor layer; Forming a planar layer on the passivation layer; A roughness-improving layer is formed on the planarization layer, the roughness of the roughness-improving layer is less than the roughness of the planarization layer, the roughness-improving layer is a nano-silver film, and the roughness of the roughness-improving layer is 0.5 nm to 5 nm; An anode is formed on the flat layer.

6. The method for manufacturing a display panel according to claim 5, characterized in that, The step of forming a planarization layer on the passivation layer includes: An initial planarization layer is deposited on the passivation layer, the initial planarization layer comprising a first initial planarization layer located in a first region and a second initial planarization layer located in a second region; A halftone mask is used to perform a photolithography process on the initial planarization layer to form a first opening in the first initial planarization layer and remove part of the second initial planarization layer, so that the height of the first initial planarization layer is greater than the height of the second initial planarization layer. The initial planarization layer is subjected to an ashing process to remove the second initial planarization layer, while retaining a portion of the first initial planarization layer as the planarization layer.

7. The method for manufacturing a display panel according to claim 6, characterized in that, The thin-film transistor layer includes a source and a drain; prior to the step of ashing the initial planarization layer, the fabrication method further includes: A second opening corresponding to the first opening is formed in the passivation layer using an etching process, and the second opening is located on the source electrode; After the step of forming a roughness-improving layer on the planar layer, the roughness-improving layer further fills the first opening and the second opening.

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