Split-Gate Dual-Bit Non-Volatile Memory Cell with an Erase Gate Located above a Word Line Gate and Method of Fabricating the Same

Abstract

The present invention discloses a memory device, which includes a semiconductor substrate; a first region and a second region in the substrate, the conductive types of the first region and the second region being different from the conductive type of the substrate, wherein a channel region in the substrate extends between the first region and the second region. The channel region is continuous between the first region and the second region. A first floating gate is disposed above a first portion of the channel region and is insulated from the first portion. A second floating gate is disposed above a second portion of the channel region and is insulated from the second portion. A first coupling gate is disposed above the first floating gate and is insulated from the first floating gate. A second coupling gate is disposed above the second floating gate and is insulated from the second floating gate. A word line gate is disposed above a third portion of the channel region between the first channel region portion and the second channel region portion and is insulated from the third portion. An erase gate is disposed above the word line gate and is insulated from the word line gate.

Description

Technical Field

[0001] The present invention relates to non - volatile memory arrays, and more particularly to split - gate dual - bit memory cells having multiple floating gates, coupling gates, word - line gates, and erase gates. Background Art

[0002] Split - gate non - volatile flash memory cells are well - known. For example, U.S. Patent No. 6,747,310 discloses such memory cells having a source region and a drain region that define a channel region therebetween; a select gate over a portion of the channel region; a floating gate over another portion of the channel region; and an erase gate over the source region. Memory cells are formed in pairs that share a common source region and a common erase gate, where each memory cell has its own channel region extending between the source region and the drain region in the substrate (i.e., there are two separate channel regions for each pair of memory cells). The lines connecting all the control gates for the memory cells in a given column run vertically. The same is true for the lines connecting the erase gate and the select gate, and the source line. The bit lines connecting the drain regions for each row of memory cells run horizontally.

[0003] Each memory cell stores a single bit of information (based on the programming state of the floating gate). Given the number of electrodes (source, drain, select gate, control gate, and erase gate) for each cell, and the two separate channel regions for each pair of memory cells, configuring and forming an architecture and array layout where all the various lines are connected to these electrodes can be overly complex and difficult to implement, especially as the critical dimensions continue to shrink.

[0004] One solution is to eliminate the source region and have two memory cells share a single continuous channel region and a common word - line gate, and this solution is disclosed in U.S. Patent No. 8,780,625. However, among other reasons, this configuration has performance limitations due to the lack of an erase gate. U.S. Patent No. 10,658,027 discloses a single continuous channel region and a common erase gate, but lacks any word - line gate positioned to control the conductivity of a portion of the channel region. U.S. Patent No. 9,972,632 discloses a single continuous channel region with a common word - line gate and an erase gate. However, this configuration is not ideal because the erase efficiency can be affected by a high coupling ratio with the drain region and the lack of a geometry that enhances the erase tunneling efficiency. Summary of the Invention

[0005] The above problems and requirements are solved by a memory device that includes a substrate of a semiconductor material of a first conductivity type; a first region and a second region spaced apart in the substrate and having a second conductivity type different from the first conductivity type, wherein a channel region in the substrate extends between the first region and the second region, and wherein the channel region is continuous between the first region and the second region; a first floating gate disposed above and insulated from a first portion of the channel region adjacent to the first region; a second floating gate disposed above and insulated from a second portion of the channel region adjacent to the second region; a first coupling gate disposed above and insulated from the first floating gate; a second coupling gate disposed above and insulated from the second floating gate; a word line gate disposed above and insulated from a third portion of the channel region between the first channel region portion and the second channel region portion; and an erase gate disposed above and insulated from the word line gate.

[0006] A method of forming a memory cell includes forming a first insulating layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a third insulating layer on the second conductive layer; forming a trench extending through the third insulating layer, the second conductive layer, and the second insulating layer; forming insulating spacers along sidewalls of the trench; causing the trench to extend through the first conductive layer between the insulating spacers; forming a word line gate in the trench, wherein the word line gate is vertically disposed above and insulated from the substrate; forming an erase gate in the trench, wherein the erase gate is vertically disposed above and insulated from the word line gate; removing portions of the second conductive layer while retaining first and second portions of the second conductive layer as a corresponding first coupling gate and second coupling gate, respectively, and removing portions of the first conductive layer while retaining first and second portions of the first conductive layer as a corresponding first floating gate and second floating gate, respectively; and forming a first region and a second region of a second conductivity type different from the first conductivity type in the substrate, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first region and the second region. The first floating gate is disposed above and insulated from the substrate and is laterally adjacent and insulated from the word line gate. The second floating gate is disposed above and insulated from the substrate and is laterally adjacent and insulated from the word line gate. The first coupling gate is disposed above and insulated from the first floating gate. The second coupling gate is disposed above and insulated from the second floating gate.

[0007] A method of forming a memory cell includes forming a first insulating layer on a semiconductor substrate of a first conductivity type; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a third insulating layer on the second conductive layer; removing portions of the second conductive layer while retaining first and second portions of the second conductive layer as a corresponding first coupling gate and second coupling gate, respectively, and removing portions of the first conductive layer while retaining first and second portions of the first conductive layer as a corresponding first floating gate and second floating gate, respectively; forming a word line gate that is vertically disposed above the substrate and insulated therefrom and horizontally disposed between the first floating gate and the second floating gate; forming an erase gate that is vertically disposed above the word line gate and insulated therefrom and horizontally disposed between the first coupling gate and the second coupling gate; and forming first and second regions of a second conductivity type different from the first conductivity type in the substrate, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first region and the second region. The first floating gate is disposed above the substrate and insulated therefrom. The second floating gate is disposed above the substrate and insulated therefrom. The first coupling gate is disposed above the first floating gate and insulated therefrom. The second coupling gate is disposed above the second floating gate and insulated therefrom.

[0008] Other objects and features of the present invention will become apparent by referring to the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 1F FIG. is a side cross-sectional view showing steps of forming a two-bit memory cell of the present invention.

[0010] Figure 2 FIG. is a side cross-sectional view showing a final two-bit memory cell structure of the present invention.

[0011] Figures 3A to 3F FIG. is a side cross-sectional view showing steps of forming an alternative embodiment of a two-bit memory cell of the present invention.

[0012] Figure 4 FIG. is a side cross-sectional view showing a final alternative embodiment two-bit memory cell structure of the present invention.

[0013] Figure 5 FIG. is a plan view showing a control circuit for operating an array of two-bit memory cells of the present invention. DETAILED DESCRIPTION

[0014] The present invention relates to a memory cell design, architecture, and method of fabricating split-gate two-bit memory cells. Refer to Figures 1A to 1F, a cross-sectional view showing steps in the process of fabricating a two-bit memory cell. Although only the formation of a single two-bit memory cell is shown in the drawing, it should be understood that an array of such two-bit memory cells is formed simultaneously when fabricating a memory device including such an array of two-bit memory cells. The process begins by forming a first insulating layer 12 (e.g., a silicon dioxide layer, also referred to herein as oxide layer 12) on the top surface 10a of a substrate 10 of a semiconductor material (e.g., single-crystalline silicon). Thereafter, a first conductive layer 14 (e.g., polysilicon (also referred to herein as "poly") or amorphous silicon) is formed on oxide layer 12. Then a second insulating layer 16 is formed on conductive layer 14. Preferably, second insulating layer 16 is an ONO layer, meaning it has oxide-nitride-oxide sub-layers. A second conductive layer 18 (e.g., polysilicon or amorphous silicon) is formed on second insulating layer 16. A third insulating layer 20 (e.g., silicon nitride - referred to herein as "nitride") is formed on second conductive layer 18. A photoresist material (not shown) is coated on this structure, and a photolithography masking step is performed to expose selected portions of the photoresist material. The photoresist is developed such that portions of the photoresist are removed. Using the remaining photoresist as a mask, the structure is etched. Specifically, anisotropic etching is performed on third insulating layer 20, second conductive layer 18, and second insulating layer 16 (using conductive layer 14 as an etch stop layer), thereby leaving trenches 22 that extend through third insulating layer 20, second conductive layer 18, and second insulating layer 16. The resulting structure is shown in Figure 1A (after photoresist removal).

[0015] Insulating spacers 24 / 26 (e.g., ON - oxide and nitride) are formed along the sidewalls of trenches 22. The formation of spacers is well known in the art and involves deposition of a material above the profile of the structure, followed by an anisotropic etching process, whereby the material is removed from the horizontal surfaces of the structure while the material remains largely intact on the vertically oriented surfaces of the structure (with a rounded upper surface, not shown). Insulating (ON) spacers 24 / 26 are formed by oxide deposition, nitride deposition, and subsequent anisotropic etching of the nitride and anisotropic etching of the oxide. Then an oxide spacer 28 is formed in trenches 22 by oxide deposition and subsequent anisotropic etching of the oxide. Thereafter, anisotropic etching is performed to remove the exposed portions of conductive layer 14 located below the regions between oxide spacers 28 (as Figure 1B shown), thereby deepening trenches 22. Implantation can be performed at this time (through oxide layer 12 at the bottom of trenches 22 and into portions of the underlying substrate 10 that will ultimately be the word line portions of the channel regions, as further described below).

[0016] Next, an oxide spacer 30 is formed along the sidewalls of the trench 22 (including along the exposed sidewalls of the conductive layer 14) by oxide deposition and anisotropic oxide etching. The spacer formation, in particular the anisotropic oxide etching that removes portions of the oxide layer 12 at the bottom of the trench 22, exposes portions of the substrate surface 10a between the oxide spacers 30. Preferably, an oxide layer 32 is formed on this exposed portion of the substrate surface 10a at the bottom of the trench 22 by thermal oxidation. Also preferably, the thickness of the oxide layer 32 is less than the thickness of the oxide layer 12. A first conductive material block 34 is formed on the oxide layer 32 within the trench 22 by material deposition, chemical mechanical polishing (CMP) using the third insulating layer 20 as a stop layer, and etchback. Preferably, the first conductive material block 34 is formed of polysilicon, and the top surface of the first conductive material block 34 is lower than the top surface of the conductive layer 14. The first conductive material block 34 is laterally adjacent to and insulated from the conductive layer 14. If polysilicon is used for the first conductive material block 34, implantation may be performed to dope the first conductive material block 34. The resulting structure is shown in Figure 1C FIG.

[0017] The upper portions of the oxide spacers 30 (above the conductive material block 34) and all of the oxide spacers 28 are removed using oxide etching (e.g., wet etching). Then an oxide layer 36 is formed over the structure by oxide deposition. A second conductive material block 38 is formed on the oxide layer 36 within the trench 22 by material deposition and chemical mechanical polishing (CMP) using the third insulating layer 20 as a stop layer. Preferably, the second conductive material block 38 is formed of polysilicon. The resulting structure is shown in Figure 1D FIG.

[0018] A photoresist material 40 is coated over the structure, and a photolithography masking step is performed to expose selected portions of the photoresist material. The photoresist material 40 is developed such that portions of the photoresist material 40 are removed (except for the photoresist material 40 above the second conductive material block 38 and above the portions of the third insulating layer 20 adjacent to the second conductive material block 38). Using the remaining photoresist material 40 as a mask, the structure is etched to remove the exposed portions of the third insulating layer 20, the second conductive layer 18, the second insulating layer 16, and the conductive layer 14, as shown in Figure 1EAs shown. After removing the photoresist 40, spacers 42 (e.g., nitride) are formed along the sides of the structure by deposition and anisotropic etching. Then implantation is performed to form drain regions 44a and 44b in the substrate 10, which are laterally adjacent to the spacers 42 and extend beneath the respective spacers 42 and partially beneath the respective adjacent conductive layers 14. The drain regions 44a / 44b are the first and second regions of the substrate, and their conductivity type is different from that of the substrate 10 near the following channel region 46. For example, the channel region 46 may have P-type conductivity, and the drain regions 44a / 44b may have N-type conductivity, and vice versa. The final structure is shown in Figure 1F in.

[0019] The final two-bit memory cell 50 is in Figure 2Best shown therein, where the channel region 46 (which is continuous) is defined in the substrate 10 by spaced-apart first drain (bit line) regions 44a and second drain (bit line) regions 44b and extends between the spaced-apart first drain (bit line) regions 44a and second drain (bit line) regions 44b. A first floating gate 14a (a first block of material remaining from the conductive layer 14) is disposed above and insulated from a first portion of the channel region 46 adjacent to the first drain region 44a (to control its conductivity), and preferably the first floating gate 14a is partially disposed above the first drain region 44a and insulated from the first drain region by a corresponding remaining portion of the oxide layer 12. A first coupling gate 18a (a first block of material remaining from the conductive layer 18) is disposed above the first floating gate 14a and insulated from the first floating gate by a corresponding remaining portion of the second insulating layer 16 (to couple voltage to the floating gate 14a). A second floating gate 14b (a second block of material remaining from the conductive layer 14) is disposed above and insulated from a third portion of the channel region 46 adjacent to the second drain region 44b (to control its conductivity), and preferably the second floating gate 14b is partially disposed above the second drain region 44b and insulated from the second drain region by a corresponding remaining portion of the oxide layer 12. A second coupling gate 18b (a second block of material remaining from the conductive layer 18) is disposed above the second floating gate 14b and insulated from the second floating gate by a corresponding remaining portion of the second insulating layer 16 (to couple voltage to the floating gate 14b). A first conductive material block 34 is a word line gate that is disposed vertically above a second portion of the channel region 46 and insulated from the second portion (to control its conductivity) and is laterally adjacent to the first floating gate 14a and the second floating gate 14b. A second conductive material block 38 is an erase gate that is disposed vertically above the word line gate 34 and insulated from the word line gate and is laterally adjacent to and insulated from the first coupling gate 18a and the second coupling gate 18b, the insulation from the word line gate 34 being provided by the oxide layer 36 and the insulation from the first coupling gate 18a and the second coupling gate 18b being provided by the oxide layer 36 and the spacers 24 / 26. The erase gate 38 includes notches 38a, each notch facing a corresponding edge 14c of one of the first floating gate 14a and the second floating gate 14b. Insulating blocks 20a and 20b (blocks of material remaining from the third insulating layer 20) are disposed above the first coupling gate 18a and the second coupling gate 18b.

[0020] Table 1 below shows exemplary operating voltages and currents for programming, reading, and erasing operations of the two-bit memory cell 50.

[0021] Table 1

[0022]

[0023]

[0024] Vcc can be, for example, 0.9V to 3.3V. Vblr can be, for example, 0.6V to 1.1V.

[0025] Electrons are used to program the first floating gate 14a to store the first bit (i.e., bit 1) information, and electrons are used to program the second floating gate 14b to store the second bit (i.e., bit 2) information. To program the first floating gate 14a, a voltage of about 4.5V is applied to the erase gate 38 and a voltage of about 10.5V is applied to the first coupling gate 18a, which are capacitively coupled to the first floating gate 14a. A voltage of about 1V is applied to the word line gate 34 to turn on the portion of the channel region 46 under the word line gate 34. A voltage of about 4.5V is applied to the second coupling gate 18b that is capacitively coupled to the second floating gate 14b to turn on the portion of the channel region 46 under the second floating gate 14b. A voltage of about 4.5V is applied to the first drain region 44a, and a current of about -1uA is applied to the second drain region 44b. Electrons travel from the second drain region 44b towards the first drain region 44a and inject themselves onto the first floating gate 14a because the erase gate 38 and the first coupling gate 18a capacitively couple a positive voltage to the first floating gate 14a. Similarly, the second floating gate 14b is programmed using the combination of voltages for bit 2 in Table 1.

[0026] To erase the first floating gate 14a and the second floating gate 14b, a voltage of about 8.5 volts is applied to the erase gate 38, and a negative voltage of about -7V is applied to the first coupling gate 18a and the second coupling gate 18b, which causes electrons to tunnel from the first floating gate 14a and the second floating gate 14b through the insulating layer 36 to the erase gate 38. The notch 38a facing the corresponding edge 14c enhances the efficiency of this tunneling.

[0027] To read the first floating gate 14a, Vcc is applied to the word line gate 34, thereby turning on the portion of the channel region 46 below the word line gate 34. A voltage of Vblr is applied to the second drain region 44b, and zero volts is applied to the first drain region 44a. A voltage of approximately 4.5V is applied to the second coupling gate 18b that is capacitively coupled to the second floating gate 14b (thereby turning on the portion of the channel region 46 below the second floating gate 14b). If the first floating gate 14a is erased, current will flow through the channel region 46 (i.e., in the erased state, there will be a positive voltage on the first floating gate 14a due to positive charge on the first floating gate 14a after erasure from the word line gate 34 and small voltage coupling, whereby the portion of the channel region 46 below the first floating gate 14a is turned on). The current is sensed as the erased state. If the first floating gate 14a is programmed (i.e., programmed with electrons sufficient to prevent turning on the portion of the channel region below the first floating gate 14a), the current will decrease or not flow through the channel region 46. This low current or no current is sensed as the programmed state. Similarly, the voltage combination of bit 2 in Table 1 is used to read the second floating gate 14b.

[0028] The two-bit memory cell 50 has many advantages. The insulating layer below the word line gate (i.e., the oxide layer 32) can be much thinner than the insulating layers below the first floating gate 14a and the second floating gate 14b (i.e., the oxide layer 12) to achieve higher performance especially for high-speed applications. The insulating layer between the first floating gate 14a and the second floating gate 14b and the erase gate 38 (i.e., the oxide layer 36) can be thinner than the insulating layer between the first floating gate 14a and the second floating gate 14b and the word line gate 34 (i.e., the oxide spacer 30). The erase performance is enhanced due to the relatively low voltage coupling ratio between the erase gate 38 and the first floating gate 14a and the second floating gate 14b (only because the corner region of the erase gate 38 (with the notch 38a) is closely adjacent to the corner regions of the first floating gate 14a and the second floating gate 14b (with the edges 14c)). Only two photolithography mask steps are required to define the structure, one photolithography mask step for forming the trench 22, and another photolithography mask step for etching through the conductive layers 18 and 14 to complete the formation of the first coupling gate 18a and the second coupling gate 18b and the first floating gate 14a and the second floating gate 14b. Both the word line gate 34 and the erase gate 38 are self-aligned to the first floating gate 14a and the second floating gate 14b.

[0029] Figures 3A to 3F An alternative embodiment for forming a two-bit memory cell is shown, which starts from a structure similar to the Figure 1A structure shown, except that as Figure 3AAs shown, when forming trench 22, additional trenches 52 are also formed (one on each side of trench 22) (after photoresist removal). Forming two trenches 52 and trench 22 therebetween creates stacked structures S1 and S2, each stacked structure having, from top to bottom in sequence, blocks of third insulating layer 20, blocks of second conductive layer 18, blocks of second insulating layer 16, and conductive layer 14. Using the same processing steps as described above with respect to Figure 1B the same, oxide spacers 24, nitride spacers 26, and oxide spacers 28 are formed along the sidewalls of stacked structures S1 and S2, thereby creating Figure 3B the structure shown. Then, using a masking step, the stacked structures S1 and S2 are covered with photoresist, but the oxide spacers 28 on the outer sides facing the sidewalls of stacked structures S1 and S2 are not covered. Then, etching is used to remove the oxide spacers 28 on the outer sides facing the sidewalls of stacked structures S1 and S2. After photoresist removal, the exposed portions of conductive layer 14 (i.e., those portions not protected by stacked structures S1 and S2) are removed by etching, thereby creating Figure 3C the structure of. Implantation can be performed at this time (through the oxide layer 12 between stacked structures S1 and S2 and into the portion of the underlying substrate 10 that will ultimately be the word line portion of the channel region, as further described below).

[0030] Next, oxide spacers 30 are formed along the sidewalls of stacked structures S1 / S2 (including along the exposed sidewalls of conductive layer 14) by oxide deposition and anisotropic oxide etching. The formation of this spacer, particularly the anisotropic oxide etching that removes portions of oxide layer 12 at the bottom of trench 22, removes the exposed portions of oxide layer 12. Preferably, an oxide layer 32 is formed on the exposed portion of substrate surface 10a at the bottom of trench 22 by thermal oxidation. Also preferably, the thickness of oxide layer 32 is less than the thickness of oxide layer 12. A conductive layer 54 (e.g., polysilicon or amorphous silicon) is formed on this structure. Chemical mechanical polishing (CMP) is performed on the conductive layer (using the third insulating layer 20 as the stop layer). Then, etching is used to lower the top surface of conductive layer 54, preferably below the top surface of conductive layer 14. If polysilicon is used for conductive layer 54, implantation can be performed to dope conductive layer 54. The resulting structure is shown in Figure 3D in.

[0031] Oxide etching (e.g., wet etching) is used to remove the upper portions of oxide spacers 30 (above conductive layer 54) and all oxide spacers 28. Then, an oxide layer 56 is formed on this structure by oxide deposition. A conductive layer 58 is formed on oxide layer 56. Preferably, conductive layer 58 is formed of polysilicon. Then, chemical mechanical polishing (CMP) is performed using the third insulating layer 20 as the stop layer. The resulting structure is shown in Figure 3E in.

[0032] A photoresist material is coated on the structure, exposed, and selectively removed such that the regions above and between the stacked structures S1 and S2 are covered, but the regions outside the stacked structures S1 and S2 are exposed (i.e., Figure 3E the region to the right of the stacked structure S2 and the region to the left of the stacked structure S1 in Figure 3F ). Then, etching is performed to remove portions of the conductive layer 58, oxide layer 56, and conductive layer 54 outside the stacked structures S1 / S2. After the photoresist is removed, spacers 42 (e.g., nitride) are formed along the sides of the structure by deposition and anisotropic etching. Then, implantation is performed to form a first drain region 44a and a second drain region 44b in the substrate 10, which are laterally adjacent to the spacers 42 and extend under the respective spacers 42 and partially under the respective adjacent conductive layer 14. The final structure is shown in

[0033] The final two-bit memory cell 62 of an alternative embodiment is best shown in Figure 4 and substantially has the same structure as the structure shown in Figure 2 , except that the erase gate 58a is the remaining portion of the conductive layer 58 (where the notch 58b faces the respective edges 14c of the first floating gate 14a and the second floating gate 14b), the word line gate 54a is the remaining portion of the conductive layer 54, and the tunnel oxide separating the erase gate 58a from the first floating gate 14a and the second floating gate 14b is the oxide layer 56.

[0034] Additional advantages of the alternative embodiment include that the horizontal dimensions of the first coupling gate 18a and the second coupling gate 18b are defined by a single lithography step, which can reduce the dimensional variations of the first coupling gate 18a and the second coupling gate 18b.

[0035] A control circuit 96 (as shown in Figure 5 ) preferably (but not necessarily) formed on the same substrate 10 is configured to program, read, and erase the memory array 98 of the two-bit memory cell 50 or 62 described herein by applying the voltages of Table 1 as described above.

[0036] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but encompasses any and all variations falling within the scope of the appended claims. For example, the reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only to refer to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values described above are merely exemplary and should not be regarded as limiting the claims. Additionally, it is apparent from the claims and the specification that not all method steps need to be performed in the exact order shown or claimed, but rather in any order that permits the proper formation of the memory cell array of the present invention. Finally, a single material layer may be formed as multiple such or similar material layers, and vice versa.

[0037] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (with no intervening material, element, or space therebetween) and "indirectly on" (with intervening material, element, or space therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or space therebetween) and "indirectly adjacent" (with intervening material, element, or space therebetween), "mounted to" includes "directly mounted to" (with no intervening material, element, or space therebetween) and "indirectly mounted to" (with intervening material, element, or space therebetween), and "electrically connected to" includes "directly electrically connected to" (with no intervening material or element electrically connecting the elements together) and "indirectly electrically connected to" (with intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate with no intervening material / element therebetween, and forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A method of forming a memory cell, comprising: Forming a first insulating layer on a semiconductor substrate having a first conductivity type; Forming a first conductive layer on the first insulating layer; Forming a second insulating layer on the first conductive layer; Forming a second conductive layer on the second insulating layer; Forming a third insulating layer on the second conductive layer; Forming a trench extending through the third insulating layer, the second conductive layer, and the second insulating layer; Forming insulating spacers along sidewalls of the trench; Extending the trench through the first conductive layer between the insulating spacers; Forming a word line gate in the trench, wherein the word line gate is vertically disposed above the substrate and insulated from the substrate; Forming an erase gate in the trench, wherein the erase gate is vertically disposed above the word line gate and insulated from the word line gate; Removing portions of the second conductive layer while retaining first and second portions of the second conductive layer as a corresponding first coupling gate and second coupling gate, and removing portions of the first conductive layer while retaining first and second portions of the first conductive layer as a corresponding first floating gate and second floating gate; And Forming first and second regions having a second conductivity type different from the first conductivity type in the substrate, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first region and the second region, Wherein: The first floating gate is disposed above the substrate and insulated from the substrate and is laterally adjacent and insulated from the word line gate, The second floating gate is disposed above the substrate and insulated from the substrate and is laterally adjacent and insulated from the word line gate, The first coupling gate is disposed above the first floating gate and insulated from the first floating gate, and The second coupling gate is disposed above the second floating gate and insulated from the second floating gate.

2. The method according to claim 1, wherein: The word line gate is disposed to be laterally adjacent and insulated from the first floating gate and the second floating gate; And The erase gate is disposed to be laterally adjacent and insulated from the first coupling gate and the second coupling gate.

3. The method according to claim 1, wherein before forming the erase gate, the method further comprises: Removing one of the insulating spacers along the sidewall of the trench.

4. The method according to claim 3, wherein the erase gate includes a first notch facing an edge of the first floating gate and a second notch facing an edge of the second floating gate.

5. The method according to claim 1, wherein the first floating gate is partially disposed above the first region and insulated from the first region, and the second floating gate is partially disposed above the second region and insulated from the second region.

6. The method according to claim 1, wherein an insulating layer between the word line gate and the substrate is thinner than insulating layers between the first floating gate and the second floating gate and the substrate.

7. The method according to claim 1, wherein an insulating layer between the erase gate and the first floating gate and the second floating gate is thinner than an insulating layer between the word line gate and the first floating gate and the second floating gate.

8. A method of forming a memory cell, comprising: forming a first insulating layer on a semiconductor substrate of a first conductivity type; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a third insulating layer on the second conductive layer; removing a portion of the second conductive layer while retaining a first portion and a second portion of the second conductive layer as a corresponding first coupling gate and a second coupling gate, and removing a portion of the first conductive layer while retaining a first portion and a second portion of the first conductive layer as a corresponding first floating gate and a second floating gate; forming a word line gate that is vertically disposed above the substrate and insulated from the substrate and is laterally disposed between the first floating gate and the second floating gate; forming an erase gate that is vertically disposed above the word line gate and insulated from the word line gate and is laterally disposed between the first coupling gate and the second coupling gate; and forming a first region and a second region of a second conductivity type different from the first conductivity type in the substrate, wherein the first region is adjacent to the first floating gate and the second region is adjacent to the second floating gate, and wherein a continuous channel region in the substrate extends between the first region and the second region; forming insulating spacers along sidewalls of the first coupling gate and the second coupling gate after removing the portion of the second conductive layer and before removing the portion of the first conductive layer; removing one of the insulating spacers along sidewalls of the first coupling gate and the second coupling gate before forming the erase gate; wherein: the first floating gate is disposed above the substrate and insulated from the substrate, the second floating gate is disposed above the substrate and insulated from the substrate, the first coupling gate is disposed above the first floating gate and insulated from the first floating gate, and the second coupling gate is disposed above the second floating gate and insulated from the second floating gate.

9. The method according to claim 8, wherein the erase gate includes a first notch facing an edge of the first floating gate and a second notch facing an edge of the second floating gate.

10. The method according to claim 8, wherein: the word line gate is disposed to be laterally adjacent to the first floating gate and the second floating gate and insulated from the first floating gate and the second floating gate; and the erase gate is disposed to be laterally adjacent to the first coupling gate and the second coupling gate and insulated from the first coupling gate and the second coupling gate.

11. The method according to claim 8, wherein the first floating gate is partially disposed above the first region and insulated from the first region, and the second floating gate is partially disposed above the second region and insulated from the second region.

12. The method according to claim 8, wherein the insulating layer between the word line gate and the substrate is thinner than the insulating layers between the first floating gate and the second floating gate and the substrate.

13. The method according to claim 8, wherein the insulating layer between the erase gate and the first floating gate and the second floating gate is thinner than the insulating layer between the word line gate and the first floating gate and the second floating gate.

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