A clock generation circuit suitable for digital LDOs

Abstract

The application discloses a clock generating circuit suitable for a digital LDO, comprising a starting module, a state comparison module and a clock stabilizing module; the clock generating circuit controls the digital LDO to work in a self-circulation mode, and does not need an external clock signal. The generated clock signal chain automatically triggers the working pulse of the next module after the signal processing of the previous module is completed in a pipeline mode, greatly accelerates the circuit running speed, reduces the static power consumption of the circuit, and avoids the signal sampling error problem caused by PVT; the clock frequency generated by the clock generating circuit is determined by the overall delay size of the circuit, and the clock frequency can be as high as 300MHz, so that the transient response performance of the digital LDO circuit can be effectively enhanced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power management technology, specifically a clock generation circuit suitable for digital LDOs. Background Technology

[0002] Low dropout regulators (LDOs) are a crucial component of power management chips, responsible for providing a stable DC voltage to subsequent circuits. Based on their loop control methods, LDOs can be categorized into analog LDOs and digital LDOs. Analog LDOs rely on a negative feedback loop consisting of an error amplifier, power transistors, and a voltage divider network to stabilize the output voltage. As the supply voltage decreases, the gain and bandwidth of the error amplifier become limited. Below 1V, the performance of analog LDOs faces significant challenges. Digital LDOs, on the other hand, adjust the number of power transistors on based on the comparator's output state to achieve output voltage stability. Compared to analog LDOs, digital LDOs operate at even lower voltages and are more suitable for sub-1V power supply environments.

[0003] Transient response speed is a key performance indicator of a digital LDO, reflecting its ability to recover from sudden load changes. It primarily depends on the LDO's clock frequency and power transistor control method. To improve the transient characteristics of a digital LDO, a high-frequency clock signal of 10MHz or higher is typically used. The clock is generated by an external high-frequency oscillator and connected to the digital LDO through a digital I / O port. Simultaneously, coarse-fine adjustment and proportional-integral-derivative (PID) control methods are introduced to further shorten the transient recovery time and improve the transient response characteristics of the digital LDO. However, this external clock signal design requires additional oscillator circuitry and external I / O ports, increasing the overall chip area and cost. Furthermore, the connection between the external high-frequency oscillator and the digital LDO increases clock signal delay, reducing the clock frequency and the overall operating speed of the digital LDO.

[0004] Improving transient response characteristics is a key challenge in digital LDO circuit design. An integrated clock is an effective solution, where the high-frequency clock signal of the digital LDO is generated by the LDO's internal logic circuitry. This approach avoids digital I / O port overhead and eliminates the need for an additional high-frequency oscillator. Summary of the Invention

[0005] The technical problem this invention aims to solve is to address the shortcomings of existing technologies by proposing a clock generation circuit suitable for digital LDOs. This clock generation circuit is a highly reusable digital LDO clock generation circuit. The high-frequency clock is generated internally, eliminating the need for an external clock signal. The generated clock signal chain operates in a pipeline mode, automatically triggering the generation of the next module's working pulse after the previous module's signal processing is complete. This significantly accelerates circuit operation, reduces static power consumption, and avoids signal sampling errors caused by process-voltage-temperature (PVT) factors. The digital LDO circuit can achieve rapid transient response to different process angles and load variations.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a clock generation circuit suitable for digital LDO, including a startup module, a state comparison module and a clock stabilization module;

[0007] The startup module includes a first D flip-flop and a first driver. The reset signal terminal of the first D flip-flop and the input terminal of the first driver are connected to a startup signal. The input terminal of the first D flip-flop is connected to the power ground, and the output terminal of the first driver is connected to the clock input terminal of the first D flip-flop.

[0008] The state comparison module includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a second driver, a third driver, a fourth driver, a fifth driver, a first XOR gate, a second XOR gate, a third XOR gate, a fourth XOR gate, a first NOR gate, a second NOR gate, and a NAND gate. One input terminal of the first XOR gate and the input terminal of the second driver are connected to the first input terminal, and the output terminal of the second driver is connected to the other input terminal of the first XOR gate. Similarly, one input terminal of the second XOR gate and the input terminal of the third driver are connected to the second input terminal, and the output terminal of the third driver is connected to the other input terminal of the second XOR gate. One input terminal of the third XOR gate and... The input terminal of the fourth driver is connected to the third input terminal, and the output terminal of the fourth driver is connected to the other input terminal of the third XOR gate; one input terminal of the fourth XOR gate and the input terminal of the fifth driver are connected to the fourth input terminal, and the output terminal of the fifth driver is connected to the other input terminal of the fourth XOR gate; the output terminals of the first XOR gate and the second XOR gate are respectively connected to the two input terminals of the first NOR gate; the output terminals of the third XOR gate and the fourth XOR gate are respectively connected to the two input terminals of the second NOR gate; and the output terminals of the first NOR gate and the second NOR gate are respectively connected to the two input terminals of the NAND gate.

[0009] The clock stabilization module includes an OR gate, a sixth driver, an inverter, a third NOR gate, a second D flip-flop, and a seventh driver. The two inputs of the OR gate are connected to the outputs of the NAND gate and the first D flip-flop, respectively. The output of the OR gate is connected to the input of the sixth driver and one input of the third NOR gate, respectively. The output of the sixth driver is connected to the input of the inverter. The output of the inverter is connected to the other input of the third NOR gate. The output of the third NOR gate is connected to the clock input of the second D flip-flop. The input of the second D flip-flop is connected to the power supply. The reset signal of the second D flip-flop is connected to the input signal. The output of the second D flip-flop is connected to the input of the seventh driver. The clock signal generated by the output of the seventh driver is a high-frequency clock signal suitable for a digital LDO.

[0010] This invention provides a clock generation circuit suitable for digital LDOs. The startup module in the circuit serves as the startup signal for the entire circuit, generating the first clock to ensure that the circuit can start normally. The state comparison module compares the working states of the first, second, third, and fourth input terminals to determine whether the working states have changed, and generates a power-on signal. The clock stabilization module drives the second D flip-flop to generate the high-frequency clock signal required by the subsequent digital LDO circuit based on the clock signal generated by the inverting delay unit composed of the sixth driver and the inverter and the third NOR gate.

[0011] Compared with the prior art, the present invention has the following advantages:

[0012] (1) The clock frequency generated by the clock generation circuit of this invention is determined by the overall delay of the circuit. By comparing the states of the circuit before and after through the state comparison module, a high-frequency clock signal is automatically generated. The clock frequency can be as high as 300MHz, which can effectively enhance the transient response characteristics of the digital LDO circuit.

[0013] (2) The clock generation circuit of this invention uses a self-circulating method to control the operation of the digital LDO. The high-frequency clock is generated internally, eliminating the dependence of the digital LDO circuit on external clock signals. The generated clock signal chain automatically triggers the generation of the working pulse of the next module after the signal processing of the previous module is completed in a pipeline mode, which greatly speeds up the circuit operation, reduces the static power consumption of the circuit, and avoids the signal sampling error problem caused by PVT. Facing different process corners and different load changes, the digital LDO circuit can achieve fast transient response. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the clock generation circuit in the embodiment;

[0015] Figure 2 The image shows the clock characteristic curve of the clock generation circuit in the embodiment. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0017] Example 1 shows a clock generation circuit suitable for a digital LDO, such as... Figure 1 As shown, it includes a startup module, a status comparison module, and a clock stabilization module.

[0018] The startup module includes a first D flip-flop FF1 and a first driver BUF1. The reset signal terminal Set of the first D flip-flop FF1 and the input terminal of the first driver BUF1 are connected to the startup signal ST (i.e., the power-on signal). The input terminal D of the first D flip-flop FF1 is connected to the power ground. The output terminal of the first driver BUF1 is connected to the clock input terminal Clk of the first D flip-flop FF1.

[0019] The state comparison module includes a first input terminal P1, a second input terminal P2, a third input terminal P3, a fourth input terminal P4, a second driver BUF2, a third driver BUF3, a fourth driver BUF4, a fifth driver BUF5, a first XOR gate XOR1, a second XOR gate XOR2, a third XOR gate XOR3, a fourth XOR gate XOR4, a first NOR gate NOR1, a second NOR gate NOR2, and a NAND gate NAND. One input terminal of the first XOR gate XOR1 and the input terminal of the second driver BUF2 are connected to the first input terminal P1, and the output terminal of the second driver BUF2 is connected to the other input terminal of the first XOR gate XOR1. One input terminal of the second XOR gate XOR2 and the input terminal of the third driver BUF3 are connected to the second input terminal P2, and the output terminal of the third driver BUF3 is connected to the other input terminal of the second XOR gate XOR2. One input terminal; one input terminal of the third XOR gate XOR3 and the input terminal of the fourth driver BUF4 are connected to the third input terminal P3, and the output terminal of the fourth driver BUF4 is connected to the other input terminal of the third XOR gate XOR3; one input terminal of the fourth XOR gate XOR4 and the input terminal of the fifth driver BUF5 are connected to the fourth input terminal P4, and the output terminal of the fifth driver BUF5 is connected to the other input terminal of the fourth XOR gate XOR4; the output terminals of the first XOR gate XOR1 and the second XOR gate XOR2 are respectively connected to the two input terminals of the first NOR gate NOR1, the output terminals of the third XOR gate XOR3 and the fourth XOR gate XOR4 are respectively connected to the two input terminals of the second NOR gate NOR2, and the output terminals of the first NOR gate NOR1 and the second NOR gate NOR2 are respectively connected to the two input terminals of the NAND gate NAND.

[0020] The clock stabilization module includes an OR gate, a sixth driver BUF6, an inverter INV, a third NOR gate NOR3, a second D flip-flop FF2, and a seventh driver BUF7. The two inputs of the OR gate are connected to the output of a NAND gate and the output Q of the first D flip-flop FF1, respectively. The output of the OR gate is connected to the input of the sixth driver BUF6 and one input of the third NOR gate NOR3, respectively. The output of the sixth driver BUF6 is connected to the input of the inverter INV. The output of the inverter INV is connected to the other input of the third NOR gate NOR3. The output of the third NOR gate NOR3 is connected to the clock input D of the second D flip-flop FF2. The input D of the second D flip-flop FF2 is connected to the power supply V. DD The reset signal terminal Set of the second D flip-flop FF2 is connected to the input signal COM (which is the signal used to determine the completion of the comparator in the digital LDO). The output terminal Q of the second D flip-flop FF2 is connected to the input terminal of the seventh driver BUF7. The clock signal CLK generated by the output terminal of the seventh driver BUF7 is a high-frequency clock signal suitable for digital LDO.

[0021] Both the first D flip-flop FF1 and the second D flip-flop FF2 are rising-edge triggered D flip-flops.

[0022] During the operation of the clock generation circuit applicable to digital LDOs described above, a clock is generated by a change in the gate state of the power transistors. When the digital LDO is regulated, the output voltage continuously fluctuates around the reference voltage. After each comparison by the comparator, the control terminal adjusts the number of power transistors turned on according to the comparator's output signal. The change in the number of power transistors turned on generates a clock, which then drives the comparator to compare the difference between the reference voltage and the output voltage, thus forming a cycle, and the circuit continues to operate.

[0023] The clock generation circuit described above for digital LDOs uses a self-clocking method to control the operation of the digital circuits. The clock for the comparator is generated internally by the digital LDO circuit, eliminating the need for an external clock compared to static comparators and voltage-controlled oscillators, thus reducing static power consumption. The generated clock signal chain operates in a pipelined manner, triggering the generation of the working pulse for the next module after the signal processing of the previous module is complete. This significantly accelerates the circuit's operating speed, and changes in PVT only affect signal transmission delay, avoiding signal sampling errors.

[0024] The clock generation characteristic curves of the clock generation circuit applicable to the digital LDO are as follows: Figure 2As shown, the first clock is generated when the start signal ST changes from 0 to 1 upon power-up. The next clock is generated when the operating state of any of the four input terminals (P1, P2, P3, P4) changes. The clock frequency depends only on the circuit delay. With a power supply voltage of 0.6V, the interval from the input transition to clock generation is only 3ns, allowing for a clock frequency as high as 300MHz. This effectively enhances the transient response characteristics of the digital LDO and reduces the need for an external oscillator to generate the clock.

Claims

1. A clock generation circuit suitable for a digital LDO, characterized by, The starting module, the state comparison module and the clock stabilization module are included. The reset signal end of the first D flip-flop and the input end of the first driver are connected with the starting signal, the input end of the first D flip-flop is connected with the power supply ground, and the output end of the first driver is connected with the clock input end of the first D flip-flop. The first input end, the second input end, the third input end, the fourth input end, the second driver, the third driver, the fourth driver, the fifth driver, the first exclusive OR gate, the second exclusive OR gate, the third exclusive OR gate, the fourth exclusive OR gate, the first NOR gate, the second NOR gate and the NAND gate are included in the state comparison module, one input end of the first exclusive OR gate and the input end of the second driver are connected with the first input end, the output end of the second driver is connected with the other input end of the first exclusive OR gate, one input end of the second exclusive OR gate and the input end of the third driver are connected with the second input end, the output end of the third driver is connected with the other input end of the second exclusive OR gate, one input end of the third exclusive OR gate and the input end of the fourth driver are connected with the third input end, the output end of the fourth driver is connected with the other input end of the third exclusive OR gate, one input end of the fourth exclusive OR gate and the input end of the fifth driver are connected with the fourth input end, the output end of the fifth driver is connected with the other input end of the fourth exclusive OR gate, the output end of the first exclusive OR gate and the output end of the second exclusive OR gate are connected with two input ends of the first NOR gate respectively, the output end of the third exclusive OR gate and the output end of the fourth exclusive OR gate are connected with two input ends of the second NOR gate respectively, and the output end of the first NOR gate and the output end of the second NOR gate are connected with two input ends of the NAND gate respectively. The OR gate, the sixth driver, the inverter, the third NOR gate, the second D flip-flop and the seventh driver are included in the clock stabilization module, two input ends of the OR gate are connected with the output end of the NAND gate and the output end of the first D flip-flop respectively, the output end of the OR gate is connected with the input end of the sixth driver and one input end of the third NOR gate respectively, the output end of the sixth driver is connected with the input end of the inverter, the output end of the inverter is connected with the other input end of the third NOR gate, the output end of the third NOR gate is connected with the clock input end of the second D flip-flop, the input end of the second D flip-flop is connected with the power supply, the reset signal end of the second D flip-flop is connected with the input signal, the output end of the second D flip-flop is connected with the input end of the seventh driver, and the output end of the seventh driver generates the clock signal which is suitable for the high-frequency clock signal of the digital LDO.

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