A novel CRO circuit structure and its CRO PUF circuit

Abstract

The invention discloses a novel CRO circuit structure and a CRO PUF circuit thereof, wherein the CRO circuit structure comprises a NAND gate and 2n+1 two-way selectors; every two two-way selectors form a first-stage delay unit, and the remaining one two-way selector alone forms a last-stage delay unit, and a total of n+1 stages of delay units are provided; the NAND gate has two input ends, and the output end of the NAND gate is respectively connected to the data input ends of the two two-way selectors in the first-stage delay unit; the output ends of the two two-way selectors in the previous-stage delay unit are both connected to the input ends of the two two-way selectors in the next-stage delay unit; the output ends of the two two-way selectors of the nth-stage delay unit are both connected to the input ends of the two-way selectors of the last-stage delay unit; the output end of the two-way selectors of the last-stage delay unit is connected to the other input end of the NAND gate; wherein the configuration ends of the 2n+1 two-way selectors are respectively controlled by mutually independent configuration signals.

Description

Technical Field

[0001] The present invention relates to the technical field of configurable ring oscillator physical unclonable functions (CRO PUFs), and more specifically, to a novel CRO circuit structure and its CRO PUF circuit. Background Art

[0002] With the continuous popularization of the Internet of Things, more and more electronic devices are connected to the Internet of Things as network nodes. Such development brings convenience to society while also hiding risks. Limited by the response speed and computing resources of device nodes, Internet of Things nodes, especially simple nodes, often lack security protection measures, and these types of nodes are easily potential attack entry points in the Internet of Things.

[0003] Currently, mainstream traditional cryptographic algorithms consume a large amount of resources. Common security encryption algorithms such as ECC (Elliptic Curve Cryptography) and HASH (Hash Algorithm) all require the consumption of more hardware resources and occupy the performance of the node processor, which is a huge burden for simple nodes. Physical unclonable functions are implemented through independent hardware, do not require excessive consumption of the node processor performance, and at the same time, due to their unclonable characteristics, they can effectively protect parameters involved in encryption such as keys or important parameters involved in key generation.

[0004] The earliest ring oscillator physical unclonable function (RO PUF) was proposed by Suh et al., and its most basic structure is as Figure 1 shown. A complete RO PUF consists of two oscillator branches. Each branch is obtained by connecting an odd number of inverters in series with the same quantity. Subsequently, the oscillation signals output by each ring oscillator are respectively counted by a counter, and finally the obtained count values are compared to obtain a one-bit output. It can be found that this structure is fixedly immutable. A complete ROPUF only outputs a one-bit fixed signal, with a large hardware resource cost. To solve this problem, the concept of configurability was proposed. Figure 2 The simplest configuration method is shown as follows. All oscillation rings are regarded as options, and each time two branches are selected through a multiplexer for comparison to obtain the output. Compared with Figure 1 in the structure of n branches, Figure 2 the number of output bits of the Figure 3 method is increased by n - 1 times compared to the original. In 2011, Maiti and Schaumont proposed the configurable RO PUF circuit structure shown asFigure 4 As shown, based on Figure 3 , one inverter in each basic unit is directly reduced. While reducing hardware resources, stability is increased. However, it should be noted that for this structure, the number of cascaded inverters cannot be an even number, so half of the configurations are useless. In 2017, Pang Zihan proposed a cross-reconfigurable RO PUF circuit, and its circuit structure is as shown in Figure 5 . It further increases the number of circuit reconfigurations and further raises the optional range of the next stage of the inverter to the number of rows n. However, this module has many limiting conditions. First, the inverters at both ends must be in the same row, and the number of inverters must be odd. In addition, due to the large number of inverters involved, the ring oscillator will inevitably cross different CLBs (configurable logic blocks) during layout and routing. Thus, the existing structures cannot overcome the condition limitation of an odd number of inverters, reducing the scalability of the ROPUF. SUMMARY OF THE INVENTION

[0005] The present invention provides a novel CRO circuit structure and its CRO PUF circuit to solve the problem of the condition limitation that the number of inverters in the above traditional RO-PUF circuit must be odd. Compared with the traditional structure, it not only eliminates the limitation of an odd number of inverters but also improves the configurable number and increases the number of stimulus-response pairs on the premise of consuming the same amount of hardware resources.

[0006] To achieve the above object of the present invention, the following technical solutions are adopted:

[0007] A novel CRO circuit structure includes 1 NAND gate and 2n + 1 two-way selectors; where every 2 two-way selectors form one stage of delay unit, and the remaining 1 two-way selector alone forms the last stage of delay unit, with a total of n + 1 stages of delay units, where n is a positive integer;

[0008] The NAND gate has two input terminals and one output terminal. One of the input terminals is used to input the enable signal en, and the output terminal of the NAND gate is respectively connected to the data input terminals of the two two-way selectors in the first stage of delay unit;

[0009] The output terminals of the two two-way selectors in the previous stage of delay unit are both connected to the input terminals of the two two-way selectors in the next stage of delay unit;

[0010] The output terminals of the two two-way selectors in the nth stage of delay unit are both connected to the input terminals of the two-way selector in the last stage of delay unit;

[0011] The output terminal of the two-way selector in the last stage of delay unit is connected to the other input terminal of the NAND gate;

[0012] Among them, the configuration terminals of the 2n + 1 two-way selectors are respectively controlled by independent configuration signals.

[0013] Preferably, when the enable signal en is at a high level, the NAND gate degenerates into an inverter, and the CRO circuit structure forms an oscillation loop to output an oscillation signal; when the enable signal en is at a low level, the inverter fixedly outputs a high level, and the oscillation loop stops oscillating and is in a sleep state.

[0014] Furthermore, two of the two-way selectors in the first n delay units are respectively defined as the first two-way selector and the second two-way selector;

[0015] The first two-way selector of the previous-level delay unit is respectively connected to the high-level input terminal of the first two-way selector and the low-level input terminal of the second two-way selector of the next-level delay unit;

[0016] The second two-way selector of the previous-level delay unit is respectively connected to the low-level input terminal of the first two-way selector and the high-level input terminal of the second two-way selector of the next-level delay unit, thereby forming a cross output;

[0017] The first two-way selector of the nth-level delay unit is connected to the high-level input terminal of the two-way selector of the last-level delay unit;

[0018] The second two-way selector of the nth-level delay unit is connected to the low-level input terminal of the two-way selector of the last-level delay unit.

[0019] Still further, the level states of the configuration signals of the two two-way selectors of the previous-level delay unit determine the signal sources of the two two-way selectors of the next-level delay unit;

[0020] When the configuration signals of the two two-way selectors of the previous-level delay unit are both at a high level, the signal input to the high-level input terminal of the two-way selector of this level is output from the output terminal and input to the next-level delay unit;

[0021] When the configuration signals of the two two-way selectors of the previous-level delay unit are both at a low level, the signal input to the low-level input terminal of the two-way selector of this level is output from the output terminal and input to the next-level delay unit;

[0022] According to the level state of the configuration signal of the last-level delay unit, the signal source fed back to the NAND gate is determined.

[0023] A novel CRO PUF circuit includes N of the novel CRO circuit structures, and the configuration signals of each novel CRO circuit structure are independent of each other; it also includes 2 frequency counters and 1 sampling counter; N is a positive integer greater than or equal to 2;

[0024] When the enable signal en is at a high level, an oscillation signal is output, and the output oscillation signal is used as the input of the frequency counter clock terminal;

[0025] Different oscillation signals are counted by different frequency counters;

[0026] When the highest bit of one of the frequency counters flips, the lock signal is at a high level, and the lock signal immediately locks the state of the entire CRO PUF circuit;

[0027] When the lock signal is at a high level and is valid, the sampling counter is further started to perform subsequent sampling processes.

[0028] Preferably, the sampling counter provides two signals:

[0029] The first signal is when the second highest bit flips to a high level, providing a sampling signal. During the period when the second highest bit is at a high level, the sampling signal synchronously maintains a high level, and compares the saved frequency count value during the valid period of the sampling signal, performs a unique sampling, and saves it to the next level D flip-flop;

[0030] The second signal is when the highest bit of the sampling counter flips to a high level, providing a circuit reset signal. The circuit reset signal resets the frequency counter and the sampling counter to zero, and pulls down the lock signal to release the lock state. Then different configuration signals are input in sequence to obtain more bit outputs.

[0031] Furthermore, the sampling process is specifically manifested as follows:

[0032] First, the count value of the frequency counter is locked, and then the count value is compared to determine whether the output one-bit signal value is 1 or 0; at the same time, the locking signal starts the sampling counter. When the sampling counter counts to the second highest bit flip, a sampling signal is output. During the period when the second highest bit of the sampling counter is high, the sampling signal is continuously pulled high. During the period when the sampling signal is continuously pulled high, the generated output signal will only be sampled once;

[0033] When the sampling counter counts to the highest bit and flips to a high level, the sampling is completed and the output data is saved in the trigger at the output end; therefore, the two frequency counters are reset and cleared, and the reset and clearing of the frequency counter will further pull down the lock signal to a low level.

[0034] Furthermore, locking the state of the entire CRO PUF circuit specifically includes two operations: stopping the oscillation of each new CRO circuit structure and saving the count values ​​of the two counters.

[0035] Furthermore, the frequency counter is constructed using a 13-bit D flip-flop.

[0036] Furthermore, it also includes two multiplexers;

[0037] The selected signal of each multiplexer is the oscillation signal output by all new CRO circuit structures;

[0038] Each of the multiplexers is used to select one from M candidate oscillation signals as the output of two multiplexers respectively; M is a positive integer less than N;

[0039] The oscillation signal output of each multiplexer is used as the input of the clock terminal of the lower frequency counter, and the frequency counter counts the output oscillation signal at the same time.

[0040] The beneficial effects of the present invention are as follows:

[0041] Based on the two-way gate, the present invention constructs a new CRO circuit structure, and then constructs a new CRO PUF circuit.

[0042] The novel CRO circuit structure designed by the present invention has only one NAND gate to provide signal flipping operation, which is not limited by the number of inverters and improves the flexibility of circuit configuration.

[0043] In the present invention, according to the number n of two-way gates constituting the oscillating ring, the following reconstruction number m formula can be obtained: m = 2 n , compared with the traditional mechanism, under the same hardware resource consumption, the number of reconfigurable circuits is greatly increased, and more stimulus-response pairs can be generated.

[0044] The circuit structure involved in counting, comparing and sampling the frequency in the present invention is simple, consumes less resources and has good stability. Brief Description of the Figures

[0045] Figure 1 It is the simplest RO PUF circuit in the prior art.

[0046] Figure 2 This is a RO PUF circuit in the prior art n-choose-1 mode.

[0047] Figure 3 It is a fourth-order configurable RO PUF circuit in the prior art.

[0048] Figure 4 It is a prior art inverter-level configurable RO PUF circuit.

[0049] Figure 5 It is a cross-reconfigurable RO PUF circuit in the prior art.

[0050] Figure 6It is the circuit diagram of the novel CRO circuit structure of the present invention.

[0051] Figure 7 It is the connection diagram when the configured signal of the present invention is 1010110.

[0052] Figure 8 It is the connection diagram when the configured signal of the present invention is 0010111.

[0053] Figure 9 It is the schematic diagram of the LUT insertion of the oscillator by the EDA tool.

[0054] Figure 10 It is the circuit diagram of the novel CRO PUF circuit of the present invention.

[0055] Figure 11 It is the circuit diagram of the novel CRO PUF circuit with multi-bit output of the present invention. Detailed implementation manners

[0056] The present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0057] Embodiment 1

[0058] According to the condition limitation of the odd number of inverters stored in the traditional RO PUF and the device characteristics of the CRO PUF implemented on the FPGA in this embodiment, the following novel CRO circuit structure is proposed:

[0059] As Figure 6 shown, a novel CRO circuit structure includes 1 NAND gate and 2n + 1 two-way selectors; among them, every 2 two-way selectors form one-stage delay unit, and the remaining 1 two-way selector alone forms the last-stage delay unit, with a total of n + 1 delay units, where n is a positive integer;

[0060] The NAND gate has two input terminals and one output terminal. One of the input terminals is used to input the enable signal en, and the output terminal of the NAND gate is respectively connected to the data input terminals of the two two-way selectors in the first-stage delay unit;

[0061] The output terminals of the two two-way selectors in the previous-stage delay unit are both connected to the input terminals of the two two-way selectors in the next-stage delay unit;

[0062] The output terminals of the two two-way selectors in the nth-stage delay unit are both connected to the input terminal of the two-way selector in the last-stage delay unit;

[0063] The output terminal of the two-way selector in the last-stage delay unit is connected to the other input terminal of the NAND gate;

[0064] Among them, the configuration terminals of the 2n + 1 two-way selectors are respectively controlled by independent configuration signals.

[0065] As Figure 6 shown, it is a single oscillation loop. The oscillation loop provides a configurable structure inside. Among them, the NAND gate provides the oscillation loop enable signal en, and at the same time serves as a delay unit to provide signal delay. The delay it provides is mainly reflected in the comparison with other oscillation loops. Under different configuration signals of the same oscillation loop structure, the delay provided by the NAND gate has no effect. Most importantly, the NAND gate is the only device in the new CRO circuit structure that can make the signal oscillate.

[0066] In a specific embodiment, the NAND gate has two inputs. One is the enable signal en. When the enable signal en is at a high level, the NAND gate degrades into an inverter, and the CRO circuit structure forms an oscillation loop to output an oscillation signal. When the enable signal en is at a low level, the inverter fixedly outputs a high level, and the oscillation loop no longer oscillates and is in a dormant state.

[0067] In a specific embodiment, two two-way selectors in the first n delay units are respectively defined as the first two-way selector and the second two-way selector;

[0068] The first two-way selector of the previous-level delay unit is respectively connected to the high-level input terminal of the first two-way selector and the low-level input terminal of the second two-way selector of the next-level delay unit;

[0069] The second two-way selector of the previous-level delay unit is respectively connected to the low-level input terminal of the first two-way selector and the high-level input terminal of the second two-way selector of the next-level delay unit, thus forming a cross output;

[0070] The first two-way selector of the nth-level delay unit is connected to the high-level input terminal of the two-way selector of the last-level delay unit;

[0071] The second two-way selector of the nth-level delay unit is connected to the low-level input terminal of the two-way selector of the last-level delay unit.

[0072] In a specific embodiment, the level states of the configuration signals of the two two-way selectors of the previous-level delay unit determine the signal sources of the two two-way selectors of the next-level delay unit;

[0073] When the configuration signals of the two two-way selectors of the previous-level delay unit are both at a high level, the signal input to the high-level input terminal of the two-way selector of this level of delay unit is output from the output terminal and input to the next-level delay unit;

[0074] When the configuration signals of the two two-way multiplexers in the previous delay unit are both at low level, the signal at the low-level input terminal of the two-way multiplexer input to this level of delay unit is output from the output terminal and input to the next-level delay unit;

[0075] According to the level state of the configuration signal of the last-level delay unit, the signal source fed back to the NAND gate is determined.

[0076] In this embodiment, the output terminal of the NAND gate is connected to the first two-way multiplexer and the second two-way multiplexer in the first-level delay unit of the configurable delay structure. As Figure 6 shown, the configuration terminals of the first two-way multiplexer and the second two-way multiplexer are controlled by the configuration signals S1 and S2 respectively. When the configuration signal S1 is at high level, the output signal of the inverter sent to the corresponding high-level port is selected and then used as the input of the next-level two-way multiplexer. When the configuration signal S1 is at low level, the output signal of the inverter sent to the corresponding low-level port is selected and then output to the input terminal of the next-level two-way multiplexer. The same applies to the second two-way multiplexer input terminal.

[0077] As Figure 6 shown, the output terminal of the first two-way multiplexer of the first-level delay unit is connected to the high-level input terminal of the first two-way multiplexer of the second-level delay unit and the low-level input terminal of the second two-way multiplexer of the second-level delay unit. The output terminal of the second two-way multiplexer of the first-level delay unit is connected to the low-level input terminal of the first two-way multiplexer of the second-level delay unit and the high-level input terminal of the second two-way multiplexer of the second-level delay unit. Thus, the next-level delay unit forms a cross output according to this connection relationship.

[0078] According to the level states of the configuration signals S3 and S4, the signal source output to the two-way multiplexer of the third level can be determined. When S3 and S4 are at high level, the signal at the high-level input terminal of the first two-way multiplexer of the second-level delay unit will be output. Similarly, since the configuration signal of the first two-way multiplexer of the second-level delay unit is the same as that of the first two-way multiplexer of the second-level delay unit, the signal at the high-level input terminal of the second two-way multiplexer of the second-level delay unit will be output. When S3 and S4 are at low level, the signal at the low-level input terminal of the first two-way multiplexer of the second-level delay unit will be output, and the signal at the low-level input terminal of the second two-way multiplexer of the second-level delay unit will be output.

[0079] Compared with the above-mentioned traditional RO circuit structure, the novel CRO circuit structure in this embodiment has no excessive restrictions on the input excitation, does not need to consider the odd-even number ratio of inverters, and can respond to any input excitation. This embodiment takes the 4-level single-inverter CRO circuit structure as an example:

[0080] When the input configuration signals are S1 = 1, S2 = 0, S3 = 1, S4 = 0, S5 = 1, S6 = 1, S7 = 0, the connection situation is as follows Figure 7 as shown

[0081] When the input configuration signals are S1 = 0, S2 = 0, S3 = 1, S4 = 0, S5 = 1, S6 = 1, S7 = 1, the connection situation is as Figure 8 shown

[0082] Considering that it needs to be implemented based on a field - programmable gate array (FPGA), the involved two - way selectors, inverters, NAND gates, etc. are all implemented by look - up tables (LUTs). As Figure 9 shown, if the candidate channel signals of the two - way selector all come from the same signal source, the electronic design automation (EDA) tool will automatically insert LUTs, causing unnecessary resource consumption. Therefore, in this embodiment, two two - way selectors are first used to construct the most basic configurable unit, and each configurable unit is a delay unit in an oscillator ring, and is cross - connected to the next - level delay unit. In this way, since the signals of the candidate channels of each two - way selector come from different signals, it can be ensured that no extra LUTs will be inserted when implemented on the FPGA. The specific structure is shown in Figure 6 .

[0083] Embodiment 2

[0084] Since the novel CRO circuit structure of Embodiment 1 cannot yet be called a physically unclonable function circuit, but is the core module of the CRO PUF circuit. To construct the corresponding CRO PUF circuit, it is also necessary to quantify the oscillation frequency of the above - mentioned oscillator ring and then obtain a 1 - bit output after comparison. The specific scheme is as follows:

[0085] As Figure 10 shown, a novel CRO PUF circuit includes N of the above - mentioned novel CRO circuit structures. The configuration signals of each novel CRO circuit structure are independent of each other to ensure the maximum time - delay difference, guarantee the stability of the output, and when the enable signal en is high - level valid, an oscillation signal is output; it also includes 2 frequency counters and 1 sampling counter; where N is a positive integer greater than or equal to 2;

[0086] When the enable signal en is high - level, an oscillation signal is output, and the output oscillation signal is used as the input of the clock terminal of the frequency counter;

[0087] Different oscillation signals are counted by different frequency counters;

[0088] When the most - significant bit of one of the frequency counters flips, the lock signal is at a high level, and this lock signal immediately locks the state of the entire CRO PUF circuit;

[0089] When the lock signal is at a high level and is valid, the sampling counter is further started to perform subsequent sampling processes.

[0090] In a specific embodiment, the sampling counter provides two signals:

[0091] The first signal is when the second highest bit flips to a high level, providing a sampling signal. During the period when the second highest bit is at a high level, the sampling signal synchronously maintains a high level, and compares the saved frequency count value during the valid period of the sampling signal, performs a unique sampling, and saves it to the next level D flip-flop;

[0092] The second signal is when the highest bit of the sampling counter flips to a high level, providing a circuit reset signal. The circuit reset signal resets the frequency counter and the sampling counter to zero, and pulls down the lock signal to release the lock state. Then different configuration signals are input in sequence to obtain more bit outputs.

[0093] In a specific embodiment, the sampling process is specifically manifested as follows:

[0094] First, the count value of the frequency counter is locked, and then the count value is compared to determine whether the output one-bit signal value is 1 or 0; at the same time, the locking signal starts the sampling counter. When the sampling counter counts to the second highest bit flip, a sampling signal is output. During the period when the second highest bit of the sampling counter is at a high level, the sampling signal is continuously pulled high. During the period when the sampling signal is continuously pulled high, the generated output signal will only be sampled once;

[0095] When the sampling counter counts to the highest bit flipped to a high level, the sampling is completed and the output data has been saved in the trigger at the output end; therefore, the two frequency counters are reset and cleared, and the reset and clearing of the frequency counters will further pull the lock signal down to a low level; the comparison results obtained after the comparison operation are spliced ​​to obtain a physical unclonable function sequence, for example, if frequency 1> frequency 2, then the output is 1, otherwise the output is 0.

[0096] In a specific embodiment, the frequency counter is composed of a 13-bit D flip-flop. In order to reduce the complexity of the circuit and improve the stability of the circuit, the D flip-flop group of the frequency counter does not use a high-frequency clock signal to count the oscillation signal, but uses the output oscillation signal of the single-phase inverter CRO circuit in Example 1 as the input of the clock end of the frequency counter. When the highest bit of one of the frequency counters flips, the lock signal is at a high level. The lock signal immediately locks the state of the entire circuit module, including stopping the oscillation of the single-phase inverter CRO circuit and saving the count values ​​of the two counters.

[0097] At this point, a one-bit CRO PUF response signal is obtained. Figure 9 The figure shows the most basic CRO PUF circuit that can generate one-bit output based on the new single-phase inverter CRO circuit in Example 1. The number of oscillation circuits can be increased according to actual needs, and the branches used for comparison can be selected through two multiplexers, and the output of the multiplexer is the oscillation signal to be compared.

[0098] The key technology of this embodiment is a novel single-phase inverter CRO circuit for realizing a physically unclonable function, a method for comparing the output signal oscillation frequencies of different novel single-phase inverter CRO circuit structures, and a sampling method for the effective signal obtained after the comparison.

[0099] Comparison of different oscillation signals. In this embodiment, the frequency is counted, and the oscillation signal to be compared is used as the input of the clock end of the frequency counter. When the highest bit of the frequency counter is flipped, a signal lock is provided, and then the current frequency count value is saved and compared with its numerical value.

[0100] For sampling of valid signals. This embodiment starts the sampling counter during the period when the lock signal is valid, and performs sampling when the second highest bit of the sampling counter flips to a high level. The valid signal is read by the D flip-flop, and is reset when the second highest bit flips to a high level, and the valid output signal is set to zero.

[0101] Example 3

[0102] Based on Example 2, this embodiment can increase the number of oscillation circuits according to actual needs, by using two multiplexers to select the branches for comparison, and the output of the multiplexer is the oscillation signal to be compared.

[0103] If Figure 11 As shown, an example of a new single inverter CRO PUF circuit with more branch selections is given. In this embodiment, a complete new single inverter CRO PUF circuit includes: N new single inverter CRO circuit structures, two multiplexers, two frequency counters, and a sampling counter; the selected signal of each multiplexer is an oscillation signal output by all the new single inverter CRO circuit structures. In actual use, according to the selection signals of the two multiplexers, the multiplexer selects one from the M candidate oscillation signals as the output of the two multiplexers, and inputs it into the lower-level circuit for counting. Among them, M is a positive integer less than N. The oscillation signal output of each multiplexer is used as the input of the clock end of the lower-level frequency counter, and the output oscillation signal is counted by the frequency counter at the same time. When the high bit of the frequency counter flips to a high level, a locking signal is provided. At this time, the locking signal continues to be a high level, and while locking the count value of the frequency counter, the adoption counter is started.

[0104] The signals available for configuration include the strobe signals of all the two-way selectors in each new single-inverting CRO circuit structure. In this embodiment, a new single-inverting CRO circuit composed of 7 two-way selectors is adopted, so there are 7*N two-way strobe signals. In addition, there are M branches available for selection. Therefore, the number of configuration signals selected for each branch should be Therefore, the total number of reconstruction numbers is 7*N*M*(M - 1). For a more general case, each new single-inverting CRO circuit is composed of 2n + 1 two-way selectors, and the specific number is determined by the user according to needs. Therefore, in this embodiment, the configurable number is: (2n + 1)*N*M*(M - 1).

[0105] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A new CRO circuit structure, characterized in that: It includes 1 NAND gate and 2n+1 two-way gates; wherein every two two-way gates form a first-stage delay unit, and the remaining one two-way gate alone forms a last-stage delay unit, and a total of n+1 stages of delay units are provided, wherein n is a positive integer; The NAND gate has two input terminals and one output terminal, wherein one input terminal is used to input an enable signal en, and the output terminal of the NAND gate is respectively connected to the data input terminals of two two-way selectors in the first-stage delay unit; The output ends of the two two-way gates in the previous delay unit are connected to the input ends of the two two-way gates in the next delay unit; The output ends of the two two-way gates of the n-th delay unit are both connected to the input ends of the two-way gate of the last delay unit; The output end of the two-way selector of the last-stage delay unit is connected to the other input end of the NAND gate; The configuration terminals of the 2n+1 two-way gates are controlled by independent configuration signals. Specifically, the two two-way gates in the first n delay units are defined as a first two-way gate and a second two-way gate respectively; The first two-way gate of the previous delay unit is connected to the high level input end of the first two-way gate and the low level input end of the second two-way gate of the next delay unit respectively; The second two-way gate of the previous delay unit is respectively connected to the low level input end of the first two-way gate and the high level input end of the second two-way gate of the next delay unit, so as to form a cross output; The first two-way gate of the n-th delay unit is connected to the high level input end of the two-way gate of the last delay unit; The second two-way gate of the n-th stage delay unit is connected to the low level input end of the two-way gate of the last stage delay unit.

2. The novel CRO circuit structure according to claim 1 is characterized in that: When the enable signal en is at a high level, the NAND gate degenerates into an inverter, and the CRO circuit structure forms an oscillation ring to output an oscillation signal; when the enable signal en is at a low level, the inverter outputs a fixed high level, and the oscillation ring no longer oscillates and is in a dormant state.

3. The novel CRO circuit structure according to claim 2 is characterized in that: The level state of the configuration signal of the two two-way gates of the previous delay unit determines the signal source of the two two-way gates of the next delay unit; When the configuration signals of the two two-way gates of the previous delay unit are both high level, the signal input to the high level input end of the two-way gate of the delay unit of this level is output from the output end and input to the next delay unit; When the configuration signals of the two two-way gates of the previous delay unit are both at low level, the signal input to the low level input end of the two-way gate of the delay unit of this level is output from the output end and input to the next delay unit; The source of the signal fed back to the NAND gate is determined according to the level state of the configuration signal of the last-stage delay unit.

4. A novel CRO PUF circuit, characterized in that: The method comprises N novel CRO circuit structures as claimed in any one of claims 1 to 3, wherein the configuration signals of each novel CRO circuit structure are independent of each other; further comprising 2 frequency counters and 1 sampling counter; N is a positive integer greater than or equal to 2; When the enable signal en is at a high level, an oscillation signal is output, and the output oscillation signal is used as the input of the frequency counter clock terminal; Different oscillation signals are counted by different frequency counters; When the highest bit of one of the frequency counters flips, the lock signal is at a high level, and the lock signal immediately locks the state of the entire CRO PUF circuit; When the lock signal is at a high level and is valid, the sampling counter is further started to perform subsequent sampling processes.

5. The novel CRO PUF circuit according to claim 4, characterized in that: The sampling counter provides two signals: The first signal is that when the second highest bit flips to a high level, a sampling signal is provided. During the period when the second highest bit is at a high level, the sampling signal is synchronously maintained at a high level, and the saved frequency count value is compared during the valid period of the sampling signal, and a unique sampling is performed and saved to the next level D flip-flop; The second signal is a circuit reset signal provided when the highest bit of the sampling counter flips to a high level. The circuit reset signal resets the frequency counter and the sampling counter to zero, and pulls down the lock signal to release the lock state. Subsequently, different configuration signals are input in sequence to obtain more bit outputs.

6. The novel CRO PUF circuit according to claim 5, characterized in that: The sampling process is specifically manifested as follows: First, the count value of the frequency counter is locked, and then the count value is compared to determine whether the output one-bit signal value is 1 or 0; at the same time, the locking signal starts the sampling counter, and when the sampling counter counts to the second highest bit flip, a sampling signal is output. During the period when the second highest bit of the sampling counter is at a high level, the sampling signal is continuously pulled high. During the period when the sampling signal is continuously pulled high, the generated output signal will only be sampled once; When the sampling counter counts to the highest bit flipped to a high level, the sampling is completed and the output data is saved in the trigger at the output end; therefore, the two frequency counters are reset and cleared, and the reset and clearing of the frequency counters will further pull down the lock signal to a low level.

7. The novel CRO PUF circuit according to claim 5, characterized in that: Locking the state of the entire CRO PUF circuit specifically includes two operations: stopping the oscillation of each new CRO circuit structure, and saving the count values ​​of two counters.

8. The novel CRO PUF circuit according to claim 7, characterized in that: The frequency counter is constructed using a 13-bit D flip-flop.

9. The novel CRO PUF circuit according to claim 7, characterized in that: Also included are two multiplexers; The selected signal of each multiplexer is the oscillation signal output by all the new CRO circuit structures; Each of the multiplexers is used to select one of the M candidate oscillation signals as the output of the two multiplexers respectively; M is a positive integer less than N; The oscillation signal output of each multiplexer is used as the input of the clock terminal of the lower frequency counter, and the frequency counter counts the output oscillation signals simultaneously.

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