A multi-functional flash memory test rack based on multiple test ports

Abstract

An embodiment of the present invention relates to a multi-functional flash memory test rack based on multiple test ports, comprising: a mobile terminal, a flash memory test device, and multiple test connection terminals; the mobile terminal is used to control the operation of the flash memory test device; the test connection terminals are used to connect to the flash memory storage device to be tested; the flash memory test device is used to perform performance tests on the flash memory storage devices to be tested connected to each test connection terminal. By providing test connection terminals for the flash memory storage devices to be tested on the flash memory test device, and then performing performance tests on different types of flash memory storage devices to be tested through the flash memory test device, the multi-functional flash memory test rack can realize performance tests on different flash chips. Compared with the existing method of manufacturing a flash memory test rack for one type of flash chip, it can reduce the cost of manufacturing flash memory test racks for manufacturers, broaden the compatibility of the products tested by the multi-functional flash memory test rack, and make the multi-functional flash memory test rack based on multiple test ports more applicable.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory testing, and in particular, to a multi-functional flash memory test rack based on multiple test ports. Background Art

[0002] The advantage of flash memory is the fast speed of storing a large amount of data. A flash memory test rack is a tool for testing indicators such as the quality, performance, and lifespan of flash memory. In addition to the above functions, a flash memory test rack can also be used as a flash memory speed measurement tool. When an enterprise intends to purchase a batch of flash memories for manufacturing flash memory-based storage devices such as solid-state drives or USB flash drives, if there is a flash memory test rack for a certain main control solution, it can conveniently perform speed, stability, and aging tests on various flash memories paired with this main control. This is an essential tool in the testing process of each storage manufacturer.

[0003] Flash memory test racks are currently widely used in companies that produce storage products. When an enterprise purchases a batch of flash memories for manufacturing flash memory-based storage devices such as solid-state drives or USB flash drives, the purchased flash memories need to be tested using a test rack before being used in production. The main test objects of flash memory test racks are downgraded chips, white chips, black chips, or second-hand disassembled chips. Since wafers with a capacity below 93% are no longer marked with the original factory logo for sale, these wafers are not discarded either, but flow into the packaging factory or the black chip market to become black chips. Especially for QLC or TLC particles, their production cost per million bytes is currently the lowest, but their lifespan is short, and the stability and yield rate of black chips are very poor, and they must be tested before use.

[0004] Currently, flash memory test racks can be purchased through various channels on the market. However, looking at the entire market, flash memory test racks have some drawbacks: expensive, single main control and compatibility. For example, a solid-state drive flash memory test rack based on SM2256K can be found on a certain online shopping website at a price of over 500 yuan, and a USB flash drive flash memory test rack based on Innostor IS903 also costs about 150 yuan. This is mainly because most factories produce flash memory test racks for their own use and rarely sell them externally. This will cause difficulties for many electronic DIY players and some manufacturers without R & D capabilities when producing storage products, or increase a lot of unnecessary costs. At the same time, although there are a wide variety of flash memory test racks on the market, their main controls are all single. If a certain manufacturer needs to produce storage devices with multiple main control solutions, then it is necessary to produce or purchase corresponding flash memory test racks for various solutions simultaneously, increasing costs. Summary of the Invention

[0005] The embodiments of the present invention provide a multi-functional flash memory test rack based on multiple test ports, which is used to solve the technical problems that the existing flash memory test racks are expensive, have a single main control and compatibility, and cannot provide general applicability.

[0006] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0007] A multi-functional flash memory test rack based on multiple test ports, comprising a mobile terminal, a flash memory test device, and a plurality of test connection ends. The mobile terminal is connected to the flash memory test device, and the plurality of test connection ends are arranged on the flash memory test device;

[0008] The mobile terminal is used to control the operation of the flash memory test device;

[0009] The test connection end is used to connect to the flash memory storage device to be tested;

[0010] The flash memory test device is used to perform performance tests on the flash memory storage devices to be tested connected to each of the test connection ends;

[0011] Among them, the performance test at least includes flash memory speed, flash memory stability, and aging performance.

[0012] Preferably, the flash memory test device includes a control board and a flash memory test circuit arranged on the control board. The flash memory test circuit includes a first test circuit, a second test circuit, and a third test circuit connected to the test connection end. The first test circuit is respectively connected to the second test circuit and the third test circuit through a connection interface. The first test line includes a control chip connected to the test connection end, and a GANG module, an SPI module, a power supply module, and a protection module connected to the control chip;

[0013] The control chip is used to control the operation of the GANG module, the SPI module, and the protection module;

[0014] The GANG module is used to detect the state of the control chip;

[0015] The SPI module is used to connect to an SPI chip to perform fixed updates for an external SPI;

[0016] The power supply module is used to supply power to at least the control chip, the GANG module, the SPI module, and the protection module, and is also used to provide different power supplies according to the flash memory storage devices to be tested connected to the test connection end;

[0017] The protection module is used to perform ESD protection on the control chip.

[0018] Preferably, the power supply module includes a power supply switch protection sub-module, a first power supply sub-module, and a second power supply sub-module connected to the control chip;

[0019] The power supply switch protection sub-module is used to conduct the spike voltage generated when the switch is closed to the ground to protect the control chip;

[0020] The first power supply sub-module is used to provide a power supply with a voltage of 3.3V;

[0021] The second power supply sub-module is used to provide a power supply with a voltage of 1.2V.

[0022] Preferably, the power supply switch protection sub-module includes a switch element connected to the control chip, a fuse element connected to the switch element, and a TVS tube connected to the fuse element.

[0023] Preferably, the power supply module includes a power supply mode sub-module for configuring different power supply modes, and the power supply mode sub-module is connected to the control chip.

[0024] Preferably, the first test circuit includes a reset module connected to the control chip, and the reset module is used to power on and reset the control chip.

[0025] Preferably, the first test circuit includes a crystal oscillator module connected to the control chip, and the crystal oscillator module is used to ensure the normal and stable operation of the control chip; an external load capacitor is provided on the crystal oscillator module.

[0026] Preferably, the control board is a four-layer stacked PCB board, the distance between the vias and signal lines of the PCB board is less than 3 cm, and the line width of the signal lines of the PCB board is 5.65 mil.

[0027] Preferably, the second test circuit includes a second control chip connected to the interface of the control chip.

[0028] Preferably, the third test circuit includes a third control chip connected to the interface of the control chip.

[0029] As can be seen from the above technical solutions, the embodiments of the present invention have the following advantages: The multi-functional flash memory test rack based on multiple test ports provided by the embodiments of the present application includes a mobile terminal, a flash memory test device, and multiple test connection terminals. The mobile terminal is connected to the flash memory test device, and the multiple test connection terminals are arranged on the flash memory test device; the mobile terminal is used to control the operation of the flash memory test device; the test connection terminal is used to connect to the flash memory storage device to be tested; the flash memory test device is used to perform performance tests on the flash memory storage devices to be tested connected to each test connection terminal. The multi-functional flash memory test rack based on multiple test ports sets test connection terminals for the flash memory storage devices to be tested on the flash memory test device, and then performs performance tests on the flash memory storage devices to be tested connected to each test connection terminal through the flash memory test device. Among them, the flash memory storage devices to be tested connected to each test connection terminal can be different types of flash memory storage devices to be tested, realizing performance tests on different flash chips. Compared with the existing method of making a flash memory test rack for one type of flash chip, it can reduce the cost of manufacturers making flash memory test racks, broaden the compatibility of the products tested by the multi-functional flash memory test rack based on multiple test ports, make the multi-functional flash memory test rack based on multiple test ports more applicable, and solve the technical problems of the existing flash memory test racks being expensive, having a single main control and compatibility, and not providing general applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a framework diagram of the multi-functional flash memory test rack based on multiple test ports described in the embodiments of the present application;

[0032] Figure 2 It is a framework diagram of the flash memory test device of the multi-functional flash memory test rack based on multiple test ports described in another embodiment of the present application;

[0033] Figure 3 It is a circuit schematic diagram of the first test circuit of the multi-functional flash memory test rack based on multiple test ports described in the embodiments of the present application;

[0034] Figure 4 It is a circuit schematic diagram of the SM3280 model flash chip connected to the multi-functional flash memory test rack based on multiple test ports described in the embodiments of the present application and the connection test terminal;

[0035] Figure 5Schematic diagram of the circuit of the AU6989-GTD model flash chip connected to the multi-functional flash test rack based on multiple test ports described in the embodiments of the present application;

[0036] Figure 6 Speed comparison chart of flash tests of the multi-functional flash test rack based on multiple test ports described in the embodiments of the present application. Detailed implementation manners

[0037] In order to make the object, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0038] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0040] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0041] The embodiment of the present application provides a multi-functional flash memory test rack based on multiple test ports, which is used to solve the technical problems of the existing flash memory test rack being expensive, having a single main control and compatibility, and not providing general applicability.

[0042] Embodiment 1:

[0043] Figure 1 It is a framework diagram of the multi-functional flash memory test rack based on multiple test ports described in the embodiment of the present application.

[0044] As Figure 1 shown, the embodiment of the present application provides a multi-functional flash memory test rack based on multiple test ports, including a mobile terminal 10, a flash memory test device 20, and multiple test connection ends 30. The mobile terminal 10 is connected to the flash memory test device 20, and the multiple test connection ends 30 are arranged on the flash memory test device 20.

[0045] In the embodiment of the present application, the mobile terminal 10 is mainly used to control the operation of the flash memory test device 20.

[0046] It should be noted that the mobile terminal 10 is mainly used as an operating device for the convenience of users. The mobile terminal 10 can be a PC computer or an industrial control computer or other mobile terminals with operating functions.

[0047] In the embodiment of the present application, the test connection end 30 is mainly used to connect with the flash memory storage device to be tested.

[0048] It should be noted that multiple test connection ends 30 are arranged in the flash memory test device 20. In this embodiment, the flash memory storage device to be tested can be a BGA152 flash memory.

[0049] In the embodiment of the present application, the flash memory test device 20 is mainly used to perform performance tests on the flash memory storage devices to be tested connected to each test connection end 20. Among them, the performance tests at least include flash memory speed, flash memory stability, and aging performance.

[0050] It should be noted that through the flash memory test device 20 of the multi-functional flash memory test rack based on multiple test ports, performance tests can be realized for different flash memory chips. Compared with the existing method of making a flash memory test rack for each type of flash memory chip, the cost of manufacturing flash memory test racks by manufacturers can be reduced. Among them, the flash memory test device 20 can be made into a USB 3.0.

[0051] A multi-functional flash memory test rack based on multiple test ports provided by the present application includes a mobile terminal, a flash memory test device, and multiple test connection ends. The mobile terminal is connected to the flash memory test device, and the multiple test connection ends are arranged on the flash memory test device. The mobile terminal is used to control the operation of the flash memory test device. The test connection end is used to connect to the flash memory storage device to be tested. The flash memory test device is used to perform performance tests on the flash memory storage devices to be tested connected to each test connection end. This multi-functional flash memory test rack based on multiple test ports is provided with test connection ends for the flash memory storage devices to be tested on the flash memory test device, and then the flash memory test device performs performance tests on the flash memory storage devices to be tested connected to each test connection end. The flash memory storage devices to be tested connected to each test connection end can be different types of flash memory storage devices to be tested, realizing performance tests on different flash chips. Compared with the existing method of making a flash memory test rack for one type of flash chip, it can reduce the cost of the manufacturer making the flash memory test rack, broaden the compatibility of the products tested by this multi-functional flash memory test rack based on multiple test ports, make this multi-functional flash memory test rack based on multiple test ports more applicable, and solve the technical problems of the existing flash memory test rack being expensive, having a single main control and compatibility, and not providing general applicability.

[0052] Figure 2 It is a framework diagram of the flash memory test device of the multi-functional flash memory test rack based on multiple test ports according to another embodiment of the present application. Figure 3 It is a circuit schematic diagram of the first test circuit of the multi-functional flash memory test rack based on multiple test ports according to the embodiment of the present application.

[0053] As Figure 2 and Figure 3 shown, in an embodiment of the present application, this multi-functional flash memory test rack based on multiple test ports includes a control board and a flash memory test circuit 22 arranged on the control board. The flash memory test circuit 22 includes a first test circuit, a second test circuit, and a third test circuit connected to the test connection end. The first test circuit is connected to the second test circuit and the third test circuit respectively through a connection interface. The first test line includes a control chip U4 connected to the test connection end 30 and a GANG module 221, an SPI module 222, a power supply module, and a protection module 224 connected to the control chip U4.

[0054] In the embodiment of the present application, the control chip U4 is mainly used to control the operation of the GANG module 221, the SPI module 222, and the protection module 224. The connection interface of the control chip U4 is a USB interface.

[0055] It should be noted that the control chip U4 is preferably selected as the Genesys Logic GL3520 chip. The Genesys Logic GL3520 chip is a USB3.0 HUB chip with a total bandwidth of 5Gbps, supporting up to 4 USB3.0 downstream ports (test connection end 30), supporting fast charging protocols, supporting sleep functions, supporting overcurrent detection, supporting internal LED status indication, supporting external SPI FLASH for firmware upgrade, etc. The Genesys Logic GL3520 chip also integrates a 5V to 3.3V LDO (low dropout linear regulator) internally, which can save the peripheral circuit structure and reduce costs.

[0056] In the embodiment of the present application, the control chip U4 needs to support multiple downstream ports (test connection ends) to simultaneously receive transmission signals of different types of chips to be tested for communication with the mobile terminal 10 without interference.

[0057] In the embodiment of the present application, the GANG module 221 is used to detect the state of the control chip U4.

[0058] It should be noted that the GANG module 221 includes a status indicator light connected to the PGANG pin of the control chip U4, and the status of the control chip U4 is displayed through the status indicator light LED. In this embodiment, the PGANG pin of the control chip U4 is in the input mode within 50ms after reset. At this time, configuring the pin to a high level can configure it to the GANG mode. After that, the GANG pin is in the output mode, used to detect whether the control chip U4 is in the normal state or the suspended state.

[0059] In the embodiment of the present application, the SPI module 222 is mainly used to connect to the SPI chip to enable external SPI for firmware update. Among them, the SPI module 222 includes an SPI chip connected to four SPI pins of the control chip U4, and a resistor R18 and a capacitor C62 connected to the SPI chip.

[0060] It should be noted that the control chip U4 supports external SPI for firmware update. PIN35, PIN36, PIN58, and PIN59 of the control chip U4 are used to connect to the SPI chip for communication. When connecting, it should be noted that the sending end of the control chip U4 should be connected to the receiving end of the SPI chip, and the receiving end of the control chip U4 should be connected to the sending end of the SPI chip. Among them, the capacitor C62 is a filtering capacitor; the resistor R18 is a pull-up resistor. To reduce power consumption, a 10K 0402 resistor is used.

[0061] In the embodiments of the present application, the power supply module is mainly used to supply power to at least the control chip U4, the GANG module 221, the SPI module 222, and the protection module 224, and is also used to provide different power supplies according to the flash memory storage device under test connected to the test connection terminal 30.

[0062] As Figure 3 shown, in the embodiments of the present application, the power supply module includes a power supply switch protection sub-module 2231, a first power supply sub-module 2232, and a second power supply sub-module 2233 connected to the control chip U4.

[0063] As Figure 3 shown, in the embodiments of the present application, the power supply switch protection sub-module 2231 is mainly used to conduct the spike voltage generated when the switch is closed to the ground to protect the control chip U4.

[0064] It should be noted that the power supply switch protection sub-module 2231 includes a switching element connected to the control chip U4, a fuse element connected to the switching element, and a TVS tube connected to the fuse element. Among them, the TVS tube uses a TVS tube of SMF6.0A. The TVS tube operates in the reverse state, and the reverse breakdown voltage is 6V. It can quickly conduct the spike voltage generated when the switching element is closed to the ground to avoid damage to the control chip U4. The fuse element is a self-recovery fuse. The fuse element uses a 0805 package and a specification of 6V / 1.1A. When the current in the power supply switch protection sub-module 2231 exceeds the limit value of the fuse element, the circuit will be disconnected to protect the backend.

[0065] As Figure 3 shown, in the embodiments of the present application, the first power supply sub-module 2232 is mainly used to provide a power supply with a voltage of 3.3V.

[0066] It should be noted that the first power supply sub-module 2232 includes a power supply chip. The input end of the power supply chip is connected to a 5V power supply, and the 5V power supply outputs a 3.3V power supply through the power supply chip. In this embodiment, the power supply chip is made of a low-dropout linear regulator of the AMS1117-3.3 model. The power supply chip uses an SOT-89 package, and the maximum output current of the power supply chip is 800mA, which can absolutely meet the power consumption requirements of this design. The first power supply sub-module 2232 also provides a 5V external auxiliary power supply interface to prevent insufficient power extraction from the flash memory test device 20 as a whole.

[0067] As Figure 3 shown, in the embodiments of the present application, the second power supply sub-module 2233 is mainly used to provide a power supply with a voltage of 1.2V. Among them, the second power supply sub-module 2233 includes a buck chip U5 and an eighth resistor R8 and a ninth resistor R9 connected to the buck chip U5.

[0068] It should be noted that the step-down chip U5 preferably uses the SY8089 chip, which is packaged in SOT23-5, with a maximum continuous output capacity of 2A and a peak value of 3A, meeting the power consumption requirements of the multi-functional flash memory test rack based on multiple test ports. The feedback voltage of the step-down chip U5 is 0.6V. In order to enable it to generate an output voltage of 1.2V, the resistance values of the eighth resistor R8 and the ninth resistor R9 need to be configured. The voltage output by the step-down chip U5 is calculated as follows:

[0069]

[0070] Since V out = 1.2V, R8 can be taken as 100K, and it is easy to calculate that R9 = 100K. The value of the inductor L6 connected to the step-down chip U5 can be taken as 2.2 - 4.7 μF according to experience. Among them, the pin FB of the step-down chip U5 is also connected with a bootstrap capacitor CB2. The bootstrap capacitor CB2 is mainly used to provide energy at the initial stage of the conduction of the upper transistor inside the step-down chip U5 in order to improve the electrical performance of the second power supply sub-module 2233. The capacitance value of the bootstrap capacitor CB2 is generally about 20pF.

[0071] As Figure 3 shown, in the embodiment of the present application, the protection module 224 is mainly used for ESD protection of the control chip U4. Among them, the protection module 224 includes an ESD protection chip U7 connected to the control chip U4.

[0072] It should be noted that the ESD protection chip U7 preferably uses the ESD protection chip of the AZ1065-06F model. The maximum output capacity of the ESD protection chip of the AZ1065-06F model is 2A, and the peak value is 3A. The ESD protection chip of the AZ1065-06F model has a low impact on signals.

[0073] In the embodiment of the present application, the multi-functional flash memory test rack based on multiple test ports passes through the ESD protection chip U7 of the protection module 224 and the fuse element and TVS tube of the power supply switch protection sub-module 2231 to enhance the anti-static ability and anti-burning ability of the multi-functional flash memory test rack.

[0074] As Figure 3 shown, in the embodiment of the present application, the power supply module includes a power supply mode sub-module 2234 for configuring different power supply modes, and the power supply mode sub-module 2234 is connected to the control chip U4.

[0075] It should be noted that the PIN60 of the control chip U4 is connected to the power supply mode sub-module 2234. The PIN60 of the control chip U4 is configured with the Self / Bus powered mode. When the PIN60 of the control chip U4 outputs a low level, it is the Buspowered power supply mode, and when the PIN60 of the control chip U4 outputs a high level, it is the Self powered power supply mode, so that the power supply module can be configured into different power supply modes according to requirements.

[0076] As Figure 3 shown, in an embodiment of the present application, the first test circuit includes a reset module 25 connected to the control chip U4. The reset module 25 is used to power on and reset the control chip U4. Among them, the reset module 25 includes a forty-seventh capacitor C47, an eleventh resistor R11, and a twelfth resistor R12 connected to the PIN61 of the control chip U4.

[0077] It should be noted that the reset level of the control chip U4 is 5V, and it internally self-resets about 40 μs after power-on. It is necessary to design the external reset time to be greater than 40 μs. Therefore, in this embodiment, an external RC reset circuit is formed by the forty-seventh capacitor C47 and the eleventh resistor R11. The eleventh resistor R11 is selected as 10 kΩ, and the forty-seventh capacitor C47 is selected as 1 μF. In addition, the twelfth resistor R12 is mainly the discharge resistor of C47, and the twelfth resistor R12 is commonly selected as 100 kΩ.

[0078] As Figure 3 shown, in an embodiment of the present application, the first test circuit includes a crystal oscillator module 26 connected to the control chip U4. The crystal oscillator module 26 is used to ensure the normal and stable operation of the control chip U4; an external load capacitor is provided on the crystal oscillator module 26. Among them, the crystal oscillator module 26 includes a crystal oscillator element connected to the control chip U4.

[0079] It should be noted that the crystal oscillator element preferably uses a common four-pin passive crystal in a 3225 package, with a nominal load capacitance of 15 pF. The fifth resistor R5 is connected in parallel with the crystal oscillator element and is a feedback resistor, using a common 1MΩ 0402 resistor. C 31 / C 32 is the external load capacitor of the crystal oscillator. In order to enable the crystal oscillator element to oscillate normally and operate stably, the external load capacitor should be equal to the capacitance value of the nominal load capacitor C. According to the external load capacitor calculation formula:

[0080]

[0081] where Cs is the stray capacitance caused by the crystal package, PCB traces, etc., and is taken as 3 - 5 μF according to experience. If C 31 = 20 μF, then C 32= 20 μF.

[0082] In an embodiment of the present application, the control board is a four-layer stacked PCB board, and the distance between the vias and signal lines of the PCB board is less than 3 cm; the line width of the signal lines of the PCB board is 5.65 mil; the solder mask dielectric constant of the PCB board is 3.8.

[0083] It should be noted that the PCB board adopts a 2313 four-layer board structure design. The signal lines are routed on the 1st and 4th layers, and the 2nd and 3rd layers are power or ground planes. The dielectric constant of the board material structure of the PCB board is 4.05. The thickness of the cover layer on the substrate of the PCB board is 0.8 mil, and the thickness of the cover layer on the signal traces of the PCB board is 0.5 mil. The solder mask dielectric constant of the PCB board is 3.8, the thickness of the PCB board is 8 mm, and the PCB size is 8 cm * 8 cm. In this embodiment, the communication bus of the control chip U3 is preferably selected as USB3.0. It is necessary to control the impedance of 3 pairs of differential signal lines (DM / DP, SSRX+ / SSRX-, SSTX+ / SSTX-) of USB3.0 to be 90 Ω differential, so that the line width of the signal lines of the PCB board is selected as 5.65 mil. A 5 mil differential line pitch and a 5 mil accompanying ground pitch can better design a differential 90-ohm impedance. Since the manufacturing process of the PCB board is etching and lamination, over-etching usually occurs during the manufacturing process, resulting in the actual line width being smaller than the preset value. Therefore, in the process of designing the PCB board, the impedance of the designed PCB board often needs to be a little smaller, so that the impedance of the actually produced PCB board will reach the target requirement value. For other non-high-speed signal lines, an appropriate line width can be used to facilitate the wiring design. The via of the PCB board is a common point of impedance discontinuity. The formula for calculating the via impedance of the PCB board is:

[0084]

[0085] In the design, T is 8 mm, D2 - D1 is 0.508 mm, D kIt is 4.05, D1 is 0.45 mm, d is 0.2 mm, and h is 8 mm. The calculated via impedance Z0 of the PCB board is 2.47 Ω, which is seriously on the low side. However, due to the process and wiring limitations of the PCB manufacturing factory, this value is already the most ideal result. Since the via impedance of the PCB board cannot be controlled, the number of vias should be minimized as much as possible, and the number of vias on high-speed signal lines should be minimized. In addition, to enhance the EMC performance of USB 3.0 in this design as much as possible, accompanying ground vias should be introduced. The distance between the accompanying ground vias and the signal line should be less than λ / 4 to enhance the signal shielding efficiency, where λ is the wavelength of the signal. The highest signal rate of the signals on this PCB board is the two differential pairs (SSTX± / SSRX±) of USB 3.0, and its clock frequency reaches 2.5 GHz. The wavelength λ = C / f, where C is the speed of light and f is the signal frequency. The calculated wavelength λ of the two high-speed differential signals of USB 3.0 is 12 cm, and λ / 4 = 3 cm. That is, the distance between the accompanying ground vias and the signal line should be less than 3 cm to enhance the EMC efficiency of the PCB board. At the same time, the PCB board needs to ensure that there is a complete and non-segmented reference plane under the USB communication high-speed signal lines connecting the upstream USB 3.0 port of the control chip U4 and the downstream USB 3.0 device to connect the flash memory storage device to be tested, so as to ensure the impedance continuity and controllability of the PCB board.

[0086] Figure 4 It is a schematic circuit diagram of the flash memory chip of model SM3280 connected to the connection test end of the multi-functional flash memory test rack based on multiple test ports described in the embodiment of the present application.

[0087] In an embodiment of the present application, the second test circuit includes a second control chip connected to the connection interface of the control chip U4. Among them, the second control chip is preferably a flash memory chip of model SM3280. The flash memory chip of model SM3280 is not open source. The flash memory chip of model SM3280 includes at least pins such as PIN48, PIN52, PIN53 / 54, PIN61, PIN64, PIN65, PIN67, etc. The function of the PIN48 pin is: the external inductor pin of the internal 1.2V DCDC circuit, and an inductor needs to be connected; the function of the PIN52 pin is: the output pin of the internal 1.8V LDO; the function of the PIN53 / 54 pins is: crystal oscillator pins, and no connection is required; the function of the PIN61 pin is: USB PHY 1.2V power supply; the function of the PIN64 pin is: the hardware write protection pin, and hardware write protection can be achieved by pulling it low; the function of the PIN65 pin is: the DDR enable jumper, and this jumper needs to be pulled up to VCCIO or left floating according to the actual situation, which is commonly known as the SB8 jumper in the industry; the function of the PIN67 pin is: the TEST pin, and it can be pulled down normally. Such as Figure 4As shown, the external 3.3V DCDC power supply circuit of the flash memory chip of model SM3280 uses SY8089 in SOT23-5 package, with a maximum continuous output capacity of 2A and a peak of 3A, which also meets the power consumption requirements of the flash memory chip of model SM3280. Its feedback voltage is 0.6V. In order to generate an output voltage of 3.3V, the resistance values of R1 and R2 need to be configured. The calculation is as follows:

[0088]

[0089] Since V out = 3.3V, R1 can be taken as 100K, and it is easy to calculate that R2 ≈ 453K. The inductance L3 can be taken as 4.7μF according to experience. Among them, the capacitor CB1 is the bootstrap capacitor of the internal upper transistor of the DCDC, and its value is generally about 20pF. Among them, the SM3280 chip supports the USB3.2 Gen2x1 protocol, with a bandwidth of 5Gbps, supports up to 8CEs, has built-in BCH ECC error correction, supports SLC, MLC, TLC, and QLC NAND FLASH of the newer process, supports 2D / 3D NAND FLASH, supports the NV-DDR2 mode, supports interleaving, supports hardware write protection, and also integrates an internal crystal oscillator, one LDO, and one 1.2V DCDC, which can greatly reduce peripheral components and reduce costs. At the same time, it also has an LED detection module inside to facilitate observing the working state of the main control, and the working state of the flash memory test device 20 can be directly observed with the naked eye from the appearance of the flash memory test device 20.

[0090] Figure 5 It is a schematic circuit diagram of the AU6989-GTD model flash memory chip connected to the multi-functional flash memory test rack based on multiple test ports described in the embodiment of the present application and the connection test end.

[0091] In an embodiment of the present application, the third test circuit includes a third control chip connected to the connection interface of the control chip U4. Among them, the third control chip is preferably selected as the flash memory chip of model AU6989-GTD. As Figure 5As shown, the flash memory chip of the AU6989 - GTD model is not open - source. The pins of the flash memory chip of the AU6989 - GTD model at least include pins such as PIN8. The function of the PIN8 pin is: an external reference resistor, and its resistance value should be 330 ohms. The AU6989 - GTD flash memory chip integrates three low - dropout linear regulators (LDOs) internally, which can generate 3.3V, 1.8V, and 1.2V. These three power supplies are all the power supplies required by the chip and the flash memory. Moreover, the AU6989 - GTD flash memory chip has very low power consumption in the normal working state and does not require external power supply. Only some filter capacitors need to be added to meet the normal working conditions. Among them, the AU6989 - GTD chip is a general - purpose flash memory controller chip compliant with the USB2.0 High - Speed protocol, with a bandwidth of 480Mbps, supporting up to 8CE at most, supporting the DDR mode, integrating an oscillator and BCH ECC error correction internally, and having three LDOs internally, which can minimize the volume of the peripheral circuit and minimize the cost, and almost support all flash memories, with strong compatibility.

[0092] It should be noted that both the flash memory chip of the SM3280 model and the flash memory chip of the AU6989 - GTD model can support flash memories with up to 8CE at most. However, the flash memory chip of the SM3280 model is a dual - channel chip, while the flash memory chip of the AU6989 - GTD model is a single - channel chip. Therefore, the number of pins of the AU6989 - GTD model flash memory chip is less and the wiring is simpler. Among them, the M3280 chip supports the flash memory communication protocol of the NV - DDR2 mode, and the AU6989 - GTD chip supports the flash memory communication protocol of the asynchronous or NV - DDR mode.

[0093] In the embodiment of this application, the multi - functional flash memory test rack based on multiple test ports adopts a PCB stack - up design through the control board. Through reasonable layout, the PCB size is controlled within 8cm * 8cm, making the size of the multi - functional flash memory test rack reasonable and convenient for carrying and using. And the line width of the control board is set to 5.65mil and the distance between the via and the signal line is set to be less than 3cm, so that the differential impedance of the transmission line between the test connection end of the multi - functional flash memory test rack and the flash memory storage device to be tested is 90Ω, the single - ended impedance of the flash memory transmission line is 50Ω, and the differential impedance is 100Ω. It is realized that the data lines of the same channel of the flash memory should be of equal length, with an error not exceeding 100mil, and the error of the differential line does not exceed 5mil.

[0094] It should be noted that the multi-functional flash memory test rack based on multiple test ports integrates flash memory chips with different characteristics from the flash memory test device on a single PCB board through test connection terminals, which can provide high-performance and wide-applicability test requirements. The flash memory test rack parts controlled by each flash memory chip can be used separately or simultaneously without interfering with each other, meeting the test requirements of most flash memory particles on the market. The multi-functional flash memory test rack based on multiple test ports has good safety and stability. Through the protection module, the flash memory test device can suppress the static electricity generated when inserting the test connection terminal and switching on and off, strengthening the anti-static ability of the flash memory test device; through the TVS tube and fuse element of the power supply switch protection sub-module, it can protect the flash memory test device without exceeding the maximum current provided by the flash memory storage device to be tested connected to the test connection terminal, strengthening the anti-burning ability of the flash memory test device.

[0095] In the embodiments of the present application, the test connection terminals 30 of the multi-functional flash memory test rack based on multiple test ports are respectively connected to the SM3280 chip and the AU6989-GTD chip, and are integrated with the control chip U4 on a PCB board. Among them, the port communication bus of the SM3280 chip is USB3.2 Gen2x1, and the bandwidth is equal to that of USB3.0. Similarly, the differential 90-ohm impedance needs to be controlled. The impedance setting of the SM3280 chip is the same as that of the control chip U4, and will not be described repeatedly here. In addition, asynchronous (Async), NV-DDR or NV-DDR2 mode is used for communication between the NAND FLASH and the SM3280 chip. The required impedances of the high-speed signal lines in the three modes are 50 ohms for single-ended and 100 ohms for differential respectively. The line width of the PCB board of the SM3280 chip is preferably 6.8 mil. The 6.8-mil line width is a better choice for controlling the 50-ohm impedance of the single-ended signal line; it is considered that the 4.6-mil line width and the 5-mil differential line pitch are better choices for controlling the 100-ohm impedance of the differential signal line. The flash memory is similar to the memory, and the same-group data lines therein need to be designed with equal length. Since the SM3280 chip is a dual-channel main controller, equal length is required for each channel, and there is no strict requirement between channels. For the SM3280 chip, the signals in the two channels should be designed with equal length, and the length difference should not exceed 50 mil. Among them, RE / RE_c and DQS / DQS_c need to be strictly equal in length, with a difference not exceeding 5 mil. Secondly, it should be ensured that all the high-speed signal lines of the SM3280 chip have a complete reference plane, that is, the 2 / 3 layer plane adjacent to the bottom of the PCB board trace of the SM3280 chip needs to be complete and not segmented, or the PCB board trace of the SM3280 chip needs to try to meet the requirement that the plane crossing pitch is as small as possible, and the signal return path is as short as possible. The port communication protocol of the AU6989-GTD chip is USB2.0 High Speed. Similarly, the 90-ohm differential impedance design needs to be controlled. The impedance setting of the AU6989-GTD chip is the same as that of the control chip U4, and will not be described repeatedly here. The line width is 5.65 mil, the differential signal pitch is 5 mil, and the accompanying pitch is 5 mil. The communication between the AU6989-GTD chip and the flash memory uses asynchronous (Async) or NV-DDR mode, and the single-ended 50-ohm trace impedance control is also required. The preferred trace width of the PCB board of the AU6989-GTD chip is 6.8 mil. In addition, the AU6989-GTD chip is a single-channel main control chip, and it does not support the NV-DDR2 mode. The flash memory running speed is relatively low, but the multi-CE flash memories of BGA132 / 152 / 136 are all single-chip dual-channel designs. Here, the channels of the flash memory need to be combined into one, that is, all the data lines on the flash memory need to be processed with equal length, and the error does not exceed 100 mil.Although the AU6989-GTD chip does not support higher-speed flash communication protocols such as NV-DDR2, it still has a minimum communication frequency of 50 MHz. Even if the signal line routing does not meet the impedance requirements, it can still communicate normally. Due to the long PCB board trace of the AU6989-GTD chip, it is necessary to ensure that there is a complete reference plane under the signal trace as much as possible. If this cannot be satisfied, try to ensure that the distance between the trace and the plane is small to shorten the signal return path.

[0096] The control chip, the second control chip, and the third control chip of the multi-functional flash memory test rack based on multiple test ports are all provided with test connection terminals. Two BGA152 flash memories are used as the flash memory storage device to be tested connected to the test connection terminals to test the multi-functional flash memory test rack based on multiple test ports. The models of the two BGA152 flash memories are Intel PF29F01T08OCMFP and Intel PF29F64G08PCME1 respectively.

[0097] It should be noted that the second control chip of the SM3280 model is a USB3.2 Gen2x1 dual-channel 8CE main control, supporting NV-DDR2, with a maximum speed of approximately 390 MB / s for reading and 200 MB / s for writing; the third control chip of the AU6989-GTD model is a USB2.0 High Speed single-channel 8CE main control, supporting NV-DDR, with a maximum speed of approximately 38 MB / s for reading and 20 MB / s for writing; PF29F01T08OCMFP has an 8CE 8DIE structure, with a single CE read speed of approximately 200 MB / s and a write speed of approximately 10 MB / s. In the actual use of a finished USB flash drive usually paired with the second control chip of the SM3280 model, the actual performance is approximately 375 MB / s for reading and 80 MB / s for writing; PF29F64G08PCME1 also has an 8CE 8DIE structure, and there is no reliable data reference for the read and write performance of a single CE.

[0098] Figure 6 This is a speed comparison chart for flash memory testing of the multi-functional flash memory test rack based on multiple test ports described in the embodiments of the present application.

[0099] Such as Figure 6As shown, the test modes of the multi-functional flash memory test rack based on multiple test ports include three methods. The first test method: the SM3280 chip with the PF29F01T08OCMFP under USB3.2; the second test method: the SM3280 chip with the PF29F01T08OCMFP under USB2.0; the third test method: the AU6989 chip with the PF29F64B08PCME1. Among them, when the SM3280 chip is paired with the Intel PF29F01T08OCMFP particles, each performance index exceeds the performance data of similar finished U disks; for the test data of the AU6989-GTD chip paired with the PF29F64B08PCME1, since the performance test data of this particle on this main control is not available, no comparison can be made. The terminal device can be a computing device such as a desktop computer, a notebook, a handheld computer, and a cloud server. The terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art can understand that this does not limit the terminal device, which may include more or fewer components than shown in the figure, or combine some components, or different components. For example, the terminal device may also include input and output devices, network access devices, buses, etc.

[0100] The so-called processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0101] The memory may be an internal storage unit of the terminal device, such as the hard disk or memory of the terminal device. The memory may also be an external storage device of the terminal device, such as a plug-in hard disk equipped on the terminal device, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the memory may also include both the internal storage unit and the external storage device of the terminal device. The memory is used to store computer programs and other programs and data required by the terminal device. The memory may also be used to temporarily store data that has been output or will be output.

[0102] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0103] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0105] In addition, in each embodiment of the present invention, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0106] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0107] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A multi-functional flash memory test rack based on multiple test ports, characterized in that, It includes a mobile terminal, a flash memory test device, and a plurality of test connection terminals. The mobile terminal is connected to the flash memory test device, and the plurality of test connection terminals are arranged on the flash memory test device; The mobile terminal is used to control the operation of the flash memory test device; The test connection terminal is used to connect to the flash memory storage device to be tested; The flash memory test device is used to perform performance tests on the flash memory storage devices to be tested connected to each of the test connection terminals; Among them, the performance test at least includes flash memory speed, flash memory stability, and aging performance; The flash memory test device includes a control board and a flash memory test circuit arranged on the control board. The flash memory test circuit includes a first test circuit, a second test circuit, and a third test circuit connected to the test connection terminals. The first test circuit is respectively connected to the second test circuit and the third test circuit through a connection interface. The first test line includes a control chip connected to the test connection terminal, and a GANG module, an SPI module, a power supply module, and a protection module connected to the control chip; The control chip is used to control the operation of the GANG module, the SPI module, and the protection module; The GANG module is used to detect the state of the control chip; The SPI module is used to connect to an SPI chip to perform fixed updates for an external SPI; The power supply module is used to provide power to at least the control chip, the GANG module, the SPI module, and the protection module, and is also used to provide different powers according to the flash memory storage devices to be tested connected to the test connection terminals; The protection module is used to perform ESD protection on the control chip.

2. The multi-functional flash memory test rack based on multiple test ports according to claim 1, wherein The power supply module includes a power supply switch protection sub-module, a first power supply sub-module, and a second power supply sub-module connected to the control chip; The power supply switch protection sub-module is used to conduct the spike voltage generated when the switch is closed to the ground to protect the control chip; The first power supply sub-module is used to provide a power supply with a voltage of 3.3V; The second power supply sub-module is used to provide a power supply with a voltage of 1.2V.

3. The multi-functional flash memory test rack based on multiple test ports according to claim 2, wherein The power supply switch protection sub-module includes a switch element connected to the control chip, a fuse element connected to the switch element, and a TVS tube connected to the fuse element.

4. The multifunctional flash memory test rack based on multiple test ports according to claim 1, wherein, The power supply module includes a power supply mode sub-module for configuring different power supply modes. The power supply mode sub-module is connected to the control chip.

5. The multi-functional flash memory test rack based on multiple test ports according to claim 1, wherein, The first test line includes a reset module connected to the control chip. The reset module is used to perform power-on reset on the control chip.

6. The multifunctional flash memory test rack based on multiple test ports according to claim 1, characterized in that The first test line includes a crystal oscillator module connected to the control chip. The crystal oscillator module is used to ensure the normal and stable operation of the control chip; an external load capacitor is arranged on the crystal oscillator module.

7. The multifunctional flash memory test rack based on multiple test ports according to claim 1, characterized in that The control board is a four-layer stacked PCB board. The distance between the vias and signal lines of the PCB board is less than 3 cm, and the line width of the signal lines of the PCB board is 5.65 mil.

8. The multifunctional flash memory test rack based on multiple test ports according to claim 1, characterized in that The second test circuit includes a second control chip connected to the connection interface of the control chip.

9. The multi-functional flash memory test rack based on multiple test ports according to claim 1, characterized in that The third test circuit includes a third control chip connected to the connection interface of the control chip.

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