Superjunction trench-gate MOSFET structure and method for forming the same

Abstract

Superjunction trench-gate MOSFET structure and method for forming the same. The method for forming the superjunction trench-gate MOSFET includes: providing a substrate, the substrate including a drift region, the substrate having opposite first and second surfaces, the first surface exposing the drift region; forming a gate structure and a body doping region in the drift region; forming a first auxiliary doping region in the drift region on one side of the gate structure, the distance from the top of the first auxiliary doping region to the first surface being greater than the distance from the bottom of the body doping region to the first surface, the first auxiliary doping region having a first projection pattern on the first surface; respectively forming a second auxiliary doping region and a third auxiliary doping region in the drift region on both sides of the gate structure, the second auxiliary doping region being located between the first auxiliary doping region and the body doping region, the second auxiliary doping region having a second projection pattern on the first surface, and the second projection pattern being within the range of the first projection pattern. Thereby, the lithography process difficulty is reduced and the process scaling ability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a superjunction trench gate MOSFET structure and a method for forming the same. Background Art

[0002] Trench gate MOSFET devices are widely used in power conversion circuits and are often used as power switching devices. In order to improve the on-resistance of the trench gate for medium and high voltages (50V - 200V), the superjunction-trench gate concept has been proposed.

[0003] In the prior art, in order to improve the characteristics of the superjunction-trench gate device, an implantation region is formed by implanting into the drift region through a single-time thick photoresist lithography process with a high aspect ratio.

[0004] However, in the above method, in order to make the implantation region as close to the substrate as possible, a high implantation energy is required for implantation. And the greater the implantation energy, the greater the aspect ratio of the photoresist needs to be, thus increasing the process difficulty. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a superjunction trench gate MOSFET structure and a method for forming the same. By forming an auxiliary doping region through multiple lithography processes, while maintaining the breakdown voltage / on-resistance performance of the device, the aspect ratio of the photolithography pattern layer is reduced, thereby reducing the lithography process difficulty and further improving the miniaturization ability of the process.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a superjunction trench gate MOSFET, including: providing a substrate, the substrate including a drift region, the substrate including opposite first and second surfaces, the first surface exposing the drift region; forming a gate structure and a body doping region in the drift region, the body doping region being in contact with the sidewall of the gate structure, and the distance from the bottom of the gate structure to the first surface being greater than the distance from the bottom of the body doping region to the first surface; forming a first auxiliary doping region in the drift region on one side of the gate structure, the distance from the top of the first auxiliary doping region to the first surface being greater than the distance from the bottom of the body doping region to the first surface, the first auxiliary doping region having a first projection pattern on the first surface; respectively forming a second auxiliary doping region and a third auxiliary doping region in the drift regions on both sides of the gate structure, the second auxiliary doping region being located between the first auxiliary doping region and the body doping region, the second auxiliary doping region having a second projection pattern on the first surface, and the second projection pattern being within the range of the first projection pattern.

[0007] Optionally, the method for forming the first auxiliary doped region includes: forming a first patterned layer on the body doped region and part of the gate structure, where the first patterned layer has a first pattern opening, and the symmetry axis of the first pattern opening in the direction perpendicular to the first surface coincides with the symmetry axis of the adjacent gate structure in the direction perpendicular to the first surface, and the first pattern opening is located on the body doped region and the gate structure; using the first patterned layer as a mask, and forming the first auxiliary doped region by a first ion implantation process.

[0008] Optionally, the aspect ratio range of the first patterned layer includes: 3:1 to 8:1.

[0009] Optionally, the parameters of the first ion implantation process include: the implantation energy is greater than or equal to 1000 KeV.

[0010] Optionally, it further includes: performing a first annealing treatment after the first ion implantation process.

[0011] Optionally, the method for forming the second auxiliary doped region and the third auxiliary doped region includes: forming a second patterned layer on the gate structure and part of the body doped region, where the second patterned layer has a second pattern opening and a third pattern opening, and the symmetry axes of the second pattern opening and the third pattern opening in the direction perpendicular to the first surface coincide with the symmetry axis of the adjacent gate structure in the direction perpendicular to the first surface, and the second pattern opening and the third pattern opening are respectively located on part of the body doped regions on both sides of the gate structure; using the second patterned layer as a mask, and forming the second auxiliary doped region and the third auxiliary doped region by a second ion implantation process.

[0012] Optionally, the aspect ratio range of the second patterned layer includes: 4:1 to 8:1.

[0013] Optionally, the thickness of the second patterned layer is less than the thickness of the first patterned layer.

[0014] Optionally, the parameters of the second ion implantation process include: the implantation energy is less than or equal to 1500 KeV.

[0015] Optionally, it further includes: performing a second annealing treatment after the second ion implantation process.

[0016] Optionally, the method for forming the gate structure includes: forming a fourth patterned layer on the drift region, the fourth patterned layer having a fifth pattern opening located on the drift region; using the fourth patterned layer as a mask to etch the drift region to form a first groove, the bottom surface of the first groove being a concave arc surface; after forming the first groove, forming a gate dielectric layer on the inner wall of the first groove; and after forming the gate dielectric layer, forming a gate electrode layer on the inner wall of the gate dielectric layer.

[0017] Optionally, the substrate further includes a drain-end doping layer, and the second surface exposes the drain-end doping layer; the drift region is located on the drain-end doping layer.

[0018] Optionally, after forming the body doping region and before forming the first auxiliary doping region, it further includes: forming a source / drain doping region in the body doping region, the source / drain doping region being in contact with the sidewalls of the gate structure, and the distance from the bottom of the source / drain doping region to the first surface being less than the distance from the bottom of the body doping region to the first surface.

[0019] Optionally, the source / drain doping region has a conductivity type opposite to that of the body doping region.

[0020] Optionally, it further includes: forming conductive plugs and contact doping regions in the body doping regions and the source / drain doping regions on both sides of the gate structure respectively, the distance from the bottom of the conductive plug to the first surface being greater than the distance from the bottom of the source / drain doping region to the first surface and less than the distance from the bottom of the body doping region to the first surface, and the contact doping region surrounding the surface of the conductive plug below the bottom of the source / drain doping region.

[0021] Optionally, the method for forming the conductive plugs and the contact doping regions includes: forming a third patterned layer on the source / drain doping region, the third patterned layer having fourth pattern openings respectively located on a part of the body doping regions on both sides of the gate structure; using the patterned third patterned layer as a mask to form conductive plug openings in the source / drain doping region and the body doping regions; after forming the conductive plug openings, performing a third ion implantation process and a third annealing treatment in the body doping region at the bottom of the conductive plug openings to form the contact doping regions; and after forming the contact doping regions, filling a conductive layer in the conductive plug openings to form the conductive plugs.

[0022] Optionally, the contact doping region has the same conductivity type as the body doping region.

[0023] Optionally, it further includes: forming an insulating layer on the gate structure; and forming a first conductive structure on the insulating layer and the source / drain doping region.

[0024] Optionally, a second conductive structure is formed on the second surface.

[0025] Optionally, the conductive type of the body doping region is opposite to that of the drift region.

[0026] Optionally, the first auxiliary doping region and the second auxiliary doping region have the same conductive type, and the conductive type of the first auxiliary doping region and the second auxiliary doping region is opposite to that of the drift region.

[0027] Correspondingly, the technical solution of the present invention further provides a superjunction trench-gate MOSFET structure, which is characterized in that it includes: a substrate, the substrate includes a drift region, and the substrate includes opposite first and second surfaces; a drift region located in the substrate, the first surface exposes the drift region; a gate structure and a body doping region located in the drift region, the body doping region is in contact with the side wall of the gate structure, and the distance from the bottom of the gate structure to the first surface is greater than the distance from the bottom of the body doping region to the first surface; a first auxiliary doping region located in the drift region, the distance from the top of the first auxiliary doping region to the first surface is greater than the distance from the bottom of the body doping region to the first surface, the first auxiliary doping region has a first projection pattern on the first surface, and the symmetry axis of the first auxiliary doping region perpendicular to the first surface coincides with the symmetry axis of the adjacent gate structure perpendicular to the first surface; a second auxiliary doping region and a third auxiliary doping region located in the drift region on both sides of the gate structure, the second auxiliary doping region is located between the first auxiliary doping region and the body doping region, the second auxiliary doping region has a second projection pattern on the first surface, and the second projection pattern is within the range of the first projection pattern, and the symmetry axis of the second auxiliary doping region and the third auxiliary doping region perpendicular to the first surface coincides with the symmetry axis of the adjacent gate structure perpendicular to the first surface.

[0028] Optionally, the gate structure includes: a gate dielectric layer located in the drift region; a gate layer located on the gate dielectric layer in the drift region.

[0029] Optionally, it further includes: a drain-end doping layer located in the substrate, the second surface exposes the drain-end doping layer; the drift region is located on the drain-end doping layer.

[0030] Optionally, it further includes: a source / drain doping region located in the body doping region, the source / drain doping region is in contact with the side wall of the gate structure, and the distance from the bottom of the source / drain doping region to the first surface is less than the distance from the bottom of the body doping region to the first surface.

[0031] Optionally, the conductive type of the source / drain doping region is opposite to that of the body doping region. [[ID=2,3]]

[0032] Optionally, it further includes conductive plugs and contact doping regions in the body doping regions and the source / drain doping regions on both sides of the gate structure. The distance from the bottom of the conductive plug to the first surface is greater than the distance from the bottom of the source / drain doping region to the first surface, and the distance from the bottom of the conductive plug to the first surface is less than the distance from the bottom of the body doping region to the first surface. The contact doping region surrounds the surface of the conductive plug below the bottom of the source / drain doping region.

[0033] Optionally, the contact doping region has the same conductivity type as the body doping region.

[0034] Optionally, it further includes an insulating layer on the gate structure; a first conductive structure on the insulating layer and the source / drain doping regions.

[0035] Optionally, it further includes a second conductive structure on the surface of the second surface.

[0036] Optionally, the conductivity type of the body doping region is opposite to the conductivity type of the drift region.

[0037] Optionally, the first auxiliary doping region and the second auxiliary doping region have the same conductivity type, and the conductivity type of the first auxiliary doping region and the second auxiliary doping region is opposite to the conductivity type of the drift region.

[0038] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0039] In a method for forming a superjunction trench gate MOSFET provided by the technical solution of the present invention, the first auxiliary doping region is formed in the drift region and the second auxiliary doping region and the third auxiliary doping region are formed in the drift region between the first auxiliary doping region and the body doping region by means of a combination of multiple photolithography processes. Since the first auxiliary doping region, the second auxiliary doping region, and the third auxiliary doping region can deplete the part near the second surface of the substrate and the part near the first surface of the substrate respectively, therefore, while maintaining the breakdown voltage / on-resistance performance of the device, due to the combination of thin glue and thick glue to achieve a lower aspect ratio, the aspect ratio of the pattern layer in each photolithography process can be reduced. Thus, while maintaining the breakdown voltage / on-resistance performance of the device, the difficulty of the photolithography process is reduced, and the miniaturization ability of the process is further improved.

[0040] Correspondingly, in a superjunction trench gate MOSFET structure provided by the technical solution of the present invention, the first auxiliary doping region located in the drift region and the second auxiliary doping region and the third auxiliary doping region located between the first auxiliary doping region and the body doping region are formed by multiple implantations. Without changing the breakdown voltage / on-resistance performance of the device, the process difficulty is reduced, and the miniaturization ability of the process is further improved. [[ID=

[0041] Figure 1 Schematic diagram of a method for forming an auxiliary doping region in a superjunction trench-gate MOSFET structure;

[0042] Figures 2 to 14 Schematic diagram of the structure in the process of forming a superjunction trench-gate MOSFET according to an embodiment of the present invention. Detailed implementation manners

[0043] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0044] As described in the background art, in order to make the implantation region as close to the substrate as possible, high implantation energy is required for implantation. And the greater the implantation energy, the greater the aspect ratio of the photoresist needs to be, thus increasing the process difficulty. Now, an analysis will be made in combination with a method for forming an auxiliary doping region in a superjunction trench-gate MOSFET structure.

[0045] Figure 1 Schematic diagram of a method for forming an auxiliary doping region in a superjunction trench-gate MOSFET structure. The method for forming the auxiliary doping region 103 includes: forming a patterned layer 121 on the body doping region 106 and part of the gate structure 120, the patterned layer 121 having a pattern opening 122, the pattern opening 122 being located on the body doping region 106 between two of the gate structures 120, and the aspect ratio of the patterned layer 121 being h / w; using the patterned layer 121 as a mask, and forming the auxiliary doping region 103 in the drift region 102 by an ion implantation process.

[0046] In order to improve the characteristics of the semiconductor structure, the bottom end of the auxiliary doping region 103 for assisting the depletion of the drift region 102 will be as close to the substrate 101 as possible. In order to make the auxiliary doping region 103 as close to the substrate 101 as possible, high implantation energy is required for implantation.

[0047] In this embodiment, the implantation energy is greater than or equal to 2500 KeV.

[0048] In this embodiment, the range of the aspect ratio h / w of the patterned layer 121 includes 10:1 to 15:1.

[0049] However, the greater the implantation energy, the greater the aspect ratio h / w of the patterned layer 121 needs to be, thus increasing the process difficulty.

[0050] To solve the aforementioned technical problem, the technical solution of the present invention forms a first auxiliary doping region in the drift region, and a second auxiliary doping region and a third auxiliary doping region in the drift region between the first auxiliary doping region and the body doping region, respectively, by combining multiple photolithography processes. Since the first auxiliary doping region, the second auxiliary doping region, and the third auxiliary doping region can be used to deplete the portion close to the second surface of the substrate and the portion close to the first surface of the substrate, respectively, while maintaining the device's breakdown voltage / on-resistance performance, the aspect ratio of the pattern layer can be reduced in each photolithography process due to the lower aspect ratio achieved by using a combination of thin and thick photoresist. This reduces the difficulty of the photolithography process while maintaining the device's breakdown voltage / on-resistance performance, further improving the process's miniaturization capability.

[0051] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figures 2 to 14 Schematic diagram of the structure of the super junction trench gate MOSFET formation process in an embodiment of the present invention.

[0053] Please refer to Figure 2 , providing a substrate 200 , wherein the substrate 200 includes a drift region 201 , and the substrate 200 includes a first surface A and a second surface B opposite to each other, wherein the first surface A exposes the drift region 201 .

[0054] In this embodiment, the substrate 200 is made of silicon.

[0055] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0056] The conductivity type of the drift region 201 includes: N-type and P-type. In this embodiment, the conductivity type of the drift region 201 is N-type.

[0057] In this embodiment, the doping concentration range of the drift region 201 includes: 5×e 15 cm -3 to 1×e 17 cm -3 .

[0058] In other embodiments, the doping concentration of the drift region may also be: the doping concentration range of the drift region close to the second surface of the substrate includes 1×e 16 cm -3from 1×e 17 cm -3 and the doping concentration range of the drift region near the first surface portion of the substrate includes 3×e 15 cm -3 to 3×e 16 cm -3 .

[0059] In this embodiment, the substrate 200 further includes a drain-end doping layer, and the second surface B exposes the drain-end doping layer; the drift region 201 is located on the drain-end doping layer.

[0060] The conduction type of the drain-end doping layer is the same as that of the drift region 201. The conduction types of the drain-end doping layer include: N-type and P-type. In this embodiment, the conduction type of the drain-end doping layer is highly doped N-type.

[0061] Next, a gate structure is formed in the drift region 201. For the specific method of forming the gate structure, please refer to Figures 3 to 5 .

[0062] Please refer to Figure 3 , a fourth patterned layer 213 is formed on the drift region 201, and a fifth pattern opening 214 is formed in the fourth patterned layer 213, and the fifth pattern opening 214 is located on the drift region 201.

[0063] The fourth patterned layer 213 is used to form a subsequent first groove.

[0064] In this embodiment, the material of the fourth patterned layer 213 includes photoresist.

[0065] Please refer to Figure 4 , using the fourth patterned layer 213 as a mask, etching the drift region 201 to form a first groove 215, and the bottom surface of the first groove 215 is a concave arc surface.

[0066] The method of etching the drift region 201 to form the first groove 215 includes a dry etching process.

[0067] The first groove 215 is used to form a subsequent gate structure.

[0068] Please refer to Figure 5 , after forming the first groove 215, a gate dielectric layer 211 is formed on the inner wall of the first groove 215; after forming the gate dielectric layer 211, a gate electrode layer 212 is formed on the inner wall of the gate dielectric layer 211.

[0069] The gate dielectric layer 211 is used to isolate the subsequent gate electrode layer and the drift region 201.

[0070] In this embodiment, the material of the gate dielectric layer 211 includes an oxide.

[0071] In this embodiment, the material of the gate layer 212 includes polysilicon.

[0072] Please refer to Figure 6 , after forming the gate structure 210, a body doping region 202 is formed in the drift region 201. The body doping region 202 is in contact with the sidewalls of the gate structure 210, and the distance from the bottom of the gate structure 210 to the first surface A is greater than the distance from the bottom of the body doping region 202 to the first surface A.

[0073] The conduction type of the body doping region 202 is opposite to that of the drift region 201. In this embodiment, the conduction type of the body doping region 202 is P-type.

[0074] The formation process of the body doping region 202 includes an ion implantation process.

[0075] Please refer to Figure 7 , after forming the body doping region 202, a source / drain doping region 203 is formed in the body doping region 202. The source / drain doping region 203 is in contact with the sidewalls of the gate structure 210, and the distance from the bottom of the source / drain doping region 203 to the first surface A is less than the distance from the bottom of the body doping region 202 to the first surface A.

[0076] The conduction type of the source / drain doping region 203 is opposite to that of the body doping region 202. In this embodiment, the conduction type of the source / drain doping region 203 is heavily doped N-type.

[0077] The formation process of the source / drain doping region 203 includes an ion implantation process.

[0078] Next, a first auxiliary doping region is formed in the drift region 201 between some of the gate structures 210. For the specific formation method of the first auxiliary doping region, please refer to Figure 8 .

[0079] Please refer to Figure 8 , a first patterned layer 221 is formed on the body doping region 202 and some of the gate structures 210. The first patterned layer 221 has a first patterned opening 222. The symmetry axis of the first patterned opening 222 in the direction perpendicular to the first surface A coincides with the symmetry axis of the adjacent gate structure 210 in the direction perpendicular to the first surface A, and the first patterned opening 222 is located on the body doping region 202 and the gate structure 210; using the first patterned layer 221 as a mask, the first auxiliary doping region 220 is formed by a first ion implantation process.

[0080] Please continue to refer toFigure 8 The distance from the top of the first auxiliary doped region 220 to the first surface A is greater than the distance from the bottom of the body doped region 202 to the first surface A, and the first auxiliary doped region 220 has a first projection pattern on the first surface A.

[0081] The aspect ratio of the first patterned layer 221 is h1 / w1.

[0082] In this embodiment, the range of the aspect ratio h1 / w1 of the first patterned layer 221 includes: 3:1 to 8:1.

[0083] In this embodiment, the thickness of the first patterned layer 221 is greater than or equal to 2.5 μm.

[0084] In this embodiment, the parameters of the first ion implantation process include: the implantation energy is greater than or equal to 1000 KeV.

[0085] The first patterned layer 221 is used to form the first auxiliary doped region 220.

[0086] The material of the first patterned layer 221 includes one of the combinations of photoresist, nitride, and oxide. In this embodiment, the material of the first patterned layer 221 is photoresist.

[0087] In this embodiment, the ions of the first ion implantation process include boron.

[0088] The conduction type of the first auxiliary doped region 220 is opposite to the conduction type of the drift region 201.

[0089] In this embodiment, the conduction type of the first auxiliary doped region 220 is P-type.

[0090] Next, after the first ion implantation process, a first annealing treatment is performed.

[0091] Next, a second auxiliary doped region and a third auxiliary doped region are formed in the drift regions on both sides of the gate structure. For the specific formation method of the second auxiliary doped region and the third auxiliary doped region, please refer to Figure 9 .

[0092] Please refer to Figure 9, a second patterned layer 231 is formed on the gate structure 210 and on a part of the body doping region 202. The second patterned layer 231 has a second pattern opening 232 and a third pattern opening 233. The symmetry axes of the second pattern opening 232 and the third pattern opening 233 in the direction perpendicular to the first surface A coincide with the symmetry axes of the adjacent gate structures 210 in the direction perpendicular to the first surface A, and the second pattern opening 232 and the third pattern opening 233 are respectively located on a part of the body doping region 202 on both sides of the gate structure 210; using the second patterned layer 231 as a mask, the second auxiliary doping region 230 and the third auxiliary doping region 240 are formed by a second ion implantation process.

[0093] Please continue to refer to Figure 9 , the second auxiliary doping region 230 is located between the first auxiliary doping region 220 and the body doping region 202. The second auxiliary doping region 230 has a second projection pattern on the first surface A, and the second projection pattern is within the range of the first projection pattern.

[0094] The aspect ratio of the second patterned layer 231 is h2 / w2.

[0095] In this embodiment, the range of the aspect ratio h2 / w2 of the second patterned layer 231 includes: 4:1 to 8:1.

[0096] In this embodiment, the parameters of the second ion implantation process include: the implantation energy is less than or equal to 1500 KeV.

[0097] The second patterned layer 231 is used to form the second auxiliary doping region 230.

[0098] The material of the second patterned layer 231 includes one of a combination of photoresist, nitride, and oxide. In this embodiment, the material of the second patterned layer 231 is photoresist.

[0099] In this embodiment, the ions of the second ion implantation process include boron.

[0100] The first auxiliary doping region 220 has the same conductivity type as the second auxiliary doping region 230 and the third auxiliary doping region 240, and the conductivity types of the second auxiliary doping region 230 and the third auxiliary doping region 240 are opposite to the conductivity type of the drift region 201.

[0101] In this embodiment, the conductivity type of the second auxiliary doping region 230 is P-type.

[0102] In this embodiment, the conductivity type of the third auxiliary doping region 240 is P-type.

[0103] The thickness of the second patterned layer 231 is less than that of the first patterned layer 221.

[0104] In this embodiment, the thickness of the second patterned layer 231 is less than or equal to 3 μm.

[0105] The first auxiliary doping region 220 is formed in the drift region 201 and the second auxiliary doping region 230 and the third auxiliary doping region 240 are formed in the drift region 201 between the first auxiliary doping region 220 and the body doping region 202 by means of a combination of multiple photolithography processes. Since the portions near the second surface B of the substrate 200 and the portions near the first surface A of the substrate 200 can be depleted by the first auxiliary doping region 220, the second auxiliary doping region 230, and the third auxiliary doping region 240 respectively, therefore, while maintaining the breakdown voltage / on-resistance performance of the device, due to the use of a combination of a thin resist and a thick resist to achieve a lower aspect ratio, the aspect ratio of the patterned layer in each photolithography process can be reduced. Thus, while maintaining the breakdown voltage / on-resistance performance of the device, the difficulty of the photolithography process is reduced, and the miniaturization ability of the process is further improved.

[0106] It should be noted that before forming the first auxiliary doping region 220, other auxiliary doping regions can be formed multiple times, and the other auxiliary doping regions are located between the first auxiliary doping region 220 and the second surface B.

[0107] Next, after the second ion implantation process, a second annealing treatment is performed.

[0108] Next, conductive plugs and contact doping regions are formed in the body doping regions 202 and the source / drain doping regions 203 on both sides of the gate structure 210. For the specific formation method of the conductive plugs and the contact doping regions, please refer to Figures 10 to 12 .

[0109] Please refer to Figure 10 , a third patterned layer 206 is formed on the source / drain doping region 203, and a fourth pattern opening 207 is formed in the third patterned layer 206, and the fourth pattern openings 207 are respectively located on a part of the body doping regions 202 on both sides of the gate structure 210; using the patterned third patterned layer 206 as a mask, conductive plug openings 208 are formed in the source / drain doping region 203 and the body doping regions 202.

[0110] The third patterned layer 206 is used to form subsequent conductive plugs.

[0111] The material of the third patterned layer 206 includes one of a combination of photoresist, nitride, and oxide. In this embodiment, the material of the third patterned layer 206 is photoresist.

[0112] The forming process of the conductive plug opening 208 includes a dry etching process.

[0113] Please refer to Figure 11 , after forming the conductive plug opening 208, a third ion implantation process and a third annealing treatment are performed in the body doping region 202 at the bottom of the conductive plug opening 208 to form the contact doping region 205.

[0114] The contact doping region 205 has the same conductivity type as the body doping region 202.

[0115] In this embodiment, the conductivity type of the contact doping region 205 is heavily doped P-type.

[0116] Please refer to Figure 12 , after forming the contact doping region 205, a conductive layer is filled in the conductive plug opening 208 to form the conductive plug 204.

[0117] The material of the conductive plug 204 includes metal.

[0118] In this embodiment, the material of the conductive plug 204 is tungsten.

[0119] Please continue to refer to Figure 12 , the distance from the bottom of the conductive plug 204 to the first surface A is greater than the distance from the bottom of the source / drain doping region 203 to the first surface A, and the distance from the bottom of the conductive plug 204 to the first surface A is less than the distance from the bottom of the body doping region 202 to the first surface A, and the contact doping region 205 surrounds the surface of the conductive plug 204 below the bottom of the source / drain doping region 203.

[0120] Please refer to Figure 13 , after forming the conductive plug 204 and the contact doping region 205, an insulating layer 251 is formed on the gate structure 210; a first conductive structure 250 is formed on the insulating layer 251 and the source / drain doping region 203.

[0121] The material of the first conductive structure 250 includes metal.

[0122] Please refer to Figure 14 , after forming the first conductive structure 250, a second conductive structure 252 is formed on the surface of the second surface B.

[0123] The material of the second conductive structure 252 includes metal.

[0124] The first conductive structure 250 and the second conductive structure 252 are used as the source / drain end metal layers of the superjunction trench gate MOSFET device.

[0125] Correspondingly, an embodiment of the present invention further provides a superjunction trench-gate MOSFET structure formed by the above method. Please continue to refer to Figure 14 , including:

[0126] A substrate 200, the substrate 200 includes a drift region 201, and the substrate 200 includes opposite first surface A and second surface B; a drift region 201 located within the substrate 200, and the first surface A exposes the drift region 201.

[0127] In this embodiment, the material of the substrate 200 is silicon.

[0128] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0129] The conductivity type of the drift region 201 includes: N-type and P-type. In this embodiment, the conductivity type of the drift region 201 is N-type.

[0130] In this embodiment, the doping concentration range of the drift region 201 includes: 5×e 15 cm -3 to 1×e 17 cm -3 .

[0131] In other embodiments, the doping concentration of the drift region can also be: the doping concentration range of the part of the drift region close to the second surface of the substrate includes 1×e 16 cm -3 to 1×e 17 cm -3 , and the doping concentration range of the part of the drift region close to the first surface of the substrate includes 3×e 15 cm -3 to 3×e 16 cm -3 .

[0132] Please continue to refer to Figure 14 , the superjunction trench-gate MOSFET structure further includes a gate structure 210 and a body doping region 202 located within the drift region 201, the body doping region 202 is in contact with the sidewall of the gate structure 210, and the distance from the bottom of the gate structure 210 to the first surface A is greater than the distance from the bottom of the body doping region 202 to the first surface A.

[0133] The conductivity type of the body doping region 202 is opposite to that of the drift region 201. In this embodiment, the conductivity type of the body doping region 202 is P-type.

[0134] Please continue to refer to Figure 14 , the gate structure 210 includes: a gate dielectric layer 211 located in the drift region 201; a gate layer 212 located on the gate dielectric layer 211 in the drift region 201.

[0135] The gate dielectric layer 211 is used to isolate the gate layer 212 and the drift region 201.

[0136] In this embodiment, the material of the gate dielectric layer 211 includes an oxide.

[0137] In this embodiment, the material of the gate layer 212 includes polysilicon.

[0138] Please continue to refer to Figure 14 , the superjunction trench gate MOSFET structure further includes a first auxiliary doping region 220 located in the drift region 201 on one side of the gate structure 210. The distance from the top of the first auxiliary doping region 220 to the first surface A is greater than the distance from the bottom of the body doping region 202 to the first surface A. The first auxiliary doping region 220 has a first projection pattern on the first surface A, and the symmetry axis of the first auxiliary doping region 220 perpendicular to the first surface A coincides with the symmetry axis of the adjacent gate structure 210 perpendicular to the first surface A.

[0139] The conductivity type of the first auxiliary doping region 220 is opposite to that of the drift region 201.

[0140] In this embodiment, the conductivity type of the first auxiliary doping region 220 is P-type.

[0141] Please continue to refer to Figure 14 , the superjunction trench gate MOSFET structure further includes a second auxiliary doping region 230 and a third auxiliary doping region 240 located in the drift region 201 on both sides of the gate structure 210. The second auxiliary doping region 230 is located between the first auxiliary doping region 220 and the body doping region 202. The second auxiliary doping region 230 has a second projection pattern on the first surface A, and the second projection pattern is within the range of the first projection pattern. The symmetry axes of the second auxiliary doping region 230 and the third auxiliary doping region 240 perpendicular to the first surface A coincide with the symmetry axis of the adjacent gate structure 210 perpendicular to the first surface A.

[0142] The first auxiliary doping region 220 has the same conductivity type as the second auxiliary doping region 230 and the third auxiliary doping region 240, and the conductivity types of the second auxiliary doping region 230 and the third auxiliary doping region 240 are opposite to the conductivity type of the drift region 201.

[0143] In this embodiment, the conductivity type of the second auxiliary doping region 230 is P-type.

[0144] In this embodiment, the conductivity type of the third auxiliary doping region 240 is P-type.

[0145] The first auxiliary doping region 220 located in the drift region 201 and the second auxiliary doping region 230 and the third auxiliary doping region 240 located between the first auxiliary doping region 220 and the body doping region 202 are formed by multiple implantations, which reduces the process difficulty and further improves the process scaling ability while keeping the breakdown voltage / on-resistance performance of the device unchanged.

[0146] Please continue to refer to Figure 14 , the superjunction trench-gate MOSFET structure further includes: a drain-end doping layer located in the substrate 200, and the second surface B exposes the drain-end doping layer; the drift region 201 is located on the drain-end doping layer.

[0147] The conductivity type of the drain-end doping layer is the same as the conductivity type of the drift region 201. The conductivity type of the drain-end doping layer includes: N-type and P-type. In this embodiment, the conductivity type of the drain-end doping layer is highly doped N-type.

[0148] Please continue to refer to Figure 14 , the superjunction trench-gate MOSFET structure further includes: a source / drain doping region 203 located in the body doping region 202, the source / drain doping region 203 is in contact with the sidewalls of the gate structure 210, and the distance from the bottom of the source / drain doping region 203 to the first surface A is less than the distance from the bottom of the body doping region 202 to the first surface A.

[0149] The conductivity type of the source / drain doping region 203 is opposite to the conductivity type of the body doping region 202. In this embodiment, the conductivity type of the source / drain doping region 203 is heavily doped N-type.

[0150] Please continue to refer to Figure 14, the superjunction trench-gate MOSFET structure further includes conductive plugs 204 and contact doping regions 205 located in the body doping regions 202 and the source / drain doping regions 203 on both sides of the gate structure 210. The distance from the bottom of the conductive plug 204 to the first surface A is greater than the distance from the bottom of the source / drain doping region 203 to the first surface A, and the distance from the bottom of the conductive plug 204 to the first surface A is less than the distance from the bottom of the body doping region 202 to the first surface A. The contact doping region 205 surrounds the surface of the conductive plug 204 that is lower than the bottom of the source / drain doping region 203.

[0151] The contact doping region 205 has the same conductivity type as the body doping region 202.

[0152] In this embodiment, the conductivity type of the contact doping region 205 is heavily doped P-type.

[0153] The material of the conductive plug 204 includes metal.

[0154] In this embodiment, the material of the conductive plug 204 is tungsten.

[0155] Please continue to refer to Figure 14 , the superjunction trench-gate MOSFET structure further includes an insulating layer 251 located on the gate structure 210; a first conductive structure 250 located on the insulating layer 251 and the source / drain doping region 203.

[0156] The material of the first conductive structure 250 includes metal.

[0157] Please continue to refer to Figure 14 , further includes a second conductive structure 252 located on the surface of the second surface B.

[0158] The material of the second conductive structure 252 includes metal.

[0159] The first conductive structure 250 and the second conductive structure 252 are used as the source / drain end metal layers of the superjunction trench-gate MOSFET device.

[0160] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a superjunction trench-gate MOSFET, characterized in that, Comprising: Providing a substrate, the substrate including a drift region, the substrate including opposite first and second surfaces, the first surface exposing the drift region; Forming a gate structure and a body doping region in the drift region, the body doping region contacting a sidewall of the gate structure, and a distance from a bottom of the gate structure to the first surface being greater than a distance from a bottom of the body doping region to the first surface; Forming a first auxiliary doping region in the drift region between some of the gate structures, a distance from a top of the first auxiliary doping region to the first surface being greater than a distance from a bottom of the body doping region to the first surface, the first auxiliary doping region having a first projection pattern on the first surface, and a conductivity type of the first auxiliary doping region being opposite to a conductivity type of the drift region; Forming a second auxiliary doping region and a third auxiliary doping region in the drift region on two sides of the gate structure respectively, the second auxiliary doping region being located between the first auxiliary doping region and the body doping region, the second auxiliary doping region having a second projection pattern on the first surface, and the second projection pattern being within the range of the first projection pattern, wherein there is a first auxiliary doping region below the second auxiliary doping region, while there is no first auxiliary doping region below the third auxiliary doping region, and conductivity types of the second auxiliary doping region and the third auxiliary doping region are opposite to the conductivity type of the drift region.

2. The forming method of the superjunction trench-gate MOSFET according to claim 1, characterized in that The forming method of the first auxiliary doping region includes: forming a first patterned layer on the body doping region and some of the gate structures, the first patterned layer having a first patterned opening, a symmetry axis of the first patterned opening in a direction perpendicular to the first surface coinciding with a symmetry axis of an adjacent gate structure in a direction perpendicular to the first surface, and the first patterned opening being located on the body doping region and the gate structures; using the first patterned layer as a mask and adopting a first ion implantation process to form the first auxiliary doping region.

3. The forming method of the superjunction trench-gate MOSFET according to claim 2, characterized in that The aspect ratio range of the first patterned layer includes: 3:1 to 8:

1.

4. The forming method of the superjunction trench-gate MOSFET according to claim 2, characterized in that, The parameters of the first ion implantation process include: an implantation energy being greater than or equal to 1000 KeV.

5. The method for forming a superjunction trench-gate MOSFET according to claim 2, wherein Further comprising: Performing a first annealing treatment after the first ion implantation process.

6. The forming method of the superjunction trench-gate MOSFET as described in claim 2, wherein The forming method of the second auxiliary doping region and the third auxiliary doping region includes: forming a second patterned layer on the gate structure and some of the body doping region, the second patterned layer having a second patterned opening and a third patterned opening, symmetry axes of the second patterned opening and the third patterned opening in a direction perpendicular to the first surface respectively coinciding with a symmetry axis of an adjacent gate structure in a direction perpendicular to the first surface, and the second patterned opening and the third patterned opening being located on some of the body doping regions on two sides of the gate structure respectively; using the second patterned layer as a mask and adopting a second ion implantation process to form the second auxiliary doping region and the third auxiliary doping region.

7. The forming method of the super junction trench gate MOSFET as described in claim 6, characterized in that, The aspect ratio range of the second patterned layer includes: 4:1 to 8:

1.

8. The method for forming a superjunction trench gate MOSFET according to claim 6, wherein The thickness of the second patterned layer is less than the thickness of the first patterned layer.

9. The forming method of the superjunction trench gate MOSFET according to claim 6, characterized in that, The parameters of the second ion implantation process include: an implantation energy being less than or equal to 1500 KeV.

10. The method for forming a super junction trench gate MOSFET according to claim 6, characterized in that, Further comprising: After the second ion implantation process, a second annealing process is performed.

11. The method for forming a super junction trench gate MOSFET according to claim 1, wherein, The method for forming the gate structure includes: forming a fourth patterned layer on the drift region, where the fourth patterned layer has a fifth patterned opening located on the drift region; using the fourth patterned layer as a mask to etch the drift region to form a first groove, the bottom surface of the first groove being a concave arc surface; after forming the first groove, forming a gate dielectric layer on the inner wall of the first groove; after forming the gate dielectric layer, forming a gate layer on the inner wall of the gate dielectric layer.

12. The forming method of the super junction trench gate MOSFET according to claim 1, characterized in that, The substrate further includes a drain end doping layer, and the second surface exposes the drain end doping layer; the drift region is located on the drain end doping layer.

13. The forming method of the super junction trench gate MOSFET according to claim 1, characterized in that, After forming the body doping region and before forming the first auxiliary doping region, it further includes: forming a source / drain doping region in the body doping region, the source / drain doping region being in contact with the sidewalls of the gate structure, and the distance from the bottom of the source / drain doping region to the first surface being less than the distance from the bottom of the body doping region to the first surface.

14. The method for forming a superjunction trench-gate MOSFET according to claim 13, wherein, The conductive type of the source / drain doping region is opposite to that of the body doping region.

15. The method for forming a superjunction trench-gate MOSFET according to claim 13, wherein, It further includes: Forming a conductive plug and a contact doping region in the body doping region and the source / drain doping region on both sides of the gate structure respectively, the distance from the bottom of the conductive plug to the first surface being greater than the distance from the bottom of the source / drain doping region to the first surface, and the distance from the bottom of the conductive plug to the first surface being less than the distance from the bottom of the body doping region to the first surface, the contact doping region surrounding the surface of the conductive plug below the bottom of the source / drain doping region.

16. The method for forming a super junction trench gate MOSFET according to claim 15, wherein The method for forming the conductive plug and the contact doping region includes: forming a third patterned layer on the source / drain doping region, the third patterned layer having a fourth patterned opening located on a part of the body doping region on both sides of the gate structure respectively; using the patterned third patterned layer as a mask to form a conductive plug opening in the source / drain doping region and the body doping region; after forming the conductive plug opening, performing a third ion implantation process and a third annealing process in the body doping region at the bottom of the conductive plug opening to form the contact doping region; after forming the contact doping region, filling a conductive layer in the conductive plug opening to form a conductive plug.

17. The forming method of the superjunction trench gate MOSFET according to claim 15, characterized in that, The conductive type of the contact doping region is the same as that of the body doping region.

18. The method for forming a super junction trench gate MOSFET according to claim 13, wherein It further includes: Forming an insulating layer on the gate structure; forming a first conductive structure on the insulating layer and the source / drain doping region.

19. The method for forming a superjunction trench gate MOSFET as described in claim 1, wherein Forming a second conductive structure on the surface of the second face.

20. The forming method of the superjunction trench gate MOSFET as described in claim 1, characterized in that, The conductive type of the body doping region is opposite to that of the drift region.

21. The forming method of the superjunction trench gate MOSFET according to claim 1, characterized in that, The conductive types of the first auxiliary doping region and the second auxiliary doping region are the same, and the conductive types of the first auxiliary doping region and the second auxiliary doping region are opposite to that of the drift region.

22. A superjunction trench-gate MOSFET structure, characterized in that, It includes: A substrate, the substrate including a drift region, the substrate including opposite first and second faces; A drift region located in the substrate, the first face exposing the drift region; A gate structure and a body doping region located in the drift region, the body doping region being in contact with the sidewalls of the gate structure, and the distance from the bottom of the gate structure to the first surface being greater than the distance from the bottom of the body doping region to the first surface; A first auxiliary doping region located in the drift region between some of the gate structures, the distance from the top of the first auxiliary doping region to the first surface being greater than the distance from the bottom of the body doping region to the first surface, the first auxiliary doping region having a first projection pattern on the first surface, the axis of symmetry of the first auxiliary doping region perpendicular to the first surface coinciding with the axis of symmetry of the adjacent gate structure perpendicular to the first surface, and the conductivity type of the first auxiliary doping region being opposite to the conductivity type of the drift region; A second auxiliary doping region and a third auxiliary doping region located in the drift region on both sides of the gate structure, the second auxiliary doping region being located between the first auxiliary doping region and the body doping region, the second auxiliary doping region having a second projection pattern on the first surface, and the second projection pattern being within the range of the first projection pattern, the axes of symmetry of the second auxiliary doping region and the third auxiliary doping region perpendicular to the first surface coinciding with the axes of symmetry of the adjacent gate structures perpendicular to the first surface, wherein there is a first auxiliary doping region below the second auxiliary doping region, while there is no first auxiliary doping region below the third auxiliary doping region, and the conductivity types of the second auxiliary doping region and the third auxiliary doping region are opposite to the conductivity type of the drift region.

23. The superjunction trench-gate MOSFET structure according to claim 22, wherein The gate structure includes: a gate dielectric layer located in the drift region; a gate layer located on the gate dielectric layer in the drift region.

24. The superjunction trench-gate MOSFET structure according to claim 22, wherein, It further includes: A drain-end doping layer located in the substrate, the second surface exposing the drain-end doping layer; The drift region is located on the drain-end doping layer.

25. The superjunction trench-gate MOSFET structure according to claim 22, characterized in that, It further includes: a source-drain doping region located in the body doping region, the source-drain doping region being in contact with the sidewalls of the gate structure, and the distance from the bottom of the source-drain doping region to the first surface being less than the distance from the bottom of the body doping region to the first surface.

26. The superjunction trench-gate MOSFET structure according to claim 25, characterized in that, The conductivity type of the source-drain doping region is opposite to the conductivity type of the body doping region.

27. The superjunction trench-gate MOSFET structure according to claim 25, characterized in that, It further includes conductive plugs and contact doping regions located in the body doping regions and the source-drain doping regions on both sides of the gate structure, the distance from the bottom of the conductive plugs to the first surface being greater than the distance from the bottom of the source-drain doping region to the first surface, and the distance from the bottom of the conductive plugs to the first surface being less than the distance from the bottom of the body doping region to the first surface, and the contact doping region surrounding the surface of the conductive plugs below the bottom of the source-drain doping region.

28. The superjunction trench-gate MOSFET structure according to claim 27, wherein The conductivity type of the contact doping region is the same as the conductivity type of the body doping region.

29. The superjunction trench-gate MOSFET structure according to claim 25, wherein It further includes: an insulating layer located on the gate structure; a first conductive structure located on the insulating layer and the source-drain doping region.

30. The superjunction trench-gate MOSFET structure according to claim 22, characterized in that, It further includes: a second conductive structure located on the surface of the second surface.

31. The superjunction trench-gate MOSFET structure according to claim 22, wherein, The conductivity type of the body doping region is opposite to the conductivity type of the drift region.

32. The superjunction trench-gate MOSFET structure according to claim 22, characterized in that, The conductivity types of the first auxiliary doping region and the second auxiliary doping region are the same, and the conductivity types of the first auxiliary doping region and the second auxiliary doping region are opposite to the conductivity type of the drift region.

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