Diode device and method of forming a diode device

Abstract

This invention relates to diode devices and methods for forming diode devices. A diode device is provided, comprising a semiconductor substrate including a well region disposed therein, a first doped region and a second doped region disposed within the well region, a first contact region disposed within the first doped region, and an isolation structure disposed within the first doped region, wherein an oxide layer may be lining the surface of the isolation structure. The first doped region and the first contact region may have a first conductivity type, and the well region and the second doped region may have a second conductivity type different from the first conductivity type. The doping concentration of the first contact region may be higher than the doping concentration of the first doped region, and a portion of the first doped region may be disposed between the first contact region and the well region.

Description

Technical Field

[0001] The present invention generally relates to diode devices, and methods of forming diode devices. Background Art

[0002] Diode devices, such as avalanche photodiodes, are often used as image sensors. A typical diode device includes a P-type semiconductor material and an N-type semiconductor material arranged side by side to form a PN junction. In operation, the PN junction is reverse biased. When light is incident on the diode device, the photons are absorbed by the depletion region of the PN junction. This produces a detection current that is proportional to the intensity of the light incident on the diode device.

[0003] Current diode devices typically have high dark count rates due to abrupt PN junctions. In addition, premature edge oxide breakdown often occurs in current diode devices. These can affect the performance of the diode device. Therefore, it is desirable to provide an improved diode device with a lower dark count rate and a reduced likelihood of premature edge oxide breakdown. Summary of the invention

[0004] According to various non-limiting embodiments, a diode device may be provided, comprising: a semiconductor substrate including a well region disposed therein; a first doping region and a second doping region disposed in the well region; a first contact region disposed in the first doping region, the doping concentration of the first contact region may be higher than the doping concentration of the first doping region, and a portion of the first doping region may be disposed between the first contact region and the well region; and an isolation structure disposed in the first doping region; wherein an oxide layer may line a surface of the isolation structure. The first doping region and the first contact region may have a first conductivity type, and the well region and the second doping region may have a second conductivity type different from the first conductivity type.

[0005] According to various non-limiting embodiments, a method for forming a diode device may be provided, the method comprising: providing a semiconductor substrate; forming a well region in the semiconductor substrate; forming a first doping region and a second doping region in the well region; forming a first contact region in the first doping region, wherein the doping concentration of the first contact region may be higher than the doping concentration of the first doping region, and a portion of the first doping region may be disposed between the first contact region and the well region; and forming an isolation structure in the first doping region, and lining a surface of the isolation structure with an oxide layer. The first doping region and the first contact region have a first conductivity type, and the well region and the second doping region have a second conductivity type different from the first conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, the same reference numerals generally refer to the same parts in different views. In addition, the drawings are not necessarily drawn to scale, emphasis generally being placed on illustrating the principles of the invention. Non-limiting embodiments of the present invention will now be described for purposes of example only with reference to the following drawings, in which:

[0007] Figure 1 shows simplified cross-sectional views of diode devices according to various non-limiting embodiments;

[0008] Figures 2A to 2I The formation of Figure 1 A simplified cross-sectional view of a method of a diode device;

[0009] Figure 3A and 3B Shows the used Figure 1 A simplified cross-sectional view of a diode device;

[0010] Figure 4 shows a simplified cross-sectional view of a diode device according to an alternative non-limiting embodiment;

[0011] Figure 5 shows a simplified cross-sectional view of a diode device according to an alternative non-limiting embodiment;

[0012] Figure 6 Shows the used Figure 5 A simplified cross-sectional view of a diode device;

[0013] Fig. 7A and 7B A simplified top view and a simplified cross-sectional view, respectively, show a diode device according to an alternative non-limiting embodiment; and

[0014] Figure 8 Shows the used Fig. 7A and 7B Simplified cross-section diagram of a diode device. DETAILED DESCRIPTION

[0015] Embodiments generally relate to diode devices. More specifically, some embodiments relate to avalanche photodiodes (APDs), such as single-photon avalanche diodes (SPADs). Diode devices can be used in a variety of applications, such as, but not limited to, image sensing applications.

[0016] Various aspects of the present invention and certain features, advantages and details thereof will be explained more fully below with reference to the non-limiting examples shown in the accompanying drawings. Descriptions of well-known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the details of the present invention. However, it should be understood that in describing various aspects of the present invention, they are given only by way of illustration and not by way of limitation. According to the present invention, a person of ordinary skill in the art will be aware of various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the underlying inventive concept.

[0017] As used herein, approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that allows variation without resulting in a change in the associated basic function. Thus, a value modified by one or more terms (e.g., "approximately," "about") is not limited to the exact value specified. In some cases, approximate language may correspond to the precision of the instrument that measures the value. In addition, a direction is modified by one or more terms, such as "substantially," indicating that the direction will be applied within the normal tolerances of the semiconductor industry. For example, "substantially parallel" means extending substantially in the same direction within the normal tolerances of the semiconductor industry, and "substantially perpendicular" means an angle of 90 degrees within the normal tolerances of the semiconductor industry.

[0018] The terms used herein are only used for the purpose of describing specific examples and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" (and any form of including, such as "comprises" and "comprising"), "have" (and any form of having, such as "has" and "having"), "include" (and any form of including, such as "includes" and "including"), and "contain" (and any form of containing, such as "contains" and "containing") are open concatenated verbs. Therefore, a method or device that "comprises", "has", "includes" or "contains" one or more steps or elements has those one or more steps or elements, but is not limited to having only those one or more steps or elements. Likewise, a method step or an element of an apparatus that "comprises," "has," "includes," or "contains" one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0019] As used herein, the term "connected" when referring to two physical elements means a direct connection between the two physical elements. However, the term "coupled" may refer to a direct connection or a connection through one or more intermediate elements.

[0020] As used herein, the terms "may" and "might be" refer to the possibility of occurring under a set of circumstances; possessing a particular characteristic, feature, or function; and / or qualifying another verb by expressing and qualifying one or more abilities, capacities, or possibilities associated with the verb. Thus, the use of "may" and "might be" indicates that the modified term is clearly appropriate, capable, or suitable for the indicated ability, function, or use, while taking into account that in certain circumstances, the modified term may sometimes not be appropriate, capable, or suitable. For example, in certain circumstances, an event or ability is expected, while in other circumstances, the event or ability is unlikely to occur - this distinction can be expressed by the terms "may" and "might be".

[0021] Figure 1 1 shows a simplified cross-sectional view of a diode device 100 according to various non-limiting embodiments. The diode device 100 may be an avalanche photodiode (APD), such as a single photon avalanche diode (SPAD). Figure 1As shown, the diode device 100 may be symmetrical about a central vertical axis AA′.

[0022] Reference Figure 1 , the diode device 100 may include a semiconductor substrate 102. The semiconductor substrate 102 may include silicon. For example, Figure 1 As shown, semiconductor substrate 102 may include bulk silicon. Semiconductor substrate 102 may include a well region 104 disposed therein.

[0023] The diode device 100 may also include a first doped region 106, a second doped region 108, and another second doped region 110 disposed within the well region 104. The first doped region 106 may also be referred to as a sidewall region. The first doped region 106, the second doped region 108, and the another second doped region 110 may be disposed horizontally adjacent to each other, wherein the first doped region 106 is located between the second doped region 108 and the another second doped region 110. The first doped region 106 and the second doped region 108 may be spaced apart, with a portion of the well region 104 disposed therebetween. Similarly, the first doped region 106 and the another second doped region 110 may be spaced apart, with a portion of the well region 104 disposed therebetween. The first doped region 106, the second doped region 108, and the another second doped region 110 may be substantially horizontally aligned along the top surface 102a of the substrate 102.

[0024] The first doped region 106 may include a first segment 106a substantially horizontally aligned along the top surface 102a of the semiconductor substrate 102 and a second segment 106b disposed below the first segment 106a. The second segment 106b may be substantially perpendicular to the first segment 106a. The first segment 106a may be an elongated segment extending horizontally and longitudinally along the top surface 102a of the semiconductor substrate 102; however, the second segment 106b may be an elongated segment extending vertically and longitudinally toward the bottom surface 102b of the semiconductor substrate 102. Figure 1 , the length L of the first section 106a 106a can be larger than the width W of the second section 106b 106b For example, the length L 106a can be in the range of about 2um to about 3um, and the width W 106b It may be in the range of about 1 um to about 2 um.

[0025] Each of the second doping region 108 and the other second doping region 110 may be an elongated region having a substantially uniform width and extending longitudinally along a vertical direction toward the bottom surface 102b of the semiconductor substrate 102. Figure 1 As shown, the first doping region 106 may extend further than the second doping region 108 and the further second doping region 110 in a direction away from the top surface 102a of the semiconductor substrate 102. In other words, the depth D of the first doping region 106 is 106The depth D of the second doping region 108 may be greater than 108 and the depth D of another second doping region 110 110 For example, the depth D 106 The range may be from about 5um to about 10um; and the depth D 108 , D 110 They may be approximately equal and each range from about 2 um to about 5 um.

[0026] The first contact region 112 and the further first contact region 114 may be disposed in the first doped region 106 (particularly, in the first section 106a of the first doped region 106). Figure 1 As shown, the first contact region 112 and the well region 104 may be spaced apart, and a portion of the first doped region 106 may be disposed between them. Similarly, another first contact region 114 and the well region 104 may be spaced apart, and a portion of the first doped region 106 may be disposed between them. The second contact region 116 may be disposed in the second doped region 108, and another second contact region 118 may be disposed in another second doped region 110. Figure 1 As shown, the second contact region 116 may be disposed along one side of the second doped region 108, and the further second contact region 118 may be disposed along one side of the further second doped region 110, wherein these sides may face away from the first doped region 106. The first contact region 112, the further first contact region 114, the second contact region 116, and the further second contact region 118 may be substantially horizontally aligned along the top surface 102a of the substrate 102. The depth D of the first contact region 112, the further first contact region 114, the second contact region 116, and the further second contact region 118 may be substantially horizontally aligned along the top surface 102a of the substrate 102. 112 , D 114 , D 116 , D 118 They may be approximately equal and each range from about 0.1 um to about 0.2 um.

[0027] Each of the semiconductor substrate 102, the well region 104, the first doped region 106, the second doped region 108, the other second doped region 110, the first contact region 112, the other first contact region 114, the second contact region 116, and the other second contact region 118 may include one or more dopants. The semiconductor substrate 102, the first doped region 106, the first contact region 112, and the other first contact region 114 may be of the first conductivity type (in other words, may include dopants having the first conductivity type). The well region 104, the second doped region 108, the other second doped region 110, the second contact region 116, and the other second contact region 118 may be of the second conductivity type (in other words, may include dopants having the second conductivity type), wherein the second conductivity type may be different from the first conductivity type. In an exemplary non-limiting embodiment, the first conductivity type may be a P-type, and the second conductivity type may be an N-type. However, the first conductivity type may be substituted by an N-type, and the second conductivity type may be substituted by a P-type. The P-type dopant may include, but is not limited to, boron (B), indium (In), or a combination thereof, and the N-type dopant may include, but is not limited to, phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. Since the first doping region 106 and the well region 104 may have different conductivity types, a first vertical PN junction 150 and a second vertical PN junction 152 may be formed. Figure 1 As shown, the first vertical PN junction 150 may face the second doping region 108, and the second vertical PN junction 152 may face another second doping region 110. Figure 1 ) may be formed across each of the first and second vertical PN junctions 150 , 152 .

[0028] The doping concentration C112 of the first contact region 112 may be approximately equal to the doping concentration C114 of the other first contact region 114. Each of the doping concentrations C112 and C114 of the first contact region 112 and the other first contact region 114 may be higher than the doping concentration C106 of the first doping region 106. The doping concentration C106 of the first doping region 106 may in turn be higher than the doping concentration C104 of the well region 104. In other words, C112≈C114>C106>C104. The doping concentrations C116 and C118 of the second contact region 116 and the other second contact region 118 may be approximately equal, and the doping concentrations C108 and C110 of the second doping region 108 and the other second doping region 110 may be approximately equal. The doping concentrations C116 and C118 may be higher than the doping concentrations C108 and C110, and the doping concentrations C108 and C110 may in turn be higher than the doping concentration C104. In other words, C116≈C118>C108≈C110>C104. For example, the doping concentration C104 of the well region 104 is in the range of about 1×10 15 / cm 3 About 1x10 17 / cm3 , the doping concentration C106 of the first doping region 106 is about 1×10 16 / cm 3 About 1x10 17 / cm 3 In the range of about 1×10 16 / cm 3 About 1x10 17 / cm 3 , the doping concentrations C112 and C114 of the first contact region 112 and the other first contact region 114 are each in the range of about 1×10 18 / cm 3 About 1x10 20 / cm 3 , and the doping concentrations C116 and C118 of the second contact region 116 and the other second contact region 118 are each in the range of about 1×10 18 / cm 3 About 1x10 20 / cm 3 .

[0029] like Figure 1 As shown, the diode device 100 may further include a first isolation element 120 substantially horizontally disposed between the first doping region 106 and the second doping region 108, and a second isolation element 122 substantially horizontally disposed between the first doping region 106 and another second doping region 110. The first and second isolation elements 120, 122 may be substantially horizontally aligned along the top surface 102a of the semiconductor substrate 102. Figure 1 As shown, the first isolation element 120 may contact the first doped region 106, and a portion of the first doped region 106 may be disposed between the first isolation element 120 and the first contact region 112. Similarly, the second isolation element 122 may contact the first doped region 106, and a portion of the first doped region 106 may be disposed between the second isolation element 122 and another first contact region 114. Figure 1 As shown, the first isolation element 120 may partially extend into the second doped region 108 and the second isolation element 122 may partially extend into the other second doped region 110. Each of the first and second isolation elements 120, 122 may include an isolation / electrical insulating material, such as, but not limited to, silicon oxide. For example, each of the first and second isolation elements 120, 122 may be a shallow trench isolation (STI) element.

[0030] In addition, the diode device 100 may further include an isolation structure 124 disposed in the first doped region 106. The isolation structure 124 may be horizontally disposed between the first contact region 112 and the further first contact region 114. Figure 1 As shown, the isolation structure 124 may be an elongated structure and may extend vertically in a direction away from the top surface 102a of the semiconductor substrate 102 toward the bottom surface 102b of the semiconductor substrate 102. For example, the isolation structure 124 may be a deep trench isolation structure and may include an isolation material, such as, but not limited to, polysilicon. As described above, the length L of the first segment 106a of the first doped region 106 is 106a The width W of the second section 106 b of the first doping region 106 may be greater than 106b Therefore, if Figure 1 As shown, the first section 106 a of the first doped region 106 may extend beyond the second section 106 b of the first doped region 106 in a direction away from the isolation structure 124 .

[0031] like Figure 1 As shown, the oxide layer 126 may be disposed within the first doped region 106 and may line the surface of the isolation structure 124, wherein the surface may include the side and bottom of the isolation structure 124. The oxide layer 126 may include an oxide material, such as but not limited to silicon oxide. The oxide layer 126 may be spaced apart from the well region 104, with a portion of the first doped region 106 disposed therebetween. Figure 1 , the oxide layer 126 may include a first portion 126a, a second portion 126b, and a third portion 126c. The first portion 126a and the third portion 126c may be disposed in the first segment 106a of the first doped region 106, and may be substantially horizontally aligned along the top surface 102a of the semiconductor substrate 102. The first portion 126a of the oxide layer 126 may be disposed between (and may contact) the first contact region 112 and the isolation structure 124; and the third portion 126c of the oxide layer 126 may be disposed between (and may contact) the other first contact region 114 and the isolation structure 124. The second portion 126b of the oxide layer 126 may be disposed below the first portion 126a and the third portion 126c.

[0032] like Figure 1 As shown, the first portion 126a and the third portion 126c of the oxide layer 126 may extend further in a direction away from the surface of the isolation structure 124 than the second portion 126b of the oxide layer 126. Figure 1 As shown, the thickness T of the first portion 126a is 126a and the thickness T of the third portion 126c 126c may be greater than the thickness T of the second portion 126b 126b For example, the thickness T 126a and thickness T126c may be approximately equal and each may range from about 200 nm to about 400 nm; and the thickness T 126b The range is about 20 nm to about 80 nm.

[0033] like Figure 1 As shown, the first portion 126a of the oxide layer 126 and the third portion 126c of the oxide layer 126 may extend further than the first contact region 112 and the further first contact region 114 in a direction away from the top surface 102a of the semiconductor substrate 102. In other words, the depth D of the first portion 126a of the oxide layer 126 is 126a and the depth D of the third portion 126c of the oxide layer 126 126c It may be greater than the depth D of the first contact region 112 112 and the depth D of another first contact region 114 114 For example, the depth D of the first and third portions 126a, 126c of the oxide layer 126 is 126a , D 126c May be approximately equal and may each be in the range from about 0.3 um to about 0.6 um.

[0034] like Figure 1 As shown, the diode device 100 may also include a plurality of dielectric elements 128a to 128f and a plurality of electrodes 130a to 130e disposed above the top surface 102a of the semiconductor substrate 102. The dielectric elements 128a to 128f may be spaced apart from each other and the electrodes 130a to 130e may be disposed in the space between each pair of adjacent dielectric elements 128a to 128f. The electrodes 130a to 130e may be in electrical contact with the corresponding regions / structures 116, 112, 124, 114, 118 of the diode device 100 and may include a conductive material, such as a metal, such as but not limited to aluminum, copper, tungsten, alloys thereof, or combinations thereof. The dielectric elements 128a to 128f may include a dielectric material, such as but not limited to an oxide, a nitride, or a combination thereof.

[0035] Figures 2A to 2I A simplified cross-sectional view of a method for manufacturing a diode device 100 according to various non-limiting embodiments is shown. Figures 2A to 2I Some reference numerals are omitted.

[0036] Reference Figure 2A The method may include providing a semiconductor substrate 102 of a first conductivity type.

[0037] Reference Figure 2BThe method may further include forming a well region 104 in the semiconductor substrate 102. The well region 104 may be formed by doping selected regions in the semiconductor substrate 102 with a dopant of the second conductivity type. This may be accomplished using any method known to one of ordinary skill in the art.

[0038] Reference Figure 2C The method may further include forming first and second isolation elements 120, 122 and an oxide element 202 horizontally located between the isolation elements 120, 122, wherein the oxide element 202 may be similar to the first and second isolation elements 120, 122. The isolation elements 120, 122 and the oxide element 202 may be formed by etching the semiconductor substrate 102 to form openings therein and filling the openings with an isolation material. The isolation elements 120, 122 may be spaced apart from the oxide element 202 such that gap portions 204a, 204b within the well region 104 may exist between the oxide element 202 and the first and second isolation elements 120, 122.

[0039] refer to Figures 2D to 2H The method may further include forming a first doping region 106 , a second doping region 108 and another second doping region 110 in the well region 104 , forming an isolation structure 124 and an oxide layer 126 in the first doping region 106 , and forming contact regions 112 , 114 , 116 , 118 .

[0040] like Figure 2D As shown, the method may include forming an intermediate doped region 206 of the first conductivity type below the oxide element 202. The intermediate doped region 206 may be formed by doping a selected region of the semiconductor substrate 102 below the oxide element 202 using any method known to a person of ordinary skill in the art. Dopants within the intermediate doped region 206 may diffuse through the well region 104, such that the intermediate doped region 206 may grow larger over time and extend horizontally beyond the oxide element 202.

[0041] like Figure 2E As shown, the oxide element 202 and the intermediate doped region 206 may be etched to form an opening 208 .

[0042] like Figure 2F As shown, an oxide liner may be formed along the interior surface of the opening 208. The oxide liner and the etched oxide element 202 together may form the oxide layer 126. The oxide liner may be formed by oxidizing the interior surface of the opening 208, but may alternatively be formed by other processes known to those of ordinary skill in the art.

[0043] like Figure 2G As shown, isolation material may be deposited into opening 208 to form isolation structure 124 .

[0044] like Figure 2H As shown, the gap portions 204a, 204b in the semiconductor substrate 102 may be doped with a dopant of the first conductivity type. The gap portions 204a, 204b may be doped using any process known to a person of ordinary skill in the art. Figure 2H As shown in FIG. 1 , a first doped region 106 including doped gap portions 204a, 204b and an intermediate doped region 206 may be formed. Figure 2H As shown, the method may include forming a second doped region 108, another second doped region 110, a first contact region 112, another first contact region 114, a second contact region 116, and another second contact region 118 by doping respective selected regions of the semiconductor substrate 102. Similarly, each of these regions 108, 110, 112, 114, 116, 118 may be doped using any process known to a person of ordinary skill in the art.

[0045] Reference Fig.2I , the method may further include forming dielectric elements 128a to 128f and electrodes 130a to 130e. The dielectric elements 128a-128f and the electrodes 130a-130e may be formed using back-end processes known to those of ordinary skill in the art. For example, the dielectric elements 128a-128f may be formed by depositing a dielectric material over the top surface 102a of the semiconductor substrate 102 and etching the dielectric material to form spaced apart dielectric elements 128a to 128f; and the electrodes 130a to 130e may be formed by depositing a conductive material in the space between each pair of adjacent dielectric elements 128a to 128f.

[0046] The above sequence of the method is intended to be exemplary only, and the method is not limited to the sequence specifically described above unless otherwise specifically stated. Figure 2D To form the intermediate doped region 206 in the semiconductor substrate 102, the oxide element 202 and a portion of the semiconductor substrate 102 below the oxide element 202 may first be etched to form an opening (e.g., using a deep reactive ion etching (DRIE) technique). Next, an oxide liner may be deposited along the inner surface of the opening to form the oxide layer 126, and then the intermediate doped region 206 may be formed by implanting dopants through the inner surface of the opening into the semiconductor substrate 102. The dopants may be implanted using any process known to those of ordinary skill in the art, such as, but not limited to, tilted implantation.

[0047] Figure 3A and 3B A simplified cross-sectional view illustrating the diode device 100 in use is shown. Specifically, Figure 3AThe diode device 100 is shown receiving front illumination, in other words, receiving illumination from the front side (specifically, the top side 102a) of the diode device 100; however, Figure 3B The diode device 100 is shown receiving backside illumination, in other words, illumination received from the back side of the diode device 100 (specifically, the bottom side 102b).

[0048] exist Figure 3A and 3B , the second doped region 108 and the further second doped region 110 may be of N-type and may serve as the cathode of the diode device 100; however, the first doped region 106 may be of P-type and may serve as the anode of the diode device 100. In use, the electrodes 130a, 130e electrically contacting the second contact region 116 and the further second contact region 118 may be grounded (Gr). The electrode 130b electrically contacting the first contact region 112, the electrode 130c electrically contacting the isolation structure 124, and the electrode 130d electrically contacting the further first contact region 114 may be connected to external voltages V1, V2, V3, respectively. The external voltages V1, V2, V3 may be negative voltages, wherein the magnitudes of the external voltages V1, V3 may be greater than the magnitude of the external voltage V2. Therefore, this may reverse bias the first and second vertical PN junctions 150, 152.

[0049] Reference Figure 3A , when photon 302( Figure 3A When a photon 302 is incident on the diode device 100 from the front side, the photon 302 may pass through the isolation structure 124 and the first doped region 106 to pass through one of the vertical PN junctions 150, 152 to reach the depletion region. The photon 302 may be absorbed in the depletion region to generate electron-hole pairs. The free electrons may diffuse toward the second doped region 108 / another second doped region 110 (cathode), and the free holes may diffuse toward the first doped region 106 (anode). Please refer to Figure 3B , when photon 302 (in Figure 3B When a photon 302 is incident on the diode device 100 from the back side, the photon 302 may pass through the semiconductor substrate 102, the well region 104, and the first doped region 106 to pass through one of the vertical PN junctions 150, 152 to reach the depletion region. Similarly, the photon 302 may be absorbed in the depletion region, and the free electrons and holes may move toward the second doped region 108 / another second doped region 110 (cathode) and the first doped region 106 (anode), respectively. When a plurality of photons from the front side illumination / back side illumination are incident on the diode device 100, the electron-hole pairs generated by the photons may form a detection current in the diode device 100, wherein the detection current may be measurable and may be proportional to the intensity of the front side illumination / back side illumination incident on the diode device 100.

[0050] It should be understood that the conductivity types of regions 106, 108, 110 may be the same as those described above with reference to Figure 3A and 3B This diode device 100 can be operated in a similar manner as described above, but the directions of motion of the free electrons and free holes are opposite. Figure 3A and 3B 1 and 2. It is shown that both front and back side illumination can be applied to the same diode device 100, but in various non-limiting embodiments, the semiconductor substrate 102 can be configured to be thinner for a diode device operating with back side illumination.

[0051] By including the elongated isolation structure 124, the diode device 100 may include vertical PN junctions 150, 152. These vertical PN junctions 150, 152 may extend deeper into the semiconductor substrate 102 than, for example, horizontal PN junctions. Therefore, the diode device 100 may be able to detect illumination having longer wavelengths, which may penetrate deeper into the semiconductor substrate 102. Therefore, the photon detection probability (PDP) or photon detection efficiency (PDE) of the diode device 100 in the near infrared (long wavelength) range may be higher. In addition, the crosstalk of the diode device 100 may be reduced by including the elongated isolation structure 124.

[0052] Furthermore, by including the second doped region 108 and the further second doped region 110 as elongated regions, the resistance of the diode device 100 within the well region 104 can be reduced. Thus, the jitter of the device 100 can be reduced and the timing response of the diode device 100 can be improved.

[0053] In addition, as described above, the first contact region 112 of the diode device 100 may be disposed within the first doped region 106 (having a lower doping concentration than the first contact region 112), and a portion of the first doped region 106 may be disposed between the first contact region 112 and the well region 104. In other words, the diode device 100 may include a region having a graduated doping concentration (formed by the first doped region 106 and the first contact region 112). The use of such a graduated doping concentration may allow the PN junctions 150, 152 to be less abrupt and thus may reduce the band-to-band tunneling effect. In addition, the inclusion of the first doped region 106 may also help to further move the PN junctions 150, 152 away from the top surface 102a of the semiconductor substrate 102 and away from the isolation elements 120, 122. As a result, the diode device 100 may have a lower dark count rate (DCR).

[0054] Furthermore, as described above, the oxide layer 126 may include a first portion 126a (between the first contact region 112 and the isolation structure 124) and a third portion 126c (between the other first contact region 114 and the isolation structure 124), wherein the first and third portions 126a and 126c are thicker than the second portion 126b of the oxide layer 126 below them. These thicker oxide portions 126a, 126c are close to the more heavily doped first contact region 112 and the other first contact region 114, which may help reduce the possibility of oxide leakage and premature edge oxide collapse.

[0055] Figure 4 A simplified cross-sectional view of a diode device 400 according to an alternative non-limiting embodiment is shown. The diode device 400 may be similar to the diode device 100, and therefore, common features are numbered with the same reference numerals and need not be discussed. For clarity, Figure 4 Some reference numerals are omitted.

[0056] like Figure 4 As shown, instead of bulk silicon, the semiconductor substrate 102 of the diode device 400 may include a silicon-on-insulator (SOI) substrate, wherein the SOI substrate may include a first silicon layer 1021, a second silicon layer 1023, and an insulating layer 1022 between the first and second silicon layers 1021, 1023. The first and second silicon layers 1021, 1023 may be of a first conductivity type. The insulating layer 1022 may allow light to pass through and may be, for example, a buried oxide layer; and the second silicon layer 1023 may be an epitaxial layer. In addition to being Figure 2A In addition to providing an SOI substrate other than bulk silicon, the diode device 400 can be similar to the above referenced Figures 2A to 2I The diode device 400 is fabricated in a similar manner to the fabrication of the diode device 100 described above. Similar to the diode device 100, the diode device 400 may be operated with front side illumination or back side illumination.

[0057] Figure 5 A simplified cross-sectional view of a diode device 500 is shown in accordance with an alternative non-limiting embodiment. The diode device 500 may be similar to the diode device 100 and, therefore, common features are numbered with the same reference numerals and need not be discussed.

[0058] like Figure 5As shown, compared with the diode device 100, the diode device 500 may further include a first additional isolation structure 524 and a second additional isolation structure 525. The first additional isolation structure 524 may be disposed horizontally adjacent to the second doping region 108, such that the second doping region 108 may be disposed between the first additional isolation structure 524 and the first doping region 106. Similarly, the second additional isolation structure 525 may be disposed horizontally adjacent to another second doping region 110, such that another second doping region 110 may be disposed between the second additional isolation structure 525 and the first doping region 106. Each additional isolation structure 524, 525 may be similar to the isolation structure 124. For example, each additional isolation structure 524, 525 may be a deep trench isolation (DTI) structure and may include an isolation material, such as, but not limited to, polysilicon.

[0059] The diode device 100 may also include a first additional oxide layer 526 lining the surface of the first additional isolation structure 524, and a second additional oxide layer 527 lining the surface of the second additional isolation structure 525. The additional oxide layers 526, 527 may be similar to the oxide layer 126 and may include an oxide material, such as, but not limited to, silicon oxide. Each of the first additional oxide layer 526 and the second additional oxide layer 527 may include a first portion 526a, 527a, a second portion 526b, 527b, and a third portion 526c, 527c. Figure 5 As shown, the first portion 526a, 527a and the third portion 526c, 527c of each additional oxide layer 526, 527 may be substantially horizontally aligned along the top surface 102a of the semiconductor substrate 102, and the second portion 526b, 527b may be disposed below the corresponding first portion 526a, 527a and the third portion 526c, 527c.

[0060] The first additional oxide layer 526 may contact the second doping region 108 and may partially extend into the second doping region 108. Similarly, the second additional oxide layer 527 may contact another second doping region 110 and may partially extend into another second doping region 110. Specifically, Figure 5 As shown, the first portion 526a of the first additional oxide layer 526 may partially extend into the second contact region 116; and the first portion 527a of the second additional oxide layer 527 may partially extend into the other second contact region 118. For each additional oxide layer 526, 527, the thickness T of the first portion 526a, 527a is 526a , T 527a The thickness T of the third portion 526c may be approximately equal to 526c , T 527c , and may be greater than the thickness T of the second portion 526b, 527b 526b , T 527bFurther, for each additional oxide layer 526, 527, the depth D of the first portion 526a, 527a is 526a , D 527a The depth D of the third portion 526c, 527c may be approximately equal to 526c , D 527c , and may be less than the depth D of the first and third portions 126a, 126c of the oxide layer 126. 126a , D 126c .

[0061] Compared to the diode device 100, the diode device 500 may include additional dielectric elements 528a, 528f, and first and second additional electrodes 530a, 530b. The first additional electrode 530a may be in electrical contact with the first additional isolation structure 524, and the second additional electrode 530b may be in electrical contact with the second additional isolation structure 525. In addition to using other processes known to those skilled in the art to form the additional isolation structures 524, 525, the additional oxide layers 526, 527, the additional dielectric elements 528a, 528f, and the additional electrodes 530a, 530b, the above-mentioned processes may also be used. Figures 2A to 2I The diode device 500 is manufactured in a similar manner to the manufacturing of the diode device 100 described above.

[0062] Figure 6 The diode device 500 is shown in use. The diode device 500 can be operated with front illumination or back illumination. In use, the electrodes 130a, 130e electrically contacting the second contact region 116 and the further second contact region 118 can be grounded (Gr). The electrode 130b electrically contacting the first contact region 112, the electrode 130c electrically contacting the isolation structure 124, and the electrode 130d electrically contacting the further first contact region 114 can be connected to external voltages V1, V2, V3, respectively. The external voltages V1, V2, V3 can be negative voltages, wherein the magnitude of the external voltages V1, V3 can be greater than the magnitude of the external voltage V2. Therefore, this can reverse bias the first and second vertical PN junctions 150, 152.

[0063] In addition, the first additional electrode 530a may be connected to a first additional external voltage V4, and the second additional electrode 530b may be connected to a second additional external voltage V5. The additional external voltages V4 and V5 may also be negative voltages, wherein the amplitudes of V4 and V5 may be lower than the amplitudes of V1 and V3 applied to the first doping region 106. For example, the amplitudes of V4 and V5 may be approximately equal to the amplitude of V2 applied to the isolation structure 124. Therefore, a first electric field / drift electric field E1 in a direction from the second doping region 108 (at a higher potential) to the first doping region 106 (at a lower potential) and a second electric field / drift electric field E2 in a direction from another second doping region 110 (at a higher potential) to the first doping region 106 (at a lower potential) may be formed.

[0064] The diode device 500 can operate in a similar manner to the diode device 100, except that the electric fields E1, E2 can sweep the free holes toward the first doped region 106 (anode). Therefore, the speed and signal integrity of the diode device 500 can be higher than the speed and signal integrity of the diode device 100. This can improve the response time and reduce the jitter of the diode device 500.

[0065] Fig. 7A shows a simplified top view of a diode structure 700 including a plurality of diode devices 700A, 700B according to an alternative non-limiting embodiment, and Figure 7B A simplified cross-sectional view of the diode device 700A along line BB' is shown. The diode device 700A may be similar to the diode device 100, and therefore, common features are labeled with the same reference numerals and need not be discussed. For simplicity, Fig. 7A The first and second isolation elements 120, 122 are not shown. Fig. 7A Only two diode devices 700A, 700B are shown, but the diode structure 700 may include fewer or more diode devices.

[0066] like Figure 7B As shown, the semiconductor substrate 102 of the diode device 700A may be an SOI substrate. However, the semiconductor substrate 102 of the diode device 700A may alternatively be formed of bulk silicon.

[0067] like Fig. 7A and 7B As shown, in each diode device 700A, 700B, the second contact region 116 and the further second contact region 118 may each include a cylindrical region 116, 118 extending into the semiconductor substrate 102. The second doped region 108, the further second doped region 110, the first contact region 112, and the further first contact region 114 may also each include a cylindrical region 108, 110, 112, 114 extending into the semiconductor substrate 102. Fig. 7A and 7B As shown, the second contact region 116 may be disposed in the second doping region 108 and may be approximately at the center of the second doping region 108 , and another second contact region 118 may be disposed in another second doping region 110 and may be approximately at the center of the another second doping region 110 .

[0068] In addition, the well region 104 may include first and second cylindrical regions 1041, 1042. Figure 7B As shown, the first and second cylindrical regions 1041, 1042 may be connected to form a continuous well region 104 in the semiconductor substrate 102. The diameter d of each cylindrical well region 1041, 1042 may range from about 4um to about 40um. Similarly, the first doped region 106 may include a cylindrical region 1061 and a second cylindrical region 1062. Figure 7B As shown, the first and second cylindrical regions 1061, 1062 may also be connected to form a continuous first doped region 106 having first and second segments 106a, 106b, similar to those described above for the diode device 100. Figure 7B As shown, the continuous first doped region 106 may be disposed within the well region 104 .

[0069] In addition, if Fig. 7A As shown, the isolation structure 124 of each diode device 700A, 700B may include a first hollow cylindrical structure 1241 and a second hollow cylindrical structure 1242. Such cylindrical structures 1241, 1242 may be referred to as nanorods, and the diode structure 700 may be referred to as including a nanorod array. Figure 7B As shown, the first and second hollow cylindrical structures 1241 , 1242 may be connected by a base 1243 to form a continuous isolation structure 124 having a trench 125 therein. The continuous isolation structure 124 may be disposed within the continuous first doped region 106 .

[0070] like Fig. 7A As shown, regions 116, 108, 1041, 1061, 112 and first cylindrical isolation structure 1241 may be arranged to form a first concentric arrangement; and regions 118, 110, 1042, 1062, 114 and second cylindrical isolation structure 1242 may be arranged to form a second concentric arrangement. These first and second concentric arrangements may be arranged within oxide layer 702. Fig. 7A and 7B As shown, the first and second concentric arrangements may be spaced apart with the trench 125 disposed therebetween, and the trench 125 may include oxide from the oxide layer 702 .

[0071] In addition, the first cylindrical isolation structure 1241 may be spaced apart from the region 1061, and the second cylindrical isolation structure 1242 may be spaced apart from the region 1062. Therefore, a portion of the oxide layer 702 may form first and second hollow cylindrical oxide layers 1261, 1262. The first cylindrical oxide layer 1261 may be disposed in the elongated hole of the first cylindrical isolation structure 1241, and may be lined with the surface of the first cylindrical isolation structure 1241 in this hole; however, the second cylindrical oxide layer 1262 may be disposed in the elongated hole of the second cylindrical isolation structure 1242, and may be lined with the surface of the second cylindrical isolation structure 1242 in this hole. Figure 7B As shown, the first and second cylindrical oxide layers 1261, 1262 can be connected to form a continuous oxide layer 126 lining the surface of the continuous isolation structure 124, wherein the continuous oxide layer 126 can also have first, second and third portions 126a, 126b, 126c similar to those described above with reference to the diode device 100.

[0072] The diode device 700A may further include electrodes 130a to 130e disposed above the top surface 102a of the semiconductor substrate 102, and instead of the single electrode 130c in electrical contact with the isolation structure 124, two separate electrodes 130c1, 130c2 may be in electrical contact with the isolation structure 124. The diode device 700A may further include a first additional electrode 730a and a second additional electrode 730b in electrical contact with the first contact region 112 and the further first contact region 114, respectively. The dielectric elements 128a to 128i may be disposed above the top surface 102a of the semiconductor substrate 102, and the electrodes 103a to 130e, 730a, 730b may be disposed between each pair of adjacent dielectric elements 128a to 128i.

[0073] Figure 8The diode device 700A in use is shown. The diode device 700A can be operated with front illumination or back illumination. In use, the electrodes 130a, 130e can be connected to ground (Gr). The electrode 130b electrically contacting the first contact area 112 can be connected to an external voltage V1, the electrodes 130c1, 130c2 electrically contacting the isolation structure 124 can be connected to an external voltage V2, and the electrode 130d electrically contacting the other first contact area 114 can be connected to an external voltage V3. The external voltages V1, V2, V3 can be negative voltages, wherein the amplitude of the external voltages V1, V3 can be greater than the amplitude of the external voltage V2. Therefore, this can reverse bias the first and second vertical PN junctions 150, 152. In addition, the first additional electrode 730a can be connected to a first additional external voltage V4, and the second additional electrode 730b can be connected to a second additional external voltage V5. The first and second additional voltages V4, V5 may also be negative voltages, wherein the magnitudes of these first and second additional voltages V4, V5 may be approximately equal to the magnitudes of the external voltages V1, V3. The diode device 700A may operate in a similar manner to the diode device 100 described above.

[0074] By using nanorods as isolation structures 124, light absorption of diode device 700A can be increased. In other words, more photons can be absorbed in the depletion region formed across PN junctions 150, 152. Therefore, the PDE of diode device 700A can be higher than that of diode device 100.

[0075] The present invention may be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the foregoing embodiments are to be considered in all respects as illustrative rather than limiting the present invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than by the foregoing description, and all changes within the meaning and scope of the equivalents of the claims are intended to be included therein.

Claims

1. A diode device, comprising: a semiconductor substrate including a well region disposed therein; A first doping region and a second doping region are disposed in the well region; A first contact region disposed in the first doping region, wherein a doping concentration of the first contact region is higher than a doping concentration of the first doping region, and wherein a portion of the first doping region is disposed between the first contact region and the well region; and An isolation structure is arranged in the first doping region; wherein the oxide layer is lined on the surface of the isolation structure, Wherein, the oxide layer comprises: A first portion is disposed between the first contact region and the isolation structure; and The second part is arranged below the first part, wherein the first portion extends further than the second portion in a direction away from the surface of the isolation structure, The first doped region and the first contact region have a first conductivity type, and the well region and the second doped region have a second conductivity type different from the first conductivity type.

2. The diode device according to claim 1, wherein The first portion of the oxide layer contacts the first contact region and the isolation structure.

3. The diode device according to claim 1, wherein: The first portion of the oxide layer and the first contact region are substantially horizontally aligned along a top surface of the semiconductor substrate; as well as The first portion of the oxide layer extends further than the first contact region in a direction away from the top surface of the semiconductor substrate.

4. The diode device of claim 1, wherein: The first doped region includes: a first section substantially horizontally aligned along a top surface of the semiconductor substrate; and A second section is arranged below the first section; The first section extends beyond the second section in a direction away from the isolation structure.

5. The diode device of claim 1, wherein: The isolation structure is a deep trench isolation structure.

6. The diode device of claim 1, wherein: A portion of the well region is disposed between the first doping region and the second doping region.

7. The diode device according to claim 1, further comprising a second contact region of the second conductivity type, disposed in the second doped region, wherein: The doping concentration of the second contact region is higher than the doping concentration of the second doping region.

8. The diode device as claimed in claim 1, further comprising another first contact region of the first conductivity type, disposed in the first doped region, wherein: The doping concentration of the further first contact region is higher than the doping concentration of the first doping region.

9. The diode device according to claim 1, further comprising another second doping region of the second conductivity type and another second contact region of the second conductivity type, wherein the another second doping region of the second conductivity type is arranged in the well region, and the another second contact region of the second conductivity type is arranged in the another second doping region, wherein: The further second contact region has a higher doping concentration than the further second doping region. 10 . The diode device as claimed in claim 1 , further comprising an isolation element horizontally disposed between the first doped region and the second doped region.

11. The diode device of claim 10, wherein: The isolation element contacts the first doped region.

12. The diode device of claim 10, wherein: The isolation element partially extends into the second doped region.

13. The diode device of claim 1, wherein: The semiconductor substrate includes a silicon-on-insulator substrate.

14. The diode device of claim 1, further comprising an additional isolation structure disposed horizontally adjacent to the second doped region, wherein: The second doped region is horizontally located between the additional isolation structure and the first doped region.

15. The diode device of claim 14, wherein: An additional oxide layer is lined on the surface of the additional isolation structure, wherein the additional oxide layer partially extends into the second doping region.

16. The diode device of claim 15, wherein: The additional oxide layer includes a first portion partially extending into the second doping region and a second portion disposed under the first portion, wherein a thickness of the first portion is greater than a thickness of the second portion.

17. The diode device of claim 1, wherein: The isolation structure includes a first hollow cylindrical structure and a second hollow cylindrical structure connected to form a continuous cylindrical structure having a trench therein, and wherein the trench includes an oxide.

18. The diode device of claim 1, wherein: The diode device includes an avalanche photodiode.

19. A method of forming a diode device, the method comprising: providing a semiconductor substrate; forming a well region in the semiconductor substrate; forming a first doped region and a second doped region in the well region; forming a first contact region in the first doping region, wherein the doping concentration of the first contact region is higher than the doping concentration of the first doping region, and wherein a portion of the first doping region is disposed between the first contact region and the well region; and An isolation structure is formed in the first doped region, and an oxide layer is lined on the surface of the isolation structure. Wherein, the oxide layer comprises: A first portion is disposed between the first contact region and the isolation structure; and The second part is arranged below the first part, wherein the first portion extends further than the second portion in a direction away from the surface of the isolation structure, The first doped region and the first contact region have a first conductivity type, and the well region and the second doped region have a second conductivity type different from the first conductivity type.

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