Method for producing a radiation-emitting semiconductor chip, radiation-emitting semiconductor chip, and radiation-emitting component

Abstract

A method for producing a radiation-emitting semiconductor chip (1) is provided, comprising the following steps: providing a semiconductor wafer (2), applying a first contact layer (5) to the semiconductor wafer (2), attaching a carrier device (8) to the semiconductor wafer (2), dividing the semiconductor wafer (2) into semiconductor bodies (13), and applying a second contact layer (14) to the semiconductor bodies (13). Furthermore, a radiation-emitting semiconductor chip and a radiation-emitting component are provided.

Description

Technical Field

[0001] A method for producing a radiation-emitting semiconductor chip is proposed. Furthermore, a radiation-emitting semiconductor chip and a radiation-emitting component are proposed. Summary of the Invention

[0002] The object to be achieved is to provide a method for producing a radiation-emitting semiconductor chip, by means of which the radiation-emitting semiconductor chip can be produced particularly cost-effectively. Furthermore, a correspondingly produced radiation-emitting semiconductor chip and a correspondingly produced radiation-emitting component are to be provided.

[0003] According to at least one embodiment of the method, a semiconductor wafer is provided. The semiconductor wafer, for example, includes a first semiconductor layer sequence of a first conductivity type. Furthermore, the semiconductor wafer, for example, includes a second semiconductor layer sequence of a second conductivity type different from the first conductivity type. The first semiconductor layer sequence is, for example, p-doped and thus has p-type conductivity. Furthermore, the second semiconductor layer sequence is, for example, n-doped and thus has n-type conductivity. Thus, in this case, the first conductivity type is p-type and the second conductivity type is n-type.

[0004] The semiconductor wafer, for example, has a main extension plane. A vertical direction extends perpendicular to the main extension plane, while a lateral direction extends parallel to the main extension plane. The first semiconductor layer sequence and the second semiconductor layer sequence are stacked, for example, one above the other in the vertical direction. The semiconductor wafer has a significantly greater extent in the vertical direction than in the lateral direction.

[0005] At least one active region is arranged between the first semiconductor layer sequence and the second semiconductor layer sequence. The active region is designed to generate electromagnetic radiation during operation. The active region, for example, directly adjoins the first semiconductor layer sequence and the second semiconductor layer sequence. The active region, for example, has a pn junction, a heterostructure, a single quantum system structure, and / or a multiple quantum system structure.

[0006] The electromagnetic radiation generated during operation of the active region is, for example, near-ultraviolet radiation, visible light and / or near-infrared radiation. Visible light is, for example, blue, green, yellow or red light.

[0007] For example, the semiconductor wafer is epitaxially grown onto the growth substrate. The semiconductor wafer is preferably based on a III-V compound semiconductor material. The III-V compound semiconductor material is, for example, a phosphide, arsenide and / or nitride compound semiconductor material, i.e., for example, In x Al y Ga 1-x-y P、In x Al y Ga 1-x-y As and / or Inx Al y Ga 1-x-y N, where 0≤x≤1, 0≤y≤1, and x+y≤1.

[0008] The semiconductor wafer may contain dopants and additional components. For the sake of simplicity, however, only the main components of the crystal lattice of the semiconductor wafer, namely Al, Ga, In, N, As or P, are described, even if these main components can be partially replaced and / or supplemented by small amounts of other substances.

[0009] According to at least one embodiment of the method, a first contact layer is applied to the semiconductor wafer. The first contact layer is, for example, arranged in a matrix, i.e., along rows and columns. This means that the first contact layer can be arranged at lattice points of a regular lattice. The first contact layer is, for example, in direct contact with the semiconductor wafer, in particular the first semiconductor layer sequence.

[0010] For example, the first contact layer includes a transparent conductive metal or a transparent conductive oxide (TCO). TCO is a transparent conductive material and includes, for example, zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, and / or indium tin oxide (ITO).

[0011] Alternatively, it is possible that the first contact layer comprises, for example, a reflective, electrically conductive metal, in which case the first contact layer comprises or consists of, for example, one or more of the following materials: Au, Ag, Al, Al:Cu, Rh, Pd, Pt.

[0012] Ideally, the first contact layer has a reflectivity of at least 80%, in particular at least 90%, for the emitted electromagnetic radiation.

[0013] According to at least one embodiment of the method, the carrier device is fixed to the semiconductor wafer. For example, the carrier device includes a second carrier layer and a third carrier layer. The second carrier layer is arranged on the semiconductor wafer and, for example, completely covers the semiconductor wafer.

[0014] The second carrier layer may in particular comprise an adhesion promoter material or be formed by an adhesion promoter material. The adhesion promoter material may be heated, for example, by means of a laser. As a result, components applied to the adhesion promoter material, in particular radiation-emitting semiconductor chips, can advantageously be detached without damage by means of laser radiation.

[0015] The second carrier layer can be formed of a material that is at least temporarily flowable. In this case, the temporarily flowable material comprises, for example, a metal solder or a benzocyclobutene bonded polymer.

[0016] Furthermore, a third carrier layer is arranged on the second carrier layer. The third carrier layer is in direct contact with the second carrier layer, for example. The third carrier layer is in particular an auxiliary carrier element, which can form a mechanically stable component of the carrier device.

[0017] According to at least one embodiment of the method, the semiconductor wafer is singulated into semiconductor bodies. The semiconductor wafer is singulated into semiconductor bodies, for example, by cutting through the semiconductor wafer in a vertical direction. The cuts, in particular, completely penetrate the semiconductor wafer. The cuts are produced, for example, by a laser process, a sawing process, or an etching process.

[0018] According to at least one embodiment of the method, a second contact layer is applied to the semiconductor body. The second contact layer is, for example, in direct contact with the semiconductor body, in particular the second semiconductor layer sequence.

[0019] For example, the second contact layer comprises a transparent conductive metal or a transparent conductive oxide (TCO).

[0020] Alternatively, the second contact layer can comprise, for example, a reflective, conductive metal. In this case, the second contact layer can comprise or consist of, for example, one or more of the following materials: Au, Ag, Al, Al:Cu, Rh, Pd, Pt. Ideally, the second contact layer has a reflectivity of at least 80%, in particular at least 90%, for the emitted electromagnetic radiation.

[0021] It is possible that the first contact layer comprises the same material as the second contact layer. This means that the first contact layer and the second contact layer are formed, for example, from the same TCO material, such as ITO. It is also possible that the first contact layer and the second contact layer are formed, for example, from a reflective conductive metal.

[0022] Alternatively, it is possible for the first contact layer to comprise a different material than the second contact layer. In this case, the first contact layer can be formed from a reflective, conductive metal and the second contact layer can be formed from a TCO. Furthermore, it is possible for the second contact layer to be formed from a reflective, conductive metal and the first contact layer from a TCO.

[0023] According to at least one embodiment, the outer surface of the first contact layer facing the semiconductor body and / or the outer surface of the second contact layer facing the semiconductor body is, in particular, completely covered by a further reflective, electrically conductive metal. The further reflective, electrically conductive metal may, for example, include or consist of one or more of the following materials: Au, Ag, Al, Al:Cu, Rh, Pd, Pt. The further reflective, electrically conductive metal ideally has a reflectivity of at least 80%, in particular at least 90%, for the emitted electromagnetic radiation.

[0024] For example, it is possible to form the first and second contact layers from the same TCO material, such as ITO, in which case the outer surface of the first contact layer facing the semiconductor body and / or the outer surface of the second contact layer facing the semiconductor body is completely covered by another reflective, electrically conductive metal.

[0025] If the first contact layer and the second contact layer comprise a metal, for example, it is further possible to cover the outer surface of the first contact layer and the outer surface of the second contact layer facing the semiconductor body with a further reflective, electrically conductive metal.

[0026] In at least one embodiment, a method for producing a radiation-emitting semiconductor chip comprises the following steps:

[0027] - Provide semiconductor wafers,

[0028] - applying a first contact layer to the semiconductor wafer,

[0029] - fixing the carrier device on the semiconductor wafer,

[0030] - dividing the semiconductor wafer into semiconductor bodies, and

[0031] - applying a second contact layer to the semiconductor body.

[0032] According to at least one embodiment of the method, after applying the first contact layer, a sacrificial layer is formed on the semiconductor wafer, which is designed to be simply connected. In this embodiment, the sacrificial layer does not have any openings. Preferably, the bottom surface and the top surface of the sacrificial layer are unstructured, in particular, flat.

[0033] According to at least one embodiment of the method, the carrier device comprises a second carrier layer and a third carrier layer. In this embodiment, the second carrier layer and the third carrier layer each have a bottom surface and a top surface, which are flat.

[0034] According to at least one embodiment of the method, a second carrier layer is applied to the sacrificial layer. In this embodiment, the second carrier layer promotes a mechanically stable connection between the sacrificial layer and the third carrier layer.

[0035] According to at least one embodiment of the method, after applying the first contact layer, a sacrificial layer is produced on the semiconductor wafer, the sacrificial layer being penetrated by the opening. For example, the sacrificial layer is applied on the first semiconductor layer sequence.

[0036] The sacrificial layer is produced, for example, by sputtering or vapor deposition, comprises, for example, a semiconductor material such as silicon, and has a thickness of, for example, at least 50 nm and at most 5 μm.

[0037] For example, the opening is produced in the sacrificial layer after the sacrificial layer has been applied. The opening passes completely through the sacrificial layer. The material removal for producing the opening in the sacrificial layer can be produced by an etching process.

[0038] According to at least one embodiment of the method, a carrier device is fixed to the sacrificial layer. The carrier device has a retaining element, by means of which the carrier device is mechanically fixedly connected to the semiconductor chip to be produced. The retaining element of the carrier device is formed in an opening in the sacrificial layer. The carrier device can include multiple layers and / or be produced in multiple method steps. For example, the carrier device has a first carrier layer, a second carrier layer, and a third carrier layer.

[0039] The first carrier layer is applied, for example, over the sacrificial layer. The first carrier layer completely covers the sacrificial layer, for example. Furthermore, the first carrier layer is also disposed within the openings. Each opening can be completely covered with the material of the first carrier layer. The material of the first carrier layer in the openings forms a retaining element. The first carrier layer, for example, includes or is formed from silicon dioxide or aluminum oxide. Furthermore, the first carrier layer has, for example, a thickness of at least 50 nm and at most 500 nm.

[0040] Subsequently, for example, a second carrier layer is applied onto the first carrier layer. The second carrier layer is in direct contact with the first carrier layer, for example. The second carrier layer particularly includes an adhesion promoter material or is formed by an adhesion promoter material. The adhesion promoter material is formed, for example, by benzocyclobutene or metal solder.

[0041] The retaining element is formed by the portion of the carrier layer arranged in the opening. For example, the first carrier layer and the second carrier layer are arranged in the opening. In the case described, the retaining element is formed by the material of the first carrier layer and the second carrier layer.

[0042] Subsequently, for example, a third carrier layer is arranged on top of the second carrier layer. The third carrier layer is in direct contact with the second carrier layer, for example. The third carrier layer is particularly an auxiliary carrier. The second carrier layer promotes a mechanically stable connection between the first and third carrier layers.

[0043] According to at least one embodiment of the method, the sacrificial layer is removed so that the carrier device is mechanically connected to the semiconductor body only in the region of the holding element. For example, the sacrificial layer is completely removed. The sacrificial layer is removed, for example, by a chemical etching process.

[0044] In at least one further embodiment, the method for producing a radiation-emitting semiconductor chip comprises the following steps:

[0045] - Provide semiconductor wafers,

[0046] - applying a first contact layer to the semiconductor wafer,

[0047] - producing a sacrificial layer on the semiconductor wafer, said sacrificial layer being pierced by an opening,

[0048] - fixing the carrier device to the sacrificial layer, wherein a retaining element of the carrier device is respectively produced in an opening in the sacrificial layer,

[0049] - dividing the semiconductor wafer into semiconductor bodies,

[0050] - applying a second contact layer to the semiconductor body, and

[0051] The sacrificial layer is removed, so that the carrier device is mechanically connected to the semiconductor body only in the region of the holding element.

[0052] It is feasible that the listed steps are performed in the order described.

[0053] The method described herein for producing radiation-emitting semiconductor chips further includes the use of a carrier device, wherein the semiconductor body is mechanically connected to the carrier device only in the region of a holding element. The holding element is connected to the semiconductor chip in such a way that the semiconductor chip can be separated from the holding element without damage. Advantageously, the produced semiconductor chip can be pressed particularly efficiently onto the terminal arrangement using the carrier device.

[0054] According to at least one embodiment of the method, a first dielectric layer is applied to the semiconductor wafer. The first dielectric layer may completely cover the semiconductor wafer. Furthermore, the first dielectric layer may be in direct contact with the semiconductor wafer. In particular, the dielectric layer is in direct contact with the first semiconductor layer sequence.

[0055] The first dielectric layer comprises, for example, at least two first dielectric sublayers. The sublayer facing the semiconductor wafer comprises, for example, silicon dioxide or is formed thereof. The sublayer facing away from the semiconductor wafer comprises, for example, aluminum oxide or is formed thereof.

[0056] According to at least one embodiment of the method, a first recess is created in the first dielectric layer. The first recess may completely penetrate the first dielectric layer. The first recess, for example, partially exposes the semiconductor wafer. In particular, the first recess partially exposes the first semiconductor layer sequence. Material removal from the first dielectric layer is performed, in particular, by an etching process.

[0057] According to at least one embodiment of the method, a first contact layer is disposed in each of the first recesses. In the region of the first recess, the first contact layer is in direct contact with the semiconductor wafer. The first contact layer, for example, does not extend vertically beyond the first dielectric layer. It is possible that the top surface of the first contact layer is flush with the top surface of the first dielectric layer. Furthermore, the first contact layer can completely fill the first recess.

[0058] According to at least one embodiment of the method, a second dielectric layer is applied over the first dielectric layer and the first contact layer. The second dielectric layer is, for example, in direct contact with the first dielectric layer and the first contact layer. The second dielectric layer comprises, for example, or consists of a dielectric material such as silicon dioxide or silicon nitride. Furthermore, it is possible for the second dielectric layer to be a Bragg mirror. The Bragg mirror preferably comprises alternating layers of a high-refractive-index material and a low-refractive-index material. The layers of the Bragg mirror preferably comprise SiO2, Al2O3, TiO2, tantalum oxide, Nb2O5, MgF, silicon nitride, and / or silicon oxynitride.

[0059] Furthermore, the second dielectric layer has a thickness of, for example, at least 500 nm and at most 30 μm, in particular approximately 1 μm.

[0060] In this embodiment, the second dielectric layer is formed in such a way that the second dielectric layer itself is mechanically stable.

[0061] According to at least one embodiment of the method, a passivation layer is applied to the semiconductor bodies after singulation of the semiconductor wafer. The passivation layer completely covers, for example, the outer surface of the semiconductor bodies facing away from the carrier. Furthermore, the passivation layer may cover the bottom surface of the first dielectric layer facing away from the carrier.

[0062] The passivation layer comprises, for example, silicon dioxide or is formed thereof. Advantageously, such a passivation layer can be used to particularly effectively protect the semiconductor body from external environmental influences.

[0063] Furthermore, it is possible for the passivation layer to be a Bragg mirror, thereby advantageously allowing electromagnetic radiation emitted by the semiconductor body to be deflected in a predetermined direction, thereby advantageously increasing the efficiency of the radiation-emitting semiconductor chip.

[0064] According to at least one embodiment of the method, a second recess is generated in the passivation layer, which is spaced apart from the semiconductor body in a lateral direction. The second recess, for example, passes completely through the passivation layer. If the second recess only passes through the passivation layer, the second recess laterally overlaps with one of the first recesses.

[0065] Furthermore, it is possible that the second recess completely passes through the passivation layer and the first dielectric layer. If the second recess passes through the first dielectric layer and the passivation layer, the second recess is spaced apart from the first recess in the radial direction.

[0066] According to at least one embodiment of the method, a third recess is generated in the passivation layer, each of which overlaps one of the semiconductor bodies in a lateral direction. The third recess, for example, passes completely through the passivation layer. Furthermore, the third recess each overlaps one of the first recesses in a lateral direction.

[0067] According to at least one embodiment of the method, the third recesses partially expose one of the semiconductor bodies, for example, the second semiconductor layer of each semiconductor body is partially exposed.

[0068] According to at least one embodiment of the method, a second contact layer is applied to each of the exposed semiconductor bodies. In the region of the third recess, the second contact layer is in direct contact with the semiconductor body. The second contact layer may extend vertically beyond the passivation layer. Furthermore, it is possible for the second contact layer to extend laterally beyond the third recess and to be disposed partially on the passivation layer. This means, for example, that the second contact layer is disposed partially on the bottom surface of the passivation layer facing away from the semiconductor body.

[0069] According to at least one embodiment of the method, an additional first contact layer is applied to the side of the passivation layer. Furthermore, the additional first contact layer can be disposed on the bottom surface of the passivation layer. For example, the additional first contact layer comprises the same material as the first contact layer. Alternatively, it is possible to form the additional first contact layer using a material different from that of the first contact layer. This means that the additional first contact layer can include a transparent conductive material, a transparent conductive oxide, or a reflective conductive metal.

[0070] If the semiconductor body is electrically conductively connected via the first contact layer, the further first contact layer, and the second contact layer, the further first contact layer and the second contact layer are advantageously arranged spaced apart from one another in a lateral direction on the bottom side of the passivation layer. In this case, the further first contact layer and the second contact layer can be electrically conductively connected from the side facing away from the carrier device. Furthermore, the further first contact layer and the second contact layer can advantageously be printed directly onto the terminal arrangement.

[0071] If the additional first contact layer comprises a TCO material, the additional first contact layer is formed as a web on the side surfaces of the passivation layer. In this case, the web has a width of up to 5 μm. For example, the width of the web is up to 50% of the extension of the radiation-emitting semiconductor chip in a lateral direction. In this case, the electromagnetic radiation is advantageously absorbed very little at the side surfaces of the passivation layer.

[0072] If the additional first contact layer comprises a reflective, electrically conductive metal, the additional first contact layer covers a majority of the side surfaces of the passivation layer. "Major" here means that the additional first contact layer covers at least 90%, in particular 95%, of the side surfaces of the passivation layer. Furthermore, the first contact layer can completely surround the passivation layer in a lateral direction. In this case, the second contact layer also comprises a reflective, electrically conductive metal, and the first contact layer comprises a TCO material. This advantageously results in particularly high light outcoupling efficiency from the radiation-emitting semiconductor chip.

[0073] Furthermore, it is possible to arrange a reflector between the semiconductor body and the passivation layer, thereby enabling particularly good light outcoupling and efficiency of the radiation-emitting semiconductor chip.

[0074] According to at least one embodiment of the method, the additional first contact layer is electrically conductively connected to one of the first contact layers in each of the second recesses. In this embodiment, the second recess and the first recess overlap in a lateral direction. The additional first contact layer and the first contact layer are in direct contact at the interface between the second recess and the first recess, for example.

[0075] According to at least one embodiment of the method, a fourth recess is generated in the second dielectric layer, each of which overlaps one of the first recesses in a lateral direction. The fourth recess, for example, completely penetrates the second dielectric layer. The fourth recess may partially expose the first contact layer.

[0076] According to at least one embodiment of the method, the first contact is disposed in each of the fourth recesses. The side surfaces of the fourth recess are formed, for example, by the bounding second dielectric layer, and the bottom surface of the fourth recess is formed, for example, by one of the bounding first contact layers. The first contact completely covers the side surfaces and bottom surface of the fourth recess.

[0077] For example, the first contact comprises a conductive metal. In this case, the first contact comprises, for example, one or more of the following materials or is formed from one or more of the following materials: Au, Ag, Al, Cu, Ni, Rh, Pd, Pt.

[0078] Alternatively, the first contact layer comprises a transparent conductive metal or a transparent conductive oxide.

[0079] According to at least one embodiment of the method, the first contact portion is in conductive contact with one of the first contact layers in each of the fourth recesses. For example, the first contact portion is in direct contact with the first contact layer partially exposed by the fourth recess.

[0080] According to at least one embodiment of the method, a fifth recess is created in the second dielectric layer, the fifth recess being laterally spaced apart from the first recess. The fifth recess, for example, completely penetrates the second dielectric layer. The fifth recess may partially expose the first dielectric layer. If the second recess penetrates the passivation layer and the first dielectric layer, the fifth recess laterally overlaps with one of the second recesses.

[0081] According to at least one embodiment of the method, a second contact is provided in each of the fifth recesses. The side surfaces of the fifth recess are formed, for example, by the bounding second dielectric layer, and the bottom surface of the fifth recess is formed, for example, by the bounding first dielectric layer. The second contact completely covers the side surfaces and bottom surface of the fifth recess.

[0082] For example, the second contact portion is formed of the same material as the first contact portion.

[0083] According to at least one embodiment of the method, an additional second contact is applied to a side surface of the passivation layer. The additional second contact layer, for example, comprises the same material as the second contact layer. Alternatively, it is possible to form the additional second contact layer from a material different from that of the second contact layer. The additional second contact layer can include a transparent conductive metal, a transparent conductive oxide, or a reflective conductive metal.

[0084] If the additional second contact layer comprises a TCO, the additional second contact layer is formed as a web on the side surfaces of the passivation layer. In this case, the web has a width of up to 5 μm. For example, the width of the web is up to 50% of the extension of the radiation-emitting semiconductor chip in a lateral direction. In this case, the electromagnetic radiation is advantageously absorbed very little at the side surfaces of the passivation layer.

[0085] If the additional second contact layer comprises a reflective, electrically conductive metal, then the additional second contact layer covers a majority of the lateral surfaces of the passivation layer. "Major" here means that the additional second contact layer covers at least 90%, in particular 95%, of the lateral surfaces of the passivation layer. Furthermore, the second contact layer can completely surround the passivation layer in a lateral direction. In this case, the first contact layer also comprises a reflective, electrically conductive metal, and the second contact layer comprises a TCO material.

[0086] According to at least one embodiment of the method, the second contact layer and the further second contact layer electrically conductively connect each of the second contacts to each of the exposed semiconductor bodies. The further second contact layer and the second contact are in direct contact at the interface between the second recess and the fifth recess, for example.

[0087] The connection between the second contact layer and the second contact can advantageously be established in a single manufacturing method. Furthermore, the use of an additional first and / or additional second contact layer makes it possible to dispense with a through-hole through the semiconductor body. This advantageously reduces non-radiative recombination (NRR), which occurs, for example, at the side walls of the through-hole.

[0088] In particular, the radiation-emitting semiconductor chip produced in this manner is a micro-LED, which can be produced particularly efficiently and transferred particularly well using the method proposed here. The micro-LED has, for example, an extension in a lateral direction of up to 100 μm, in particular up to 50 μm.

[0089] Furthermore, a radiation-emitting semiconductor chip is proposed, which can be produced in particular by means of the method described here. All features and embodiments disclosed in conjunction with the method are therefore also disclosed in conjunction with the radiation-emitting semiconductor chip, and vice versa.

[0090] According to at least one embodiment, a radiation-emitting semiconductor chip includes a semiconductor body designed to emit electromagnetic radiation. The semiconductor body preferably has a first semiconductor layer sequence and a second semiconductor layer sequence, between which an active region is arranged, which is designed to generate electromagnetic radiation during operation. The electromagnetic radiation is, for example, near-ultraviolet radiation, visible light, and / or near-infrared radiation. Visible light is, for example, blue, green, yellow, or red light.

[0091] In accordance with at least one embodiment, the radiation-emitting semiconductor chip comprises a first contact layer, which is in direct contact with the first semiconductor layer sequence, for example.

[0092] According to at least one embodiment of the method, the radiation-emitting semiconductor chip comprises a second contact layer, which is in direct contact with the second semiconductor layer sequence, for example.

[0093] According to at least one embodiment of the method, current can be injected into the semiconductor body via the first contact layer and the second contact layer. For example, charge carriers can be injected into the first semiconductor layer sequence via the first contact layer. Furthermore, charge carriers can be injected into the second semiconductor layer sequence via the second contact layer.

[0094] According to at least one embodiment, the radiation-emitting semiconductor chip comprises only components that are transmissive to the electromagnetic radiation emitted by the semiconductor body. For example, the transmissive components are transmissive to at least 80%, in particular at least 90%, of the electromagnetic radiation emitted by the semiconductor body.

[0095] If the radiation-emitting semiconductor chip comprises, for example, a metal layer, the metal layer may each have a thickness of at most 5 nm, in particular at most 0.5 nm. Furthermore, the metal layer covers at most 0.5% of the outer surface of the semiconductor body. In particular, the metal layer covers no more than 1 μm of the outer surface of the semiconductor body. 2 .

[0096] Such a radiation-emitting semiconductor chip can therefore be integrated particularly well into various housings. The light direction can be predetermined by the housing in this case. This means that such a radiation-emitting semiconductor chip can be used particularly flexibly. Furthermore, such a radiation-emitting semiconductor chip has a particularly simple chip structure.

[0097] According to at least one embodiment, the first contact layer and the second contact layer include a transparent conductive material, for example, a TCO material such as ITO.

[0098] The TCO comprises, for example, a highly doped oxide semiconductor that is transparent to the electromagnetic radiation emitted by the semiconductor body and electrically conductive. Consequently, the first and second contact layers do not include any metal layers. This allows the radiation-emitting semiconductor chip as a whole to be free of metal layers and components.

[0099] The metal layer absorbs a relatively high proportion of the electromagnetic radiation emitted by the semiconductor body. In contrast, the TCO has a relatively low absorption of the electromagnetic radiation emitted by the semiconductor body.

[0100] According to at least one embodiment, the first contact layer is arranged on the bottom surface of the semiconductor body. For example, the bottom surface of the semiconductor body is formed by the bottom surface of the second semiconductor layer sequence. Furthermore, the second contact layer may also be arranged on the bottom surface of the semiconductor body, in particular on the bottom surface of the second semiconductor layer sequence.

[0101] According to at least one embodiment, the first contact layer extends from a bottom side of the semiconductor body into the semiconductor body. For example, the semiconductor body has a through-hole extending from the second semiconductor layer sequence into the first semiconductor layer sequence. The first contact layer is in direct contact with the first semiconductor layer sequence in the region of the through-hole.

[0102] Furthermore, a radiation-emitting component is provided, which includes the radiation-emitting semiconductor chip described herein. All features and embodiments disclosed in conjunction with the radiation-emitting semiconductor chip are therefore also disclosed in conjunction with the radiation-emitting component, and vice versa.

[0103] According to at least one embodiment, a radiation-emitting component includes a carrier having at least one first contact element. For example, the first contact element comprises an electrically conductive metal. In this case, the first contact element may include or be formed from one or more of the following materials: Au, Ag, Al, Cu, Ni, Rh, Pd, or Pt.

[0104] Alternatively, the first contact element comprises a transparent conductive metal or a transparent conductive oxide.

[0105] According to at least one embodiment, the radiation-emitting semiconductor chip is mounted on a carrier by means of a direct bond and / or an adhesive. The direct bond, for example, does not include solder metal. During a direct bond, the semiconductor chip and the carrier are mechanically and stably connected, for example, by atomic and / or molecular forces. These atomic and / or molecular forces are, for example, hydrogen bonds and / or van der Waals interactions. Direct bonding typically occurs between two planar interface surfaces solely under the influence of pressure and / or temperature. Consequently, solder metal is not required for the direct bond. Advantageously, absorption losses can thus be avoided.

[0106] The adhesive, for example, includes a matrix material. The matrix material can be, for example, a resin such as an epoxy, or a silicone, or a mixture of these materials. Furthermore, conductive particles can be incorporated into the matrix material. The conductive particles impart, for example, conductive properties to the adhesive. Alternatively, the adhesive can be an electrically insulating adhesive. Alternatively, the adhesive can be spin-on glass.

[0107] If the radiation-emitting semiconductor chip is mounted on a carrier by means of a direct bond connection, an intermediate space may be formed between the semiconductor chip and the carrier. In this case, the adhesive is at least partially or completely disposed in the intermediate space. Advantageously, this provides the radiation-emitting component with a particularly stable design.

[0108] Furthermore, it is possible that the adhesive can be used only for positioning the radiation-emitting semiconductor chip on the carrier. After the semiconductor chip has been positioned and fixed on the carrier, the adhesive can in this case be ashed.

[0109] In accordance with at least one embodiment, the carrier and / or the first contact element are embodied so as to be transparent to the electromagnetic radiation emitted by the semiconductor body.

[0110] In accordance with at least one embodiment, the first contact element is reflective with respect to radiation emitted by the semiconductor body.

[0111] According to at least one embodiment, the first contact element has a curved shape. For example, the first contact element has a concave shape. The first contact element can thus have a cavity in which the radiation-emitting semiconductor chip is disposed. For example, the radiation-emitting semiconductor chip is completely disposed in the cavity. Furthermore, the radiation-emitting semiconductor chip can be completely surrounded in a lateral direction by the first contact element. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] A method for producing a radiation-emitting semiconductor chip, a radiation-emitting semiconductor chip, and a radiation-emitting component are explained in more detail below with reference to exemplary embodiments and the associated figures.

[0113] The accompanying drawings show:

[0114] Figure 1 、2 , 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 show schematic sectional illustrations of method stages during the production of a radiation-emitting semiconductor chip in accordance with one embodiment.

[0115] Figure 17 、 18 , 19, 20, 21, 22 and 23 show schematic sectional views of a radiation-emitting semiconductor chip having a carrier device according to one embodiment, in each case.

[0116] Figure 24 shows a schematic sectional illustration of a method stage during the production of a radiation-emitting semiconductor chip in accordance with one exemplary embodiment,

[0117] Figure 25 and 26 shows a schematic sectional view of a radiation-emitting semiconductor chip according to one embodiment, and

[0118] Figure 27 、 28 , 29 , 30 , 31 and 32 show schematic sectional views of a radiation-emitting component according to each of one exemplary embodiment.

[0119] Elements that are identical, of the same type, or perform the same function are provided with the same reference numerals in the drawings. The drawings and the size relationships of the elements shown in the drawings relative to one another should not be considered true to scale. Rather, individual elements may be shown exaggeratedly for better illustration and / or to provide a better understanding. DETAILED DESCRIPTION

[0120] according to Figure 1 In a method step for producing a radiation-emitting semiconductor chip 1, a semiconductor wafer 2 is first provided. The semiconductor wafer 2 comprises a first semiconductor layer sequence 3 and a second semiconductor layer sequence 4. The semiconductor wafer 2 is then epitaxially grown onto a growth substrate 16. In this exemplary embodiment, the first semiconductor layer sequence 3 is p-doped and the second semiconductor layer sequence 4 is n-doped.

[0121] A first dielectric layer 17 is applied to the semiconductor wafer 2, in particular to the first semiconductor layer sequence 3. The first dielectric layer 17 is in direct contact with the semiconductor wafer 2. The first dielectric layer 17 comprises two first dielectric layers 17. In this case, the first dielectric layer 17 facing the semiconductor wafer 2 comprises silicon dioxide and has a thickness of up to 50 nm. The first dielectric layer 17 facing away from the semiconductor wafer 2 comprises aluminum oxide and likewise has a thickness of up to 50 nm.

[0122] according to Figure 2In a further method step, a first recess 18 is produced in the first dielectric layer 17. The first recess 18 passes completely through the first dielectric layer 17 and exposes the semiconductor wafer 2, in particular the first semiconductor layer sequence 3, in places.

[0123] Next, a first contact layer 5 is applied to the semiconductor wafer 2, in particular to the first semiconductor layer sequence 3. In this exemplary embodiment, the first contact layer 5 is disposed in each of the first recesses 18. The first contact layer 5 is in direct contact with the semiconductor wafer 2 in the region of the first recess 18. In this exemplary embodiment, the first contact layer 5 comprises a TCO, such as, for example, ITO. The thickness of the first contact layer 5 is, in this case, a maximum of 50 nm. Consequently, the thickness of the first contact layer 5 is less than the thickness of the first dielectric layer 17.

[0124] In this exemplary embodiment, the first contact layer 5 covers a majority of the surface area of the first semiconductor layer sequence 3. In this case, “majority” means that the first contact layer 5 covers at least 70% of the surface area of the first semiconductor layer sequence 3.

[0125] In such a Figure 3 In the method step shown in , a second dielectric layer 20 is applied over the first dielectric layer 17 and the first contact layer 5. The second dielectric layer 20 is in direct contact with the first dielectric layer 17 and the first contact layer 5. In this exemplary embodiment, the second dielectric layer 20 comprises silicon dioxide and has a thickness of approximately 1 μm.

[0126] In accordance with Figure 4 In a further method step, fourth recesses 26 are produced in the second dielectric layer 20, each of which overlaps laterally with one of the first recesses 18. Furthermore, fifth recesses 28 are produced in the second dielectric layer 20, which are spaced apart laterally from the first recesses 18. The fourth and fifth recesses 26, 28 pass completely through the second dielectric layer 20. The fourth recess 26 partially exposes the first contact layer 5, and the fifth recess 28 partially exposes the first dielectric layer 17.

[0127] Furthermore, first dividing trenches 39 are created in the second dielectric layer 20, which are spaced apart from the first recesses 18 in the lateral direction. The first dividing trenches 39 are each arranged between one of the fourth recesses 26 and one of the fifth recesses 28. The first dividing trenches 39 completely penetrate the second dielectric layer 20. Furthermore, the first dividing trenches 39 partially expose the first dielectric layer.

[0128] As in Figure 5As shown in FIG, a first contact portion 27 is provided in each of the fourth recesses 26. The first contact portion 27 completely covers the surface bounding the fourth recess 26. Furthermore, a second contact portion 29 is provided in each of the fifth recesses 28. The second contact portion 29 completely covers the surface bounding the fifth recess 28. Both the first contact portion 27 and the second contact portion 28 comprise a conductive metal. Furthermore, the first contact portion 27 makes conductive contact with one of the first contact layers 5 in each of the fourth recesses 26.

[0129] In accordance with Figure 6 In a method step, a sacrificial layer 6 is applied to the semiconductor body 2 , in particular the first semiconductor layer sequence 3 . In this exemplary embodiment, the sacrificial layer 6 comprises silicon.

[0130] according to Figure 7 , an opening 7 is produced in the sacrificial layer 6 , which completely passes through the sacrificial layer 6 and exposes the second dielectric layer 20 in places.

[0131] Bonding on sacrificial layer 6 Figure 8 、 9 and 10 fix the carrier device 8 to the sacrificial layer 6 .

[0132] As in Figure 8 As shown in , a first carrier layer 10 is applied over the sacrificial layer 6. The first carrier layer 10 completely covers the sacrificial layer 6 and is also arranged in the opening 7. In this exemplary embodiment, the first carrier layer comprises aluminum oxide and has a thickness of at least 50 nm and at most 500 nm.

[0133] Then, as in Figure 9 As shown in FIG, a second carrier layer 11 is applied over the first carrier layer 10. The second carrier layer 11 fills the opening 7 and extends vertically beyond the opening 7. In this exemplary embodiment, the second carrier layer comprises an adhesion promoter material such as, for example, benzocyclobutene.

[0134] In subsequent method steps, such as Figure 10 As shown in FIG, a third carrier layer 12 is arranged on the second carrier layer 11. The third carrier layer 12 is an auxiliary carrier in this embodiment.

[0135] Furthermore, a retaining element 9 is defined by the carrier device 8, said retaining element being arranged in the opening 7. In this embodiment, a first carrier layer 10 and a second carrier layer 11 are arranged in the opening and form the retaining element 9.

[0136] In accordance with Figure 11 In the method step, the growth substrate 16 is detached from the semiconductor layer sequence.

[0137] Figure 12A further method step is shown in which the semiconductor wafer 2 is singulated into semiconductor bodies 13. The semiconductor wafer 2 is singulated into semiconductor bodies 13, for example, by cutting in a vertical direction through the semiconductor wafer 2. In this exemplary embodiment, the cutting passes completely through the semiconductor wafer 2.

[0138] according to Figure 13 In this method step, a passivation layer 21 is applied onto the semiconductor body 13. The passivation layer 21 completely covers the outer surface of the semiconductor body 13 facing away from the carrier 8. Furthermore, the passivation layer 21 completely covers the bottom side of the first dielectric layer 17 facing away from the carrier 8. In this exemplary embodiment, the passivation layer comprises silicon dioxide.

[0139] If combined Figure 14 As shown, in a further method step, a second recess 22 is produced in the passivation layer 21, which is spaced apart in a lateral direction from the semiconductor body 13. In this exemplary embodiment, the second recess 22 also completely penetrates the first dielectric layer 17. The second recess 22 exposes the region of the second contact 29.

[0140] Furthermore, third recesses 23 are produced in the passivation layer 21, which each overlap laterally with one of the semiconductor bodies 13. The third recesses 23 extend completely through the passivation layer 21, for example. The third recesses 23 each partially expose one of the semiconductor bodies 13, in particular the second semiconductor layer sequence 4.

[0141] Furthermore, second dividing trenches 40 are generated in the first dielectric layer 17, each of which overlaps laterally with one of the first dividing trenches 39. The second dividing trenches 40 completely penetrate the first dielectric layer 17. Furthermore, the second dividing trenches 40 partially expose the sacrificial layer 6.

[0142] Figure 15 A further method step is shown, in which a second contact layer 14 is applied to the semiconductor body 13 exposed by the third recess 23. The second contact layer 14 is in direct contact with the semiconductor body 13, in particular the second semiconductor layer sequence 4. The second contact layer 14 completely fills the third recess 23 and vertically projects beyond the passivation layer 21. Furthermore, the second contact layer 14 projects beyond the third recess 23 in a lateral direction and is arranged in places on the passivation layer 21.

[0143] Furthermore, a further second contact layer 30 is applied to the side surfaces of the passivation layer 21. The further second contact layer 30 completely fills the second recess 22. The second contact layer 14 and the further second contact layer 30 electrically conductively connect each of the second contacts 29 to each of the exposed semiconductor bodies 13, in particular the second semiconductor layer sequence 4.

[0144] In this exemplary embodiment, the second contact layer 14 and the further second contact layer 30 comprise a TCO, such as, for example, ITO. The further second contact layer 30 on the side of the passivation layer 21 a has a thickness of at least 50 nm and at most 20 nm. Furthermore, in this exemplary embodiment, the further second contact layer 30 on the side of the passivation layer 21 a is formed as a web having a width of at most 5 μm.

[0145] In accordance with Figure 16 In a further step, the sacrificial layer 6 is removed, ie the carrier device 8 is mechanically connected to the semiconductor body 13 only in the region of the holding element 9. In this exemplary embodiment, the sacrificial layer 6 is removed by a chemical etching process.

[0146] The radiation-emitting semiconductor chip 1 is thus mechanically connected to the carrier device 8 solely via the holding element 9. Advantageously, the produced semiconductor chip 1 can thus be printed onto a terminal assembly by means of the carrier device 8.

[0147] according to Figure 17 The radiation-emitting semiconductor chip 1 of the exemplary embodiment is Figure 16 The embodiment of the invention has a first contact layer 5 which comprises a reflective conductive metal. In addition, the further second contact layer 30 is a reflective conductive metal. In this embodiment, the further second contact layer 30 covers a large part of the side surfaces of the passivation layer 21a.

[0148] In this exemplary embodiment, the first contact layer 5 and the further second contact layer 30 are reflective with respect to the electromagnetic radiation generated in the semiconductor body 13 .

[0149] In this embodiment, the second contact layer 14 covers a majority of the bottom surface of the second semiconductor layer sequence 4. In this case, "majority" means that the second contact layer 14 covers at least 90% of the bottom surface of the second semiconductor layer sequence 4. Radiation generated in the semiconductor body 13 can be coupled out via such a second contact layer 14.

[0150] according to Figure 18 The radiation-emitting semiconductor chip 1 of the exemplary embodiment is Figure 17 The exemplary embodiment of the present invention comprises, in contrast, a further reflector 38 which partially covers the side surfaces of the semiconductor body 13, in particular the side surfaces of the first semiconductor layer sequence 3. The further reflector 38 is formed, for example, from the same material as the first contact layer 5. As a result, the further reflector 38 in this exemplary embodiment is reflective for the electromagnetic radiation generated in the semiconductor body 13.

[0151] Advantageously, the reflective first contact layer 5 , the further second contact layer and the further mirror 38 each completely surround the semiconductor body 13 , with the exception of the transparent second contact layer 14 .

[0152] In accordance with Figure 19 In the radiation-emitting semiconductor chip 1 of the exemplary embodiment, the first contact 27 and the second contact 29 are connected to Figure 16 The embodiments are variously formed from TCO.

[0153] and Figure 16 、 17 , 18 and 19 are different, according to Figure 20 The radiation-emitting semiconductor chip 1 of the exemplary embodiment does not comprise a first contact 27 and does not comprise a second contact 29 . Consequently, neither the fourth recess 26 nor the fifth recess 28 is provided in the second dielectric layer 20 .

[0154] In this exemplary embodiment, the second semiconductor layer sequence 4 can be electrically conductively contacted in the region of the individual semiconductor bodies 13 only via the second contact layer 14 . Consequently, the semiconductor chip 1 does not have a further second contact layer 30 in this case.

[0155] Furthermore, a further first contact layer 25 is arranged on the side surfaces of the passivation layer 21 a. Furthermore, a further first contact layer is arranged on the bottom surface of the passivation layer 21 .

[0156] The further first contact layers 25 are each electrically conductively connected to one of the first contact layers 5 in each of the second recesses 22 .

[0157] The further first contact layer 25 comprises the same material as the first contact layer 5, such as TCO in this embodiment. The further first contact layer 25 is formed as a web on the side of the passivation layer 21a. The web has a width of at most 5 μm in this case.

[0158] In accordance with Figure 21 In the radiation-emitting semiconductor chip 1 of the exemplary embodiment, the first contact layer 25 and the second contact layer 14 are further Figure 20 Embodiments of are variously formed from reflective conductive metal.

[0159] Furthermore, the mirror 31 is arranged between the semiconductor body 13 , in particular the second semiconductor layer sequence 4 , and the passivation layer 21 .

[0160] according to Figure 22 In the embodiment of the present invention, the second semiconductor layer sequence 4 of each semiconductor body 13 is respectively connected to the second contact portion 29 as in Figure 162. The semiconductor chip 1 is electrically conductively connected as in the exemplary embodiment of FIG. However, the semiconductor chip 1 does not have a first contact 27. A further second recess 24 is created in the passivation layer 21, which is spaced apart in a lateral direction from the semiconductor body 13 and the second recess 22. The further second recess 24 passes completely through the passivation layer 21. Further first contact layers 25, each provided on the side surfaces of the passivation layer 21, are electrically conductively connected to one of the first contact layers 5 in each of the further second recesses 24.

[0161] and Figure 22 According to the embodiment of Figure 23 The radiation-emitting semiconductor chip 1 of the exemplary embodiment comprises a first contact 27 .

[0162] In accordance with Figure 24 In the method stage of the embodiment of Figures 15 to 16 In the method stages of the exemplary embodiment of the present invention, the radiation-emitting semiconductor chip 1 is mechanically fixed to a carrier device 8. The carrier device 8 comprises a second carrier layer 11 and a third carrier layer 12. The second carrier layer 11 is in direct contact with the sacrificial layer 6. Furthermore, the second carrier layer 11 promotes a mechanically stable connection between the sacrificial layer 6 and the third carrier layer 12. The radiation-emitting semiconductor chip 1 can be detached from the carrier device 8 without damage by laser radiation.

[0163] according to Figure 25 The radiation-emitting semiconductor chip 1 of the exemplary embodiment includes a semiconductor body 13 designed to emit electromagnetic radiation. The semiconductor body 13 has a first semiconductor layer sequence 3 and a second semiconductor layer sequence 4. A first contact layer 5 is arranged on the first semiconductor layer sequence 3, and a second contact layer 14 is arranged on the second semiconductor layer sequence 4. Furthermore, the side surfaces of the semiconductor body 13 are completely covered by a passivation layer 21.

[0164] In this exemplary embodiment, the radiation-emitting semiconductor chip 1 comprises only components that are transmissive to the electromagnetic radiation emitted by the semiconductor body 13. The first contact layer 5 and the second contact layer 14 are formed from a transparent conductive material such as, for example, ITO. Furthermore, the passivation layer 21 is formed from silicon dioxide.

[0165] and Figure 25 According to the embodiment of Figure 26 The radiation-emitting semiconductor chip 1 of the exemplary embodiment does not comprise a passivation layer 21 .

[0166] according to Figure 27 The radiation emitting device 32 of the embodiment comprises a device according to Figure 25. The semiconductor chip 1 is applied to a carrier 33 having at least one first contact element 34. In this embodiment, the radiation-emitting semiconductor chip 1 is arranged on the first contact element 34 of the carrier 33 by means of a second contact layer 14 and by means of an adhesive 35. In this case, the adhesive 35 is an electrically conductive adhesive 35.

[0167] and Figure 27 According to the embodiment of Figure 28 The radiation-emitting semiconductor chip 1 of the exemplary embodiment is arranged with a first contact layer 5 on a first contact element 34 of a carrier 33 by means of an adhesive 35. In this case, the adhesive 35 is an electrically insulating adhesive 35.

[0168] and Figure 28 The embodiments are different, according to Figure 29 The radiation-emitting component 32 of the exemplary embodiment includes an encapsulation 37. The encapsulation 37 is, for example, transmissive to the radiation generated by the radiation-emitting semiconductor chip 1. The encapsulation 37 can be a resin, such as an epoxy, or a silicone resin, or a mixture of these materials. Furthermore, the first contact layer 5 also covers, in particular, the entire surface of the encapsulation 37.

[0169] The first contact element 34 is based on Figure 30 Examples and Figure 28 The embodiments of variously have a curved shape.

[0170] In this exemplary embodiment, the first contact element 34 comprises a cavity, in which the radiation-emitting semiconductor chip 1 is completely arranged. Furthermore, the radiation-emitting semiconductor chip 1 is completely surrounded in a lateral direction by the first contact element 34 .

[0171] The first contact layer 5 and the second contact layer 14 of the radiation-emitting component 32 are arranged according to Figure 31 In an exemplary embodiment, the first contact layer 5 is arranged on the bottom side of the semiconductor body 13, in particular the second semiconductor layer sequence 4. In this embodiment, the first contact layer 5 extends from the bottom side of the semiconductor body 13 into the semiconductor body 13 as far as the first semiconductor layer sequence 3. Furthermore, the first contact layer 5 is arranged on the first contact element 34 and the second contact layer 14 is arranged on the second contact element 36. In this exemplary embodiment, the first contact element 34 and the second contact element 36 include a reflective, electrically conductive metal.

[0172] and Figure 31 According to the embodiment of Figure 32 The first contact element 34 and the second contact element of the embodiment are formed of TCO.

[0173] This application claims priority from German patent application 10 2019 123 188.4, and the disclosure content of that is incorporated herein by reference.

[0174] The features and embodiments described in conjunction with the figures can be combined with one another according to further embodiments, even if not all combinations are described in detail. Furthermore, the embodiments described in conjunction with the figures can alternatively or additionally have further features according to the description in the general part.

[0175] The present invention is not restricted to the exemplary embodiments described herein. Rather, the present invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if the feature or combination itself is not specified in detail in the claims or exemplary embodiments.

[0176] List of reference numerals:

[0177] 1 Radiation-emitting semiconductor chip

[0178] 2 semiconductor chips

[0179] 3 First semiconductor layer sequence

[0180] 4 Second semiconductor layer sequence

[0181] 5 First contact layer

[0182] 6 Sacrificial layer

[0183] 7 Opening

[0184] 8 Carrying device

[0185] 9 Retaining element

[0186] 10 First bearing layer

[0187] 11 Second bearing layer

[0188] 12 The third bearing layer

[0189] 13 Semiconductor body

[0190] 13 a Bottom surface of the semiconductor body

[0191] 14 Second contact layer

[0192] 16 Growth substrate

[0193] 17 First dielectric layer

[0194] 18 First recess

[0195] 20 Second dielectric layer

[0196] 21 Passivation layer

[0197] 21a Side view of the passivation layer

[0198] 22 Second recess

[0199] 23 Third recess

[0200] 24 Another second recess

[0201] 25 Additional first contact layer

[0202] 26 Fourth recess

[0203] 27 First contact

[0204] 28 Fifth recess

[0205] 29 Second contact portion

[0206] 30 Additional second contact layer

[0207] 31 Reflector

[0208] 32 Radiation-emitting devices

[0209] 33 bearing parts

[0210] 34 First contact element

[0211] 35 viscose

[0212] 36 Second contact element

[0213] 37 Encapsulation

[0214] 38 Additional reflectors

[0215] 39 first dividing groove

[0216] 40 Second dividing groove

Claims

1. A method for producing a radiation-emitting semiconductor chip (1), comprising the following steps: - providing semiconductor wafers (2), - applying a first dielectric layer (17) on the semiconductor wafer (2), - creating a first recess (18) in the first dielectric layer (17), - applying a first contact layer (5) to the semiconductor wafer (2), - applying a second dielectric layer (20) over the first dielectric layer (17) and the first contact layer (5), - creating a fourth recess (26) in the second dielectric layer (20), - fixing a carrier device (8) to the semiconductor wafer (2), - dividing the semiconductor wafer (2) into semiconductor bodies (13), and - applying a second contact layer (14) to the semiconductor body (13), wherein - the second dielectric layer (20) is constructed such that it is mechanically stable, and - the fourth recess (26) overlaps with one of the first recesses (18) in the transverse direction, - arranging the first contact portion (27) in each of the fourth recesses (26), - the first contact portion (27) is in electrically conductive contact with one of the first contact layers (5) in each of the fourth recesses (26), - creating a fifth recess (28) in the second dielectric layer (20), said fifth recess being spaced apart from the first recess (18) in a lateral direction, - arranging the second contact portion (29) in each of the fifth recesses (28), and The fourth recess (26) partially exposes the first contact layer (5) and the fifth recess (28) partially exposes the first dielectric layer (17).

2. The method for producing a radiation-emitting semiconductor chip (1) according to claim 1, wherein - producing a sacrificial layer (6) on the semiconductor wafer, said sacrificial layer being of single-connected configuration, - the carrying device (8) comprises a second carrying layer (11) and a third carrying layer (12), and The second carrier layer (11) is applied on the sacrificial layer (6).

3. The method for producing a radiation-emitting semiconductor chip (1) according to claim 1, After applying the first contact layer (5) - producing a sacrificial layer (6) on the semiconductor wafer, said sacrificial layer being penetrated by an opening (7), - fixing the carrier device (8) to the sacrificial layer (6), wherein a retaining element (9) of the carrier device (8) is respectively produced in an opening (7) of the sacrificial layer (6), and The sacrificial layer (6) is removed, so that the carrier device (8) is mechanically connected to the semiconductor body (13) only in the region of the holding element (9).

4. The method according to any one of claims 1 to 3, In this case, a passivation layer (21) is applied to the semiconductor bodies (13) after the semiconductor wafer (2) has been singulated.

5. The method according to claim 4, wherein - producing a second recess (22) in the passivation layer (21), the second recess being spaced apart from the semiconductor body (13) in a lateral direction, - producing a third recess (23) in the passivation layer (21), said third recess each overlapping one of the semiconductor bodies (13) in a lateral direction, and The third recesses (23) each partially expose one of the semiconductor bodies (13).

6. The method according to claim 5, In this case, a second contact layer (14) is applied to each of the exposed semiconductor bodies (13).

7. The method according to claim 5, wherein - applying a further first contact layer (25) to the side surface (21a) of the passivation layer, and The further first contact layers (25) are each electrically conductively connected to one of the first contact layers (5) in each of the second recesses (22).

8. The method according to claim 1, wherein - applying a passivation layer (21) on the semiconductor bodies (13) after singulation of the semiconductor wafer (2), - applying a further second contact layer (30) on the side surface (21a) of the passivation layer, and The second contact layer (14) and the further second contact layer (30) electrically conductively connect one of the second contacts (29) to one of the exposed semiconductor bodies (13).

9. A radiation-emitting semiconductor chip (1) comprising: - a semiconductor body (13) designed to emit electromagnetic radiation, - a first contact layer (5), - a second contact layer (14), - a first dielectric layer (17), said first dielectric layer having a first recess (18), and - a second dielectric layer (20), which is arranged above the first dielectric layer (17) and the first contact layer (5), wherein - the second dielectric layer (20) is designed such that it is mechanically stable, - current can be injected into the semiconductor body via the first contact layer (5) and the second contact layer (14), and - providing a fourth recess (26) in the second dielectric layer (20), said fourth recess overlapping in a lateral direction with one of the first recesses (18), - arranging the first contact portion (27) in each of the fourth recesses (26), - the first contact portion (27) is in electrically conductive contact with one of the first contact layers (5) in each of the fourth recesses (26), - creating a fifth recess (28) in the second dielectric layer (20), said fifth recess being spaced apart from the first recess (18) in a lateral direction, - arranging the second contact portion (29) in each of the fifth recesses (28), and The fourth recess (26) partially exposes the first contact layer (5) and the fifth recess (28) partially exposes the first dielectric layer (17).

10. The radiation-emitting semiconductor chip (1) as claimed in claim 9, The first contact layer (5) and the second contact layer (14) comprise transparent conductive materials.

11. The radiation-emitting semiconductor chip (1) as claimed in claim 9 or 10, wherein - the first contact layer (5) is arranged on the bottom surface (13a) of the semiconductor body, and The first contact layer (5) extends from the bottom surface (13a) of the semiconductor body into the semiconductor body (13).

12. A radiation emitting device (32) comprising: - a radiation-emitting semiconductor chip (1) according to any one of claims 9 to 11, - a carrier (33) having at least one first contact element (34), and The radiation-emitting semiconductor chip (1) is arranged on the carrier by means of a direct bonding connection and / or an adhesive (35).

13. The radiation-emitting component according to claim 12, The carrier (33) and / or the first contact element (34) are designed to be transparent to the electromagnetic radiation emitted by the semiconductor body (13).

14. The radiation-emitting component according to claim 12, The first contact element (34) is designed to be reflective for electromagnetic radiation emitted by the semiconductor body (13).

15. The radiation-emitting component according to claim 14, The first contact element (34) has a curved shape.

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