Configuration circuit with reset and configuration circuit of FPGA

Abstract

The present application relates to the field of semiconductor technology, and provides a configuration circuit with reset and a configuration circuit of FPGA, wherein the configuration circuit with reset includes: a plurality of storage units, each storage unit includes a first positive power supply node, a second positive power supply node, a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power supply node and the negative power supply terminal and has a first storage node, the second inverter is connected to the second positive power supply node and the negative power supply terminal and has a second storage node, and the second positive power supply node is connected to the positive power supply terminal; a reset unit, the input end is connected to the first signal output end, the output end is connected to the first positive power supply node of each storage unit, and is also connected to the positive power supply terminal and the negative power supply terminal; during the reset process, the signal of the first storage node is low level, and the signal of the second storage node is high level. The storage unit can be reset during the power-on process to shorten the reset time, and a fast reset function can also be realized during the reconfiguration process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a configuration circuit with reset and an FPGA. Background Art

[0002] In FPGA chips, configuration memory is a very important part. Since a large number of one-hot gates are used in the winding switches of FPGA chips, the configuration memory needs to keep the storage value at 0 at the initial power-on or reconfiguration to ensure that there is no signal conflict and output short-circuit current.

[0003] Figure 1 A circuit diagram of a configuration bit cell in a configuration memory is shown. Figure 2 Figure 1 shows the FPGA power-on configuration process. Figure 2 As shown in Figure 1, the FPGA will go through the chip power-on stage, the configuration memory reset process, and the chip will perform normal user mode operations. Among them, the chip power-on stage takes about several to tens of milliseconds, and the configuration memory reset process can be understood as Figure 1 It usually takes several tens of microseconds for the storage cell shown to maintain the storage value at 0.

[0004] Therefore, how to shorten the reset time of the storage unit has become a technical problem to be solved urgently. Summary of the invention

[0005] The present invention provides a configuration circuit with reset and a configuration circuit of FPGA, which can realize reset in the power-on process and the reconfiguration process, thereby shortening the reset time.

[0006] In a first aspect, the present invention provides a configuration circuit with reset, comprising:

[0007] At least one storage unit, each of the storage units includes a first positive power node, a second positive power node, and a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node and a negative power terminal and has a first storage node, the second inverter is connected to the second positive power node and the negative power terminal and has a second storage node, and the second positive power node is connected to the positive power terminal;

[0008] A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node of each storage unit, and the reset unit is also connected to the positive power supply end and the negative power supply end;

[0009] During the reset process, the signal at the first signal output terminal controls the signal at the output terminal of the reset unit to be low level, the signals at the first positive power node and the first storage node are both low level, and the signals at the second positive power node and the second storage node are both high level.

[0010] In a second aspect, the present invention provides a configuration circuit with reset, comprising:

[0011] At least one storage unit, each of the storage units includes a first positive power node, a second positive power node, and a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node and a negative power terminal and has a first storage node, the second inverter is connected to the second positive power node and the negative power terminal and has a second storage node;

[0012] A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node of each storage unit, and the reset unit is also connected to the positive power supply end and the negative power supply end;

[0013] A setting unit, wherein the input end of the setting unit is connected to the second signal output end, the output end is connected to the second positive power supply node of each of the storage units, and the setting unit is also connected to the positive power supply end and the negative power supply end;

[0014] During the reset process, the signal at the first signal output terminal controls the signal at the output terminal of the reset unit to be low level, and the signals at the first positive power node and the first storage node are both low level; the signal at the second signal output terminal controls the signal at the output terminal of the set unit to be high level, and the signals at the second positive power node and the second storage node are both high level.

[0015] In a third aspect, the present invention provides a configuration circuit of an FPGA, comprising: the configuration circuit described in the first aspect or the configuration circuit described in the second aspect.

[0016] The present invention provides a configuration circuit with reset and a configuration circuit of FPGA, the reset circuit includes a plurality of storage units, each storage unit includes a first positive power node, a second positive power node, a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node, the negative power terminal and has a first storage node, the second inverter is connected to the second positive power node, the negative power terminal and has a second storage node, the second positive power node is connected to the positive power terminal; a reset unit, the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power node of each storage unit, and the reset unit is also connected to the positive power terminal and the negative power terminal; during the reset process, the signal of the first signal output end controls the signal of the output end of the reset unit to be low level; the signals of the first positive power node and the first storage node are both low level; the signals of the second positive power node and the second storage node are both high level. In summary, through the technical solution of the present invention, the reset of the storage unit can be realized in the power-on process and the reconfiguration process to shorten the reset time.

[0017] The further effects of the above-mentioned non-conventional preferred manner will be described below in conjunction with specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the existing technical solutions, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A circuit diagram of a storage unit in the prior art provided by an embodiment of the present invention;

[0020] Figure 2 for Figure 1 A signal timing diagram for resetting a storage unit is provided;

[0021] Figure 3 A first reset circuit diagram provided by an embodiment of the present invention;

[0022] Figure 4 for Figure 3 A signal timing diagram of a first reset circuit is provided;

[0023] Figure 5 A second reset circuit diagram provided by an embodiment of the present invention;

[0024] Figure 6 A third reset circuit diagram provided by an embodiment of the present invention;

[0025] Figure 7A fourth reset circuit diagram provided by an embodiment of the present invention;

[0026] Figure 8 A fifth reset circuit diagram provided by an embodiment of the present invention;

[0027] Fig. 9 A sixth reset circuit diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] Semiconductor processing involves the formation of a wide variety of circuits. One type of circuit is a memory array. A memory array typically includes a plurality of memory cells arranged in a two-dimensional array. In a first direction of the two-dimensional array, the memory cells are connected along bit lines. In a second direction perpendicular to the first direction, the memory cells are connected along word lines. For the purposes of discussion, a string of memory cells along the first direction will be referred to as a column, and a string of memory cells along the second direction will be referred to as a row.

[0030] Conventionally, to access a specific memory cell in a memory array, a signal (e.g., voltage or current) is applied to the bit line and word line connected to the memory cell. Accessing a specific cell may involve reading data stored in the memory cell or writing data to the memory cell. Each memory cell can store a digital "1" or a digital "0" based on the signal of the transistor in the memory cell; where "1" represents a high level and "0" represents a low level. The following description takes "0" representing a low level and "1" representing a high level as an example.

[0031] One type of memory array is a static random access memory (SRAM) array. In some memory cell designs, each memory cell utilizes two different bit lines, often referred to as a bit line (BL) and a complementary bit line bar (BLB). Both the bit line and the complementary bit line extend along the column of memory cells. Also extending in the same direction as the bit lines are power rails. The power rails include a negative power (Vss) line and a positive power (Vdd) line; wherein the negative power (Vss) line is connected to a negative power terminal, such as ground, and the positive power (Vdd) line is connected to a positive power terminal. In these designs, each memory cell has two bit lines, a positive power line, and a negative power line, and these line segments extend in the same direction and pass through each memory cell.

[0032] Please Figure 3 This embodiment provides a reset circuit, characterized by comprising:

[0033] At least one storage cell (configuration bitcell), each storage cell (configuration bitcell) includes a first positive power node VCl, a second positive power node VCr and a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node VCl and the negative power terminal VSS and has a first storage node cfg, the second inverter is connected to the second positive power node VCr and the negative power terminal and has a second storage node cfgb, and the second positive power node VCr is connected to the positive power terminal VC;

[0034] A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node VCl of each storage unit, and the reset unit is also connected to the positive power supply terminal VC and the negative power supply terminal VSS;

[0035] During the power-on process, the information at the first signal output end controls the signal at the output end of the reset unit to be low level; the signals at the first positive power node VCl and the first storage node cfg are both low level; the signals at the second positive power node VCr and the second storage node cfgb are both high level.

[0036] In this embodiment, the reset unit is used to implement the reset during the power-on process, thereby increasing the reset speed of the storage unit and further speeding up the reset reconfiguration of the storage unit.

[0037] In practical applications, during the power-on process, the signal at the positive power supply terminal VC is at a high level, the signal rst at the first signal output terminal is transmitted to the input terminal of the reset unit, and the signal at the output terminal of the reset unit is at a low level, so that the signals at the first positive power supply node VCl and the first storage node cfg are both at a low level; the signal at the positive power supply terminal VC is at a high level, so that the signals at the second positive power supply node VCr and the second storage node cfgb are both at a high level.

[0038] For the convenience of description, the first inverter is referred to as I1, the second inverter is referred to as Ir, and the first signal output terminal is referred to as the reset signal output terminal.

[0039] As a feasible implementation, the input of the first inverter I1 is connected to the second storage node cfgb, and the output is connected to the first storage node cfg; the input of the second inverter Ir is connected to the first storage node cfgb, and the output is connected to the second storage node called cfgb.

[0040] In one example, the first inverter I1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1, the control ends of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected to the second storage node cfgb, the source end of the first pull-up transistor PU1 is connected to the first positive power supply node of the storage unit; the source end of the first pull-down transistor PD1 is connected to the negative power supply end; the node connected between the drain end of the first pull-up transistor PU1 and the drain end of the first pull-down transistor PD1 serves as the first storage node cfg. Among them, the drain end can be understood as the drain electrode, and the source end can be understood as the source electrode, and the same applies hereinafter. The output end of the first inverter I1 is located on the line connecting the drain end of the first pull-up transistor PU1 and the drain end of the first pull-down transistor PD1, and the input end of the first inverter I1 is located on the line connecting the control end of the first pull-up transistor PU1 and the control end of the first pull-down transistor PD1.

[0041] In one example, the second inverter Ir includes a second pull-up transistor PU2 and a second pull-down transistor PD2, the control terminals of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected to the first storage node cfg, the source terminal of the second pull-up transistor PU2 is connected to the second positive power supply node of the storage unit; the source terminal of the second pull-down transistor PD2 is connected to the negative power supply terminal; the node connected to the drain terminal of the second pull-up transistor PU2 and the drain terminal of the second pull-down transistor PD2 is used as the first storage node cfg. The output terminal of the second inverter I2 is located on the line connected to the drain terminal of the second pull-up transistor PU2 and the drain terminal of the second pull-down transistor PD2, and the input terminal of the second inverter I2 is located on the line connected to the control terminal of the second pull-up transistor PU2 and the control terminal of the second pull-down transistor PD2.

[0042] By way of example, the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors; the first pull-down transistor PD1 and the second pull-down transistor PD2 are NMOS transistors.

[0043] In actual applications, during the power-on process, the signal at the positive power supply terminal VC is at a high level, the signal rst at the reset signal output terminal is transmitted to the input terminal of the reset unit, and the signal at the output terminal of the reset unit is at a low level, so that the signal at the first positive power supply node VCl is at a low level, and the signal at the first storage node cfg is at a low level; when the signal at the positive power supply terminal VC is at a high level, the signal at the second positive power supply node VCr is at a high level, and at the same time, the signal at the first storage node cfg connected to the input terminal of the second pull-up transistor PU2 is at a low level, so that the second pull-up transistor PU2 is turned on and the second pull-down transistor PD2 is turned off, therefore, the signal at the second storage node cfgb is at a high level, the first pull-down transistor PD1 is turned on, the first pull-up transistor PU1 is turned off, and the signal at the first storage node cfg is locked to a low level.

[0044] As a feasible implementation method, Figure 3 and Figure 5 As shown, the levels of the signals at the input and output ends of the reset unit are opposite, for example, if the level of the signal at the input end is high, the level of the signal at the output end is low. During the power-on process, the signal rst at the reset signal output end is high, and the signal rst at the reset signal output end is transmitted to the input end of the reset unit, and the signal at the output end of the reset unit is low.

[0045] In one example, the reset unit includes a transistor Mp1 and a transistor Mn1. The control terminals of the transistor Mp1 and the transistor Mn1 are both connected to the reset signal output terminal, the source terminal of the transistor Mp1 is connected to the positive power supply terminal VC, the drain terminal is connected to the drain terminal of the transistor Mn1 and the first positive power supply node VCl, and the source terminal of the transistor Mn1 is connected to the negative power supply terminal VSS. It should be understood that the output terminal of the reset unit is located on the line connecting the drain terminal of the transistor Mp1 and the drain terminal of the transistor Mn1.

[0046] By way of example, the transistor Mp1 is a PMOS transistor and the transistor Mn1 is an NMOS transistor.

[0047] During the power-on process, the signal rst at the reset signal output end is at a high level, and the signal rst at the reset signal output end is transmitted to the control ends of the transistor Mp1 and the transistor Mn1, then the transistor Mp1 is turned off, the transistor Mn1 is turned on, and the signal of the line connected to the drain end of the transistor Mp1 and the drain end of the transistor Mn1 is at a low level, that is, the signal at the output end of the reset circuit is at a low level.

[0048] Due to the introduction of the reset unit, the original symmetrical storage unit will become asymmetrical during reading and writing, which will lead to poor noise tolerance and poor reading and writing yield.

[0049] To optimize this problem, in an example, Figure 3 and Figure 5 As shown, the reset circuit also includes a transistor Mpc, the control end of the transistor Mpc is connected to the second signal output end, the source end and the drain end are respectively connected to the output end of the reset unit and the second positive power node VCr in a one-to-one correspondence, and under normal reading and writing and data retention working conditions, the signal of the second signal output end controls the conduction of the transistor Mpc to keep the voltage of the first positive power node and the second positive power node consistent. It should be noted that during the reset process, the signal of the second signal output end controls the cutoff of the transistor Mpc.

[0050] By way of example, the transistor Mpc may be a PMOS transistor.

[0051] By way of example, the second signal output terminal can be a reset signal output terminal. In other words, the control terminal of the transistor Mpc is connected to the reset signal output terminal. During the reading and writing process or the data retention process of the storage unit, the signal rst at the reset signal output terminal is 0 (low level). The signal rst at the reset signal output terminal is transmitted to the control terminal of the transistor Mpc, so that the transistor Mpc is turned on, and further the voltage of the first positive power supply node VCI and the second positive power supply node VCr are kept consistent.

[0052] Furthermore, in order to improve the reset speed of the configuration bit cell, as Figure 5 As shown, the storage unit (configuration bitcell) can also be provided with a transistor Mpur, the control end of the transistor Mpur is connected to the third signal output end, the source end is connected to the second positive power supply node VCr, and the drain end is connected to the second storage node cfgb. It should be noted that during the reset process, the signal at the third signal output end controls the conduction of the transistor Mpur.

[0053] By way of example, the transistor Mpur can be a PMOS transistor, and the signal at the third signal output terminal is the signal after the signal at the reset signal output terminal is inverted. For ease of description and distinction, the third signal output terminal can be referred to as the reset signal inverse output terminal. In practical applications, the reset signal inverse output terminal can be understood as the output terminal of the reset inverter connected to the reset signal output terminal, wherein the reset inverter is used to invert the signal rst at the reset signal output terminal. In other words, the level of the signal rst at the reset signal output terminal is opposite to the level of the signal rstn at the reset signal inverse output terminal. During the reset process, the signal rst at the reset signal output terminal is 1 (high level), the signal cfgb is high level, the signal rstn at the reset signal inverse output terminal is 0 (low level), and the signal rstn at the reset signal inverse output terminal is transmitted to the control terminal of the transistor Mpur, and the transistor Mpur is turned on, thereby increasing the reset speed, so that Figure 3 The reset speed of the reset circuit shown can reach nanosecond level.

[0054] As a feasible implementation method, Figure 3 and Figure 5 As shown, each storage cell (configuration bitcell) is respectively connected to a different word line WL, the first storage node cfg of each storage cell (configuration bitcell) is connected to the bit line BL through a switch tube, and the second storage node cfgb is connected to the complementary bit line BLB through a switch tube; if multiple storage cells (configuration bitcells) are arranged in a row, the bit line BL is connected to the first storage nodes cfg of these storage cells (configuration bitcells) through their respective switch tubes; the complementary bit line BLB is connected to the second storage nodes cfgb of these storage cells (configuration bitcells) through their respective switch tubes.

[0055] For example, the signal levels of the input and output ends of the reset unit are opposite. When the storage unit (configuration bitcell) needs to be reset, the signal rst at the first signal input end is set to 1 (high level), and WL is set to 0 (low level), BL is set to BLB (high level), then the first positive power node VCl is set to 0 (low level), and the second positive power node VCr is set to VC. At this time, no matter what value was previously stored in the first storage node cfg, it will become 0. The first storage node cfg will then cause the second storage node cfgb to become 1, thus completing the reset function.

[0056] In an example, Figure 3 and Figure 5As shown, the switch tube of the storage unit (configuration bitcell) includes a first pass transistor PG1 and a second pass transistor PG2. By way of example, the first pass transistor PG1 and the second pass transistor PG2 are NMOS transistors.

[0057] For example, the control terminals of the first transfer transistor PG1 and the second transfer transistor PG2 are respectively connected to the same word line, the input terminal of the first transfer transistor PG1 is connected to the bit line BL, and the output terminal is connected to the first storage node cfg, for example, the source of the first transfer transistor PG1 is connected to the bit line BL, and the drain of the first transfer transistor PG1 is connected to the first storage node cfg. The input terminal of the second transfer transistor PG2 is connected to the complementary bit line BLB, and the output terminal is connected to the second storage node cfgb.

[0058] For example, the first pass transistor PG1 and the second pass transistor PG2 may be bidirectional conduction transistors, and therefore, there is no need to care about the electrodes of the input end and the output end.

[0059] Considering that adding a reset unit will bring about a large hardware resource overhead, in order to reduce the overhead, as a feasible implementation method, such as Fig. 9 As shown, multiple storage units share the same reset unit. The multiple storage units can be a column of configuration memory or a configurable device module. They can be reset based on a certain area size and can complete the reset in 1 to 2 clock cycles, that is, reset can be achieved quickly.

[0060] It should be noted that the structure of the above reset unit is only an example and does not constitute a specific limitation. It needs to be determined in combination with actual conditions. It only needs to ensure that the signal at the output end of the reset unit is at a low level during the reset process.

[0061] like Figure 6 As shown, this embodiment provides another reset circuit, including:

[0062] At least one storage cell (configuration bitcell), each storage cell (configuration bitcell) includes a first positive power node VCl, a second positive power node VCr and a latch circuit, the latch circuit includes a cross-coupled first inverter I1 and a second inverter I2, the first inverter I1 is connected to the first positive power node VCl and the negative power terminal and has a first storage node cfg, the second inverter I2 is connected to the second positive power node VCr and the negative power terminal and has a second storage node cfgb, and the second positive power node VCr is connected to the positive power terminal;

[0063] A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node VCl of each storage unit, and the reset unit is also connected to the positive power supply terminal VC and the negative power supply terminal VSS;

[0064] A setting unit, wherein the input terminal of the setting unit is connected to the second signal output terminal, the output terminal of the setting unit is connected to the second positive power supply node VCr of each storage unit, and the setting unit is also connected to the positive power supply terminal VC and the negative power supply terminal VSS;

[0065] During the reset process, the signal at the first signal output terminal controls the signal at the output terminal of the reset unit to be a low level signal, the signals at the first positive power node VCl and the first storage node cfg are both low level, the signal at the second signal output terminal controls the signal at the output terminal of the set unit to be a high level signal, the second positive power node VCr is high level, and the signal at the second storage node cfgb is high level.

[0066] In this embodiment, the reset unit is used to achieve reset during the power-on process, thereby improving the reset speed of the storage unit, and further speeding up the reset reconfiguration of the storage unit. In addition, due to the presence of the setting unit, setting can also be achieved. It should be understood that if there is no setting requirement, there is no need to set the setting unit. Correspondingly, the second positive power node VCr is directly connected to the positive power terminal VC. During the reset process, the signal of the positive power terminal VC is at a high level, so that the signal of the second positive power node VCr is at a high level. For details, see the above, Figure 3 and Figure 5 .

[0067] For the convenience of description and distinction, the first signal output terminal is referred to as the reset signal output terminal, the second signal output terminal is referred to as the set signal output terminal, and the set signal inverse output terminal refers to the terminal where the signal of the set signal output terminal is inverted and output. In practical applications, the set signal inverse output terminal can be understood as the output terminal of the set inverter connected to the set signal output terminal. The set inverter is used to invert the signal set of the set signal output terminal. In other words, the level of the signal set of the set signal output terminal is opposite to the level of the signal setn of the set signal inverse output terminal.

[0068] As a feasible implementation method, Figures 6 to 8 As shown, the levels of the signals at the input terminal and the output terminal of the reset unit and the set unit are opposite.

[0069] The first inverter I1 includes a first pull-up transistor PU1, a first pull-down transistor PD1 and a second inverter Ir. The second inverter Ir includes a second pull-up transistor PU2 and a second pull-down transistor PD2. For details, please refer to the above description, and no further details will be given here.

[0070] In the reset process, the signal rst at the reset signal output end is high level, and the signal rst at the reset signal output end is transmitted to the input end of the reset unit. The signal at the output end of the reset unit is low level, so that the signal at the first positive power supply node VCI is low level, and the signal at the first storage node cfg is low level. The signal set=0 (low level) at the set signal output end is transmitted to the input end of the set unit. The signal at the output end of the set unit is high level, so that the signal at the second positive power supply node VCr is high level, and the signal cfg connected to the drain end of the second pull-up transistor PU2 is low level, so that the second pull-up transistor PU2 is turned on, and the second pull-down transistor PD2 is turned off, then the signal at the second storage node cfgb is high level, so that the first pull-down transistor PD1 is turned on, the first pull-up transistor PU1 is turned off, and the signal of locking cfg is low level.

[0071] In the setting process, the signal set at the setting signal output end is high level, and the signal set at the setting signal output end is transmitted to the input end of the setting unit, and the signal at the output end of the setting unit is low level, so that the signal at the second positive power supply node VCr is low level, and the signal at the second storage node cfgb is low level. The signal rst at the reset signal output end is 0 (low level), and the signal rst at the reset signal output end is transmitted to the input end of the reset unit, and the signal at the output end of the reset unit is high level, so that the signal at the first positive power supply node VCl is high level, and the signal cfgb connected to the drain end of the first pull-up transistor PU1 is low level, so that the first pull-up transistor PU1 is turned on, and the first pull-down transistor PD1 is turned off, then the signal at the first storage node cfg is high level, so that the second pull-down transistor PD2 is turned on, and the second pull-up transistor PU2 is turned off, and the cfgb signal is locked to a low level.

[0072] In an example, Figures 6 to 8 As shown, the reset unit includes a transistor Mpl and a transistor Mnl. For related contents, please refer to the above text and will not be described in detail here. Figure 7 and Figure 8 As shown, the storage unit (configuration bit cell) can also set the transistor Mpur. For related content, please refer to the above text and will not be elaborated here.

[0073] In an example, Figures 6 to 8As shown, the setting unit includes a transistor Mpr and a transistor Mnr. The control terminals of the transistor Mpr and the transistor Mnr are both connected to the setting signal output terminal, the source terminal of the transistor Mpr is connected to the positive power supply terminal VC, the drain terminal is connected to the drain terminal of the transistor Mnr and the second positive power supply node VCr, and the source terminal of the transistor Mnr is connected to the negative power supply terminal VSS. It should be understood that the output terminal of the setting unit is located on the line connected to the drain terminal of the transistor Mpr and the drain terminal of the transistor Mnr.

[0074] By way of example, the transistor Mpr is a PMOS transistor and the transistor Mnr is an NMOS transistor.

[0075] During the reset process, the signal set at the set signal output end is set to 0 (low level), and the signal set at the set signal output end is transmitted to the control ends of the transistor Mpr and the transistor Mnr respectively, the transistor Mpr is turned on, the transistor Mnr is turned off, and the signal of the line connected to the transistor Mpr and the transistor Mnr is high level, that is, the signal at the output end of the set circuit is high level.

[0076] Due to the introduction of reset units and set units, the original symmetrical storage cells will become asymmetrical during reading and writing, which will lead to poor noise tolerance and poor reading and writing yield.

[0077] To optimize this problem, in an example, Figures 6 to 8 As shown, the reset circuit also includes a transistor Mpc, the control end of the transistor Mpc is connected to the fifth signal output end, the source end and the drain end are respectively connected to the output end of the reset unit and the output end of the set unit in a one-to-one correspondence, and in the normal reading and writing and data retention process of the storage unit, the signal of the fifth signal output end controls the conduction of the transistor Mpc, so that the voltage of the first positive power supply node and the second positive power supply node remain consistent. It should be noted that in the reset and set process, the signal of the fifth signal output end controls the cutoff of the transistor Mpc.

[0078] By way of example, the transistor Mpc may be a PMOS transistor.

[0079] For example, the fifth signal output terminal can be a reset signal output terminal. During the reading and writing process or data retention process of the storage unit, the signal rst of the reset signal output terminal is 0 (low level), and the signal rst of the reset signal output terminal is transmitted to the control terminal of the transistor Mpc, so that the transistor Mpc is turned on.

[0080] Furthermore, in order to improve the reset speed of the configuration bit cell, as Figure 8 As shown, the storage unit (configuration bitcell) can also set the transistor Mpur. For details, please refer to the above and will not be elaborated on this time.

[0081] Furthermore, in order to improve the setting speed of the storage unit (configuration bitcell), the storage unit can also be provided with a transistor Mpul, the control end of the transistor Mpul is connected to the fourth signal output end, the source end is connected to the first positive power supply node VCl, and the drain end is connected to the first storage node cfg. It should be noted that during the power-on process, the signal of the fourth signal output end controls the cut-off of the transistor Mpul, and during the setting process, the signal of the fourth signal output end controls the conduction of the transistor Mpul.

[0082] For example, if the transistor Mpul is a PMOS transistor, the fourth signal output terminal is the reverse output terminal of the set signal. In the reset process, the signal set=0 (low level) at the set signal output terminal, the signal cfgb is high level, the signal setn=1 (high level) at the reverse output terminal of the set signal, the signal setn at the reverse output terminal of the set signal is transmitted to the control terminal of the transistor Mpul, and the transistor Mpul is cut off and does not interfere with the reset. In the setting process, the signal set=1 (high level) at the set signal output terminal, the signal cfgb is low level, the signal setn=0 (low level) at the reverse output terminal of the set signal, the signal setn at the reverse output terminal of the set signal is transmitted to the control terminal of the transistor Mpul, and the transistor Mpul is turned on, thereby increasing the setting speed. Figure 8 The reset circuit shown can achieve a set speed of nanoseconds.

[0083] As a feasible implementation method, Figures 6 to 8 As shown, each storage cell (configuration bitcell) is respectively connected to a different word line WL, the first storage node cfg of each storage cell (configuration bitcell) is connected to the bit line BL through a switch tube, and the second storage node cfgb is connected to the complementary bit line BLB through a switch tube; if multiple storage cells (configuration bitcells) are arranged in a row, the bit line BL is connected to the first storage nodes cfg of these storage cells (configuration bitcells) through their respective switch tubes; the complementary bit line BLB is connected to the second storage nodes cfgb of these storage cells (configuration bitcells) through their respective switch tubes.

[0084] The levels of the signals at the input and output terminals of the reset unit and the set unit are opposite.

[0085] For example, when the storage unit (configuration bitcell) needs to be reset, the signal rst at the reset signal output end is 1 (high level), the signal set at the set signal output end is 0 (low level), and at the same time WL is 0 (low level), BL is BLB is 1 (high level), then the first positive power node VCl is 0 (low level), the second positive power node VCr is VC (high level), at this time, no matter what value was previously stored in the first storage node cfg, it will become 0 (low level), then the first storage node cfg will make the second storage node cfgb become 1 (high level), completing the reset function.

[0086] For example, when the storage unit (configuration bitcell) needs to be set, the signal set at the set signal output terminal is set=1 (high level), and the signal rst at the reset signal output terminal is rst=0 (low level), and at the same time WL=0 (low level), BL=BLB=1 (high level), then the first positive power node VCl=VC (high level), the second positive power node VCr=0 (low level), at this time, no matter what value was previously stored in the second storage node cfgb, it will become 0 (low level), then the second storage node cfgb will make the first storage node cfg become 1 (high level), completing the setting function.

[0087] It should be noted that, in order to save circuit overhead, when there is no setting requirement, only transistor Mp1, transistor Mn1 and transistor Mpc can be added. When there is no reset requirement, only Mpr, Mpc and Mnr can be added without adding Mpl and Mnl.

[0088] Considering that adding a reset unit will bring about a large hardware resource overhead, in order to reduce the overhead, as a feasible implementation method, such as Fig. 9 As shown, multiple storage units share the same reset unit. The multiple storage units can be a column of configuration memory or a configurable device module. They can be reset based on a certain area size and can complete the reset in 1 to 2 clock cycles, that is, reset can be achieved quickly.

[0089] It should be noted that the above-mentioned structures of the reset unit and the set unit are only examples and do not constitute specific limitations. The specific needs to be determined in combination with actual conditions. It is sufficient to ensure that the signal at the output end of the reset unit is at a low level and the output end of the set unit is at a high level during the reset process.

[0090] The various embodiments of the present invention are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.

[0091] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A configuration circuit with reset, characterized in that, include: At least one storage unit, each of the storage units includes a first positive power node, a second positive power node, and a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node and a negative power terminal and has a first storage node, the second inverter is connected to the second positive power node and the negative power terminal and has a second storage node, and the second positive power node is connected to the positive power terminal; A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node of each storage unit, and the reset unit is also connected to the positive power supply end and the negative power supply end; During the reset process, the signal at the first signal output terminal controls the signal at the output terminal of the reset unit to be low level; the signals at the first positive power node and the first storage node are both low level; the signals at the second positive power node and the second storage node are both high level.

2. The configuration circuit according to claim 1, characterized in that: The reset unit comprises: a first transistor and a second transistor, wherein control terminals of the first transistor and the second transistor are connected to the first signal output terminal, a source terminal of the first transistor is connected to the positive power terminal, a drain terminal of the first transistor is connected to the drain terminal of the second transistor and the first positive power node, and a source terminal of the second transistor is connected to the negative power terminal; The storage unit also includes: A third transistor, wherein the control end of the third transistor is connected to the second signal output end, the source end is connected to the second positive power supply node, and the drain end is connected to the second storage node; wherein, during the reset process, the signal at the second signal output end controls the conduction of the third transistor.

3. The configuration circuit according to claim 1, characterized in that: The configuration circuit further includes: A fourth transistor, wherein the control end of the fourth transistor is connected to the third signal output end, and the drain end and the source end are respectively connected to the output end of the reset unit and the second positive power supply node in a one-to-one correspondence; wherein, during the reading and writing process or the data retention process of the storage unit, the signal of the third signal output end controls the conduction of the fourth transistor so that the voltage of the first positive power supply node and the second positive power supply node remain consistent.

4. The configuration circuit according to claim 1, characterized in that: The at least one storage unit is arranged in one or more columns according to an arrangement direction; The storage unit also includes a fifth transistor and a sixth transistor; wherein the control ends of the fifth transistor and the sixth transistor are respectively connected to the same word line, the input end and the output end of the fifth transistor are respectively connected to the bit line and the first storage node in a one-to-one correspondence, and the input end and the output end of the sixth transistor are respectively connected to the complementary bit line and the second storage node in a one-to-one correspondence; wherein, during the reset process, the word line is not turned on, and the bit line and the complementary bit line remain at 1.

5. A configuration circuit with reset, characterized in that: include: At least one storage unit, each of the storage units includes a first positive power node, a second positive power node, and a latch circuit, the latch circuit includes a cross-coupled first inverter and a second inverter, the first inverter is connected to the first positive power node and a negative power terminal and has a first storage node, the second inverter is connected to the second positive power node and the negative power terminal and has a second storage node, and the second positive power node is connected to the positive power terminal; A reset unit, wherein the input end of the reset unit is connected to the first signal output end, the output end is connected to the first positive power supply node of each storage unit, and the reset unit is also connected to the positive power supply end and the negative power supply end; A setting unit, wherein the input end of the setting unit is connected to the second signal output end, the output end is connected to the second positive power supply node of each of the storage units, and the setting unit is also connected to the positive power supply end and the negative power supply end; During the reset process, the signal at the first signal output terminal controls the signal at the output terminal of the reset unit to be low level, and the signals at the first positive power node and the first storage node are both low level; the signal at the second signal output terminal controls the signal at the output terminal of the set unit to be high level, and the signals at the second positive power node and the second storage node are both high level.

6. The configuration circuit according to claim 5, characterized in that: The reset unit comprises: a first transistor and a second transistor, wherein control terminals of the first transistor and the second transistor are connected to the first signal output terminal, a source terminal of the first transistor is connected to the positive power terminal, a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor and the first positive power node, and a source terminal of the second transistor is connected to the negative power terminal; The setting unit includes: a third transistor and a fourth transistor, the control ends of the third transistor and the fourth transistor are connected to the second signal output end, the source end of the third transistor is connected to the positive power supply end, the drain end of the third transistor is respectively connected to the drain end of the fourth transistor and the second positive power supply node, and the source end of the fourth transistor is connected to the negative power supply end.

7. The configuration circuit according to claim 5, characterized in that: The storage unit also includes: a fifth transistor, wherein the control terminal of the fifth transistor is connected to the third signal output terminal, the source terminal is connected to the second positive power supply node, and the drain terminal is connected to the second storage node; wherein, during the reset process, the signal at the third signal output terminal controls the conduction of the fifth transistor; A sixth transistor, wherein the control end of the sixth transistor is connected to the fourth signal output end, the source end is connected to the first positive power supply node, and the drain end is connected to the first storage node; wherein, during the reset process, the signal of the fourth signal output end controls the cutoff of the sixth transistor.

8. The configuration circuit according to claim 5, characterized in that: The configuration circuit further includes: A seventh transistor, wherein the control end of the seventh transistor is connected to the fifth signal output end, and the source end and the drain end are respectively connected to the output ends of the reset unit and the set unit in a one-to-one correspondence; wherein, during the reading and writing process or the data retention process of the storage unit, the signal of the fifth signal output end controls the conduction of the seventh transistor so that the voltages of the first positive power supply node and the second positive power supply node remain consistent.

9. The configuration circuit according to claim 5, characterized in that: The at least one storage unit is arranged in one or more columns according to an arrangement direction; The storage unit also includes an eighth transistor and a ninth transistor; wherein the control ends of the eighth transistor and the ninth transistor are respectively connected to the same word line, the input end and the output end of the eighth transistor are respectively connected to the bit line and the first storage node in a one-to-one correspondence, and the input end and the output end of the ninth transistor are respectively connected to the complementary bit line and the second storage node in a one-to-one correspondence; wherein, during the power-on process, the word line is not turned on, and the bit line and the complementary bit line are turned on.

10. A configuration circuit for an FPGA, characterized in that: Includes the configuration circuit described in any one of claims 1 to 9.

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