A method for forming a multi-layer resistive random access memory

Abstract

The present invention discloses a method for forming a multi-layer resistive memory. The method includes: providing a semiconductor substrate having a bottom electrode formed therein; depositing an oxide with a first oxygen content on the semiconductor substrate to form a first resistive layer located on the semiconductor substrate; depositing an oxide with a second oxygen content on the first resistive layer to form a second resistive layer located on the first resistive layer, wherein the second oxygen content is greater than the first oxygen content; depositing an oxide with the first oxygen content on the second resistive layer to form a third resistive layer located on the second resistive layer; oxidizing the third resistive layer to convert it into a fourth resistive layer, and forming an upper electrode on the fourth resistive layer; and patterning the upper electrode, the first resistive layer, the second resistive layer, and the fourth resistive layer to form a memory. This method can improve the controllability and controllable preparation of the oxide material of the deposited resistive layer, thereby improving the characteristics of the resistive memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for forming a multi-layer resistive random access memory. Background Art

[0002] Currently, memory manufacturing technology is a crucial component of semiconductor integrated circuit manufacturing. As Moore's Law continues to accelerate, the operating frequency of central processing units (CPUs) continues to rise, placing increasing demands on memory performance. Mainstream traditional memory is struggling to meet these demands. The "memory wall" problem is becoming increasingly prominent, prompting the emergence of various new memory technologies.

[0003] Currently, major new memory technologies include resistive random access memory (RRAM), magnetic random access memory (MR), phase change memory (PCM), and ferroelectric memory (FRAM). Cutting-edge research has demonstrated these new memory technologies offer superior performance and promising application prospects. With the exception of phase change memory, which has already entered mass production, the remaining new memory technologies have yet to achieve widespread adoption. For these new memory technologies to achieve mass production, stable and reliable production processes are crucial, in addition to offering superior cost-performance compared to existing mainstream memory technologies.

[0004] Taking oxide resistive random access memory as an example, although the structure of the memory itself is very simple, how to prepare it in a controllable manner is the key to its large-scale production and application. In the prior art, resistive random access memory is usually a MIM sandwich structure. The I in this structure is a single component material, which is easy to control and apply on a large scale. In order to modulate and improve the characteristics of resistive random access memory, a double-layer or even multi-layer resistive random access layer structure is required. Taking sputtering deposition to prepare resistive random access layer materials as an example, the deposition of multiple layers of resistive random access materials is achieved by changing the sputtering gas ratio. However, in the actual process, since the surface of the sputtering target material will be oxidized and varies with different sputtering gases, a layer of oxide is uncontrolled at the beginning of sputtering deposition, affecting the consistency of the resistive random access memory device.

[0005] Therefore, how to effectively control the processing of the multi-layer resistive switching structure in the existing memory is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] An embodiment of the present invention provides a method for forming a multi-layer resistive random access memory, which is used to improve the material consistency and controllable preparation problems of the resistive random access layer in the existing memory and enhance the memory characteristics.

[0007] In a first aspect, the present invention provides a method for forming a multi-layer resistive memory, the method comprising: providing a semiconductor substrate, wherein a lower electrode is formed in the semiconductor substrate, and the lower electrode contacts the upper surface of the semiconductor substrate; depositing an oxide with a first oxygen content on the semiconductor substrate to form a first resistive layer located on the semiconductor substrate; depositing the oxide with a second oxygen content on the first resistive layer to form a second resistive layer located on the first resistive layer, wherein the second oxygen content is greater than the first oxygen content; depositing the oxide with the first oxygen content on the second resistive layer to form a third resistive layer located on the second resistive layer; oxidizing the third resistive layer to convert the third resistive layer into a fourth resistive layer, wherein the oxygen content of the fourth resistive layer is greater than the oxygen content of the third resistive layer; forming an upper electrode on the fourth resistive layer; and patterning the upper electrode, the first resistive layer, the second resistive layer, and the fourth resistive layer to form a memory.

[0008] The beneficial effect of the method for forming a memory provided by the present invention is that: because the oxygen content of the first resistive switching layer is the same as the oxygen content of the third resistive switching layer, the oxygen content of the three resistive switching layers varies from low to high and low, similar to a "peak type". In this way, during the manufacturing process, after the previous substrate is made into a memory, the next substrate is started to be made, and the next substrate also starts to deposit the oxide with the first oxygen content first. Compared with the existing technology, the existing technology has two resistive switching layers, and the oxygen content of the second resistive switching layer is greater than that of the first resistive switching layer. After the previous substrate is made into a memory, the next substrate is started to be made, and the next substrate also needs to start to deposit the oxide with the first oxygen content first. However, due to the influence of the process of the previous substrate, there will be a layer of oxide with a high oxygen content at the beginning of the deposition, resulting in an uncontrolled oxide layer. The present application adopts a deposition method similar to the "peak type", and the oxygen content state of the target material surface is consistent at the beginning and the end of the deposition, avoiding the problem of an uncontrolled oxide layer at the beginning of the deposition in the prior art. This method improves the consistency and controllable preparation of the resistive switching layer and improves the memory characteristics.

[0009] Optionally, the oxide is deposited by any one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0010] Optionally, the oxide is at least one of copper oxide, aluminum oxide, hafnium oxide, titanium oxide or tantalum oxide.

[0011] Optionally, the metal material of the upper electrode and the lower electrode includes at least one of copper, aluminum, hafnium, titanium, tantalum, titanium nitride or tantalum nitride.

[0012] Optionally, a specific method of performing oxidation treatment on the third resistive switching layer may include: performing oxidation treatment on the third resistive switching layer using an oxidizing gas, wherein the oxidation treatment temperature is 100° C. to 400° C.

[0013] Optionally, forming an upper electrode on the fourth resistive layer includes: forming an upper electrode on the fourth resistive layer by physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition.

[0014] Optionally, the oxidizing gas is oxygen, ozone or nitrous oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic flow chart of a method for forming a multi-layer resistive random access memory provided by the prior art;

[0017] Figure 2 A schematic diagram of various stages of a manufacturing process for a multi-layer resistive random access memory provided by an embodiment of the present invention.

[0018] Component number description

[0019] 100 semiconductor substrates

[0020] 200 lower electrode

[0021] 300 first resistive switching layer

[0022] 400 second resistive switching layer

[0023] 500 third resistive switching layer

[0024] 600 fourth resistive switching layer

[0025] 700 upper electrode DETAILED DESCRIPTION

[0026] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also included in the scope of protection of the present invention.

[0027] It should be noted that in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structures in the accompanying drawings are not drawn according to general proportions, and are partially enlarged, deformed and simplified. Therefore, it should be avoided to understand this as a limitation of the present invention.

[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the following further Figure 1 FIG. 1 shows a flow chart of a method for forming a memory. Figure 2 A schematic diagram of the phased results of each process preparation stage in this example is shown.

[0029] See also Figure 1 The manufacturing process of the memory provided by the embodiment of the present invention includes the following steps:

[0030] S101 , providing a semiconductor substrate 100 , wherein a lower electrode 200 is formed in the semiconductor substrate 100 .

[0031] like Figure 2 As shown in (a) of FIG. 1 , the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The semiconductor substrate 100 may also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate.

[0032] Specifically, the silicon substrate may already have the required CMOS processing circuitry fabricated. A lower electrode 200, which is a metal electrode, is then formed on the silicon substrate. In this embodiment, for example, a 12-inch silicon wafer may be used as the silicon substrate. The CMOS control circuitry is already fabricated within the silicon substrate. The CMOS circuit is connected to the underlying metal electrode via metal. The metal electrode may be made of various metal materials, such as copper, aluminum, titanium nitride, or tantalum nitride. In this embodiment, tantalum nitride is used, with a thickness of 50 nanometers.

[0033] S102 , depositing an oxide with a first oxygen content on the semiconductor substrate 100 to form a first resistive layer 300 on the semiconductor substrate 100 .

[0034] See also Figure 2 As shown in (b), physical vapor deposition is used to deposit oxide on the front surface of the N-type or P-type silicon substrate to form the first resistive layer 300. The oxide of the first resistive layer 300 can be at least one of copper oxide, aluminum oxide, hafnium oxide, titanium oxide, and tantalum oxide, each having a low oxygen content.

[0035] In this embodiment, illustratively, 2 nm titanium oxide is deposited on the front surface of an N-type or P-type silicon substrate by physical vapor deposition (PVD) as the first resistive layer 300 , and the ratio of oxygen O to titanium Ti in the titanium oxide is 1.2:1.

[0036] S103 , depositing the oxide with a second oxygen content on the first resistive layer 300 to form a second resistive layer 400 located on the first resistive layer 300 , wherein the second oxygen content is greater than the first oxygen content.

[0037] See also Figure 2 As shown in (c) of FIG. 3 , specifically, the oxide is deposited on the first resistive switching layer 300 using physical vapor deposition to form the second resistive switching layer 400. The second resistive switching layer 400 has the same composition as the first resistive switching layer 300, but has a different oxygen content. In this embodiment, 5 nm of titanium oxide is sputter-deposited as the second resistive switching layer 400. The ratio of oxygen (O) to titanium (Ti) in the titanium oxide is 1.6:1.

[0038] S104 , depositing the oxide with the first oxygen content on the second resistive switching layer 400 to form a third resistive switching layer 500 located on the second resistive switching layer.

[0039] See also Figure 2 As shown in (d), physical vapor deposition is used to deposit an oxide with the same oxygen content as the first resistive layer on the second resistive layer 400, thereby forming the third resistive layer 500. The third resistive layer 500 has the same composition as the first resistive layer 300, and the oxygen content of the third resistive layer 500 is lower than that of the second resistive layer 400. In this embodiment, 5 nm of titanium oxide is deposited on the second resistive layer 400 using physical vapor deposition (PVD). The ratio of oxygen (O) to titanium (Ti) in the titanium oxide is 1.2:1.

[0040] S105 , performing oxidation treatment on the third resistive switching layer 500 , so that the third resistive switching layer 500 is converted into a fourth resistive switching layer 600 , wherein the oxygen content of the fourth resistive switching layer 600 is greater than that of the third resistive switching layer 500 .

[0041] Specifically, a possible implementation method is as follows: Figure 2 As shown in (e), the third resistive layer 500 can be oxidized with an oxidizing gas such as oxygen, ozone, or nitrous oxide at a temperature of 100°C-400°C to further increase the oxygen content of the third resistive layer 500, thereby converting the third resistive layer 500 into a fourth resistive layer 600.

[0042] In this embodiment, for example, the titanium oxide of the third resistive layer 500 is treated by decoupled plasma oxidation at 400° C. to increase the oxygen content in the third resistive layer 500 to a ratio of oxygen O to titanium Ti of 1.9:1.

[0043] It can be seen that the ultimate goal achieved by this embodiment is: the oxygen content of the fourth resistive layer 600 is greater than the oxygen content of the second resistive layer 400 and is greater than the oxygen content of the first resistive layer 300, and the oxygen content of the third resistive layer 500 is equal to the oxygen content of the first resistive layer 300. The specific values ​​of the ratios of oxygen O and titanium Ti in this article are exemplary and do not constitute a limitation on the scope of protection of this article.

[0044] S106 , forming an upper electrode 700 on the fourth resistive layer.

[0045] Specifically, a possible implementation method is as follows: Figure 2 As shown in (f), physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition can be used to deposit an upper metal electrode to form the upper electrode 700. In this embodiment, 50 nanometers of tantalum nitride is exemplarily deposited by physical vapor deposition as the upper electrode metal.

[0046] S107 , patterning the upper electrode 700 , the first resistive switching layer 300 , the second resistive switching layer 400 and the fourth resistive switching layer 600 to form a memory.

[0047] Specifically, a possible implementation method is to use photolithography to form Figure 2 The memory shown in (g).

[0048] It is worth noting that the temperature for oxidation treatment generally does not exceed 400°C. Although the higher the temperature, the more intense the reaction and the shorter the reaction time, once the temperature exceeds 400°C, the properties of the metal may be destroyed.

[0049] In summary, in the method for forming a multi-layer resistive memory provided by the present invention, since the oxygen content of the first resistive layer is the same as that of the third resistive layer, the oxygen content of the three resistive layers varies from low to high and low, similar to a "peak type". In this way, during the manufacturing process, after the previous substrate is made into a memory, the next substrate is started to be made, and the next substrate also starts to deposit the oxide with the first oxygen content first. Compared with the prior art, the prior art has two resistive layers, and the oxygen content of the second resistive layer is greater than that of the first resistive layer. After the previous substrate is made into a memory, the next substrate is started to be made, and the next substrate also needs to start to deposit the oxide with the first oxygen content first. However, due to the influence of the process of the previous substrate, there will be a layer of oxide with a high oxygen content at the beginning of the deposition, resulting in an uncontrolled oxide layer. The present application adopts a deposition method similar to the "peak type", and the oxygen content state of the target surface at the beginning and the end of the deposition is consistent, avoiding the problem in the prior art that there is an uncontrolled oxide layer at the beginning of the deposition. This method improves the consistency and controllable preparation of the resistive layer, and improves the memory characteristics.

[0050] The above descriptions are merely preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the scope of protection of the present invention.

[0051] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

Claims

1. A method for forming a multi-layer resistive random access memory, characterized in that: include: Providing a semiconductor substrate, wherein a lower electrode is formed in the semiconductor substrate, and the lower electrode contacts the upper surface of the semiconductor substrate; Depositing an oxide with a first oxygen content on the semiconductor substrate by physical vapor deposition to form a first resistive switching layer on the semiconductor substrate; Depositing the oxide with a second oxygen content on the first resistive switching layer by physical vapor deposition or sputtering to form a second resistive switching layer located on the first resistive switching layer, wherein the second oxygen content is greater than the first oxygen content; Depositing the oxide with the first oxygen content on the second resistive switching layer by physical vapor deposition to form a third resistive switching layer located on the second resistive switching layer; performing an oxidation treatment on the third resistance switching layer so that the third resistance switching layer is converted into a fourth resistance switching layer, wherein the oxygen content of the fourth resistance switching layer is greater than the oxygen content of the second resistance switching layer; forming an upper electrode on the fourth resistive layer; The upper electrode, the first resistive switching layer, the second resistive switching layer and the fourth resistive switching layer are patterned to form a memory.

2. The forming method according to claim 1, wherein: The oxide is deposited by any one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.

3. The forming method according to claim 2, wherein: The oxide is at least one of copper oxide, aluminum oxide, hafnium oxide, titanium oxide or tantalum oxide.

4. The forming method according to any one of claims 1 to 3, characterized in that: The metal material of the upper electrode and the lower electrode includes at least one of copper, aluminum, hafnium, titanium, tantalum, titanium nitride or tantalum nitride.

5. The forming method according to any one of claims 1 to 3, characterized in that: The third resistive switching layer is subjected to an oxidation treatment, comprising: The third resistive switching layer is oxidized by using an oxidizing gas at a temperature of 100° C. to 400° C.

6. The forming method according to any one of claims 1 to 3, characterized in that: forming an upper electrode on the fourth resistive switching layer, comprising: An upper electrode is formed on the fourth resistive layer by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

7. The forming method according to claim 5, wherein: The oxidizing gas is oxygen, ozone or laughing gas.

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