Storage device and method for operating the same

Abstract

The present application relates to a storage device, which includes a memory device and a memory controller, and the memory controller includes a plurality of cores. The memory controller can load a bootloader image for firmware update operation into the memory of a core arbitrarily selected from the plurality of cores, receive a new firmware image from a host in response to the bootloader image running in the selected core, and use the new firmware image to update the firmware images stored in the memory of each of the plurality of cores.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0128796, filed with the Korean Intellectual Property Office on October 6, 2020, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a storage device and a method of operating the storage device. Background art

[0004] Generally, a storage device is a device that stores data under the control of a host device such as a computer, a smart phone, etc. The storage device may include a memory device configured to store data and a memory controller configured to control the memory device. The memory device is mainly classified into a volatile memory device and a non - volatile memory device.

[0005] A volatile memory device is a memory device that stores data only while power is supplied thereto and loses the stored data when the power is turned off. Examples of the volatile memory device include a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0006] A non - volatile memory device is a memory device that can retain the stored data even when the power is turned off. Examples of the non - volatile memory device include a read - only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc. Summary of the invention

[0007] Various embodiments of the present disclosure are directed to a storage device having improved firmware update performance and a method of operating the storage device.

[0008] A memory controller according to an embodiment of the present disclosure may include a processor including a plurality of cores and a buffer memory. The buffer memory may store a bootloader image for firmware update operation. The processor may load the bootloader image from the buffer memory into the memory of a core arbitrarily selected from the plurality of cores, receive a new firmware image from the host in response to the bootloader image running in the selected core, and update the firmware image stored in the memory of each of the plurality of cores using the new firmware image.

[0009] A method of operating a memory controller according to an embodiment of the present disclosure, the memory controller including a plurality of cores and a buffer memory and being configured to control a memory device, the method may include: loading a bootloader image into the memory of a core arbitrarily selected from the plurality of cores, the bootloader image being stored in the buffer memory and provided for a firmware update operation; receiving a new firmware image from a host in response to the bootloader image running in the selected core; and updating the firmware image stored in the memory of each of the plurality of cores with the new firmware image.

[0010] A storage device according to an embodiment of the present disclosure may include: a memory device; and a memory controller including a plurality of cores. The memory controller may load a bootloader image for a firmware update operation into the memory of a core arbitrarily selected from the plurality of cores, receive a new firmware image from a host in response to the bootloader image running in the selected core, and update the firmware image stored in the memory of each of the plurality of cores with the new firmware image. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 is for describing Figure 1 the configuration and operation of a processor according to an embodiment

[0013] Figure 3 is for describing Figure 2 a firmware image of

[0014] Figure 4 is for describing Figure 1 the configuration and operation of a processor according to an embodiment

[0015] Figure 5 is for describing Figure 4 a firmware image of

[0016] Figure 6 is a flowchart for describing the operation of a memory controller according to an embodiment of the present disclosure.

[0017] Figure 7 is for describing Figure 6 a method of

[0018] Figure 8 is a diagram showing Figure 1 a memory controller according to an embodiment of the present disclosure.

[0019] Figure 9is a block diagram of a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0020] Figure 10 is a block diagram of a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0021] Figure 11 is a block diagram of a user system to which a storage device according to an embodiment of the present disclosure is applied. Detailed Description

[0022] The description of the specific structures or functions in the embodiments of the present disclosure introduced in this specification or application is only for describing the embodiments of the present disclosure. This description should not be construed as being limited to the embodiments described in the specification or application.

[0023] Figure 1 is a view showing a storage device 50 according to an embodiment of the present disclosure.

[0024] Referring to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 configured to control the operation of the memory device 100. The storage device 50 may be a device configured to store data under the control of a host 300 such as: a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, an in-vehicle infotainment system, etc.

[0025] According to the host interface, the storage device 50 may be manufactured as any one of various storage devices, and the host interface is a communication system for communicating with the host 300. For example, the storage device 50 may be configured by any one of various storage devices such as: an SSD, an MMC, an eMMC, an RS-MMC, a micro MMC type multimedia card, an SD, a mini SD, a micro SD type secure digital card, a universal serial bus (USB) storage device, a universal flash (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, a memory stick, etc.

[0026] The storage device 50 may be manufactured in the form of any one of various package types such as: a package on package (POP) type, a system in package (SIP) type, a system on chip (SOC) type, a multi-chip package (MCP) type, a chip on board (COB) type, a wafer level package (WFP) type, a wafer level stack package (WSP) type, etc.

[0027] The memory device 100 can store data therein. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 can include a memory cell array including a plurality of memory cells configured to store data therein.

[0028] The memory cells can include single-level cells (SLCs) capable of storing one unit of data, multi-level cells (MLCs) capable of storing two bits of data, three-level cells (TLCs) capable of storing three bits of data, or quad-level cells (QLCs) capable of storing four bits of data.

[0029] The memory cell array can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. Each memory block can include a plurality of pages. In an embodiment, a page can be a unit for storing data in the memory device 100 or reading the stored data from the memory device 100.

[0030] A memory block can be a unit for erasing data. In an embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth-generation low-power double data rate (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low-power DDR (LPDDR), a rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for simplicity of explanation, it is assumed that the memory device 100 is a NAND flash memory.

[0031] The memory device 100 can receive commands and addresses from the memory controller 200 and access a region of the memory cell array selected by the address. In other words, the memory device 100 can perform an operation indicated by the command on the region selected by the address. For example, the memory device 100 can perform a write (or program) operation, a read operation, and an erase operation. During the program operation, the memory device 100 can program data into the region selected by the address. During the read operation, the memory device 100 can read data from the region selected by the address. During the erase operation, the memory device 100 can erase data from the region selected by the address.

[0032] The memory controller 200 can control all operations of the storage device 50.

[0033] When power is applied to the storage device 50, the memory controller 200 may execute firmware (FW). In the case where the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a flash translation layer (FTL) to control communication between the host 300 and the memory device 100.

[0034] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA) indicating the address of a memory cell in which the data to be stored is included, the memory cell being included in the memory device 100.

[0035] The memory controller 200 may control the memory device 100 to perform a programming operation, a read operation, or an erase operation in response to a request from the host 300. During the programming operation, the memory controller 200 may provide a write command, a PBA, and data to the memory device 100. During the read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During the erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0036] In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of requests from the host 300, and transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a programming operation for wear leveling and a programming operation for garbage collection.

[0037] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving scheme, thereby improving operation performance. The interleaving scheme may be an operation scheme in which the operation periods of at least two or more memory devices 100 overlap.

[0038] In an embodiment, the memory controller 200 may include a processor 210 and a buffer memory 220. The processor 210 may include a plurality of cores. Each core may store a firmware image for the operation of the storage device 50. Each core may execute the stored firmware to control all operations of the storage device 50.

[0039] The memory controller 200 may load a boot loader image from the buffer memory 220 into the memory of any one of the plurality of cores selected. The memory controller 200 may dynamically allocate an address of a target memory area in the memory of the selected core into which the boot loader image is to be loaded. The memory controller 200 may run the boot loader image loaded into the target memory area. The memory controller 200 may receive a new firmware image from the host 300 in response to the running boot loader image. The memory controller 200 may update the firmware images stored in the memory of each of the plurality of cores with the new firmware image. In an embodiment, the memory controller 200 may update the firmware images stored in the memory of each of the plurality of cores with the new firmware image in parallel with processing requests received from the host 300.

[0040] The memory controller 200 may control the memory device 100 such that the memory device 100 stores the updated firmware images stored in the memory of each of the plurality of cores therein before power-off.

[0041] The buffer memory 220 may store a boot loader image for a firmware update operation. In an embodiment, the buffer memory 220 may be formed of a volatile memory device. In this case, after power-on, the boot loader image stored in the memory device 100 may be loaded into the buffer memory 220. In another embodiment, the buffer memory 220 may be formed of a non-volatile memory device. In this case, loading the boot loader image from the memory device 100 may be omitted.

[0042] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial ATA (SATA), Serial SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low-Rank DIMM (LRDIMM) communication methods.

[0043] Figure 2 is a diagram for describing Figure 1 the configuration and operation of the processor 210 according to an embodiment.

[0044] Refer to Figure 2, the processor 210 may include multiple cores Core 1 to Core 4. The number of cores included in the processor 210 is not limited to the number in this embodiment.

[0045] The first core Core 1 may be a processor dedicated to running firmware updates. The firmware image to be loaded into the memory of the first core Core 1 may include firmware update code for running firmware updates. The firmware image including the firmware update code (e.g., the main firmware image) may be loaded into the memory area corresponding to the static address in the memory of the first core Core 1.

[0046] The first core Core 1 may, in response to the running firmware update code, use the new firmware image received from the host 300 to update the firmware images stored in the memories of the other cores Core 2 to Core 4.

[0047] During the firmware update run, since the firmware update code included in the main firmware image is running, the main firmware image stored in the memory of the first core Core 1 may not be updated. In other words, since the first core Core 1 communicates with the host 300 in response to the running firmware update code, the firmware image update cannot be performed on the first core Core 1 when communicating with the host 300.

[0048] Before power-off, the new firmware images updated in the memories of the other cores Core 2 to Core 4 may be stored in the memory device 100. Thereafter, after power-on, the new firmware images stored in the memory device 100 are loaded into the memory of the first core Core 1, so that the main firmware image corresponding to the first core Core 1 can be updated.

[0049] In other words, after the communication with the host 300 has been completed, the main firmware image stored in the memory of the first core Core 1 can be updated by a power-off or power-on process.

[0050] Figure 3 is a diagram for describing Figure 2 the firmware image.

[0051] Referring to Figure 3 , the memory of each core of the processor 210 may store a corresponding firmware image.

[0052] Here, the firmware update code for running firmware updates may be included in the main firmware image corresponding to the first core Core 1 dedicated to firmware updates. The firmware update code may be stored in the memory area corresponding to the static address in the memory of the first core Core 1.

[0053] Figure 4 is a diagram for describing the configuration and operation of a processor 210 according to an embodiment. Figure 1

[0054] Referring to Figure 4 , the processor 210 may include multiple cores Core 1 to Core 4. The number of cores included in the processor 210 is not limited to the number in this embodiment.

[0055] In Figure 4 , there may not be a separate processor dedicated to the firmware update operation. Therefore, any one of the multiple cores Core 1 to Core 4 can be selected to perform the firmware update operation.

[0056] The firmware update code can be generated as a bootloader image. The generated bootloader image can be stored in the buffer memory 220. The bootloader image for the firmware update operation can be loaded from the buffer memory 220 into the memory of any one of the randomly selected cores from Core 1 to Core 4. In an embodiment, the bootloader image can be generated as binary code.

[0057] The selected core can dynamically allocate, among the memory regions of the selected core, a target memory region into which the bootloader image is to be loaded. The target memory region can be an empty region where no data is stored. Therefore, the address of the target memory region can be variable.

[0058] Referring to Figure 4 , the selected core can be the second core Core 2. The second core Core 2 can run the bootloader image in the target memory region loaded into it. The second core Core 2 can receive a new firmware image from the host 300 in response to the running bootloader image. The second core Core 2 can update the firmware images stored in the memories of each of the other cores Core 1, Core 3, and Core 4 using the new firmware image in response to the running bootloader image.

[0059] The firmware image stored in the memory of the second core Core 2 can also be updated using the new firmware image. The reason for this is that regardless of the region in the memory of the second core Core 2 where the firmware image is loaded, the bootloader image has been loaded into the target memory region as an empty region. Therefore, even when the bootloader image is running, the firmware image stored in the region other than the target memory region in the memory of the second core Core 2 can be updated using the new firmware image.

[0060] In other words, the second core Core 2 can perform communication with the host 300 in response to the running bootloader image code loaded into the target memory area, but performs this operation regardless of the firmware image stored in other areas where the second core Core 2 runs, so that the second core Core 2 can update the firmware image stored therein while performing communication with the host 300. In other words, the second core Core 2 can perform the operation of updating the firmware images stored in the memories of each of the multiple cores Core 1 to Core 4 in parallel with processing the requests received from the host 300.

[0061] Before power-off, the newly updated firmware images in the memories of each core can be stored in the memory device 100.

[0062] Figure 5 is a diagram for describing Figure 4 the firmware image.

[0063] Referring to Figure 5 each core's memory can store the corresponding firmware image.

[0064] Here, the bootloader image for firmware update operation can be generated separately instead of being included in a specific firmware image. The bootloader image can be loaded into the memory of any one of the multiple cores Core 1 to Core 4 selected.

[0065] In Figure 5 the embodiment, in the memory of any selected core (for example, the second core Core 2), in response to a dynamically allocated address, i.e., a dynamic address, the bootloader image can be loaded into the target memory area as an empty memory area.

[0066] Figure 6 is a flowchart for describing the operation of the Figure 1 memory controller 200 according to an embodiment of the present disclosure.

[0067] Referring to Figure 6 in S601, the memory controller 200 can load the bootloader image from the buffer memory 220 into the memory of the selected core among the multiple cores in the processor 210. The bootloader image provided for the firmware update operation is stored in the buffer memory 220. The bootloader image loaded into the memory of the selected core is stored in the empty target memory area in the memory of the selected core instead of being included in the firmware image of the selected core.

[0068] At S603, the memory controller 200 may receive a new firmware image from the host 300 in response to a boot loader image running in the selected core.

[0069] At S605, the memory controller 200 may update the firmware images stored in the memories of each of the multiple cores with the new firmware image.

[0070] Figure 7 is a flowchart for a method for Figure 6 described in detail.

[0071] Referring to Figure 7 , at S701, the memory controller 200 may dynamically allocate an address of a target memory region in the memory of the selected core into which the boot loader image is to be loaded.

[0072] At S703, the memory controller 200 may load the boot loader image into the target memory region and then run the boot loader image.

[0073] At S705, the memory controller 200 may receive a new firmware image from the host 300 in response to the running boot loader image.

[0074] At S707, the memory controller 200 may update the firmware images stored in the memories of each of the multiple cores with the new firmware image in parallel with processing requests received from the host 300.

[0075] Figure 8 is a diagram showing a memory controller 1000 according to an embodiment. Figure 8 The memory controller 1000 of Figure 1 may correspond to the memory controller 200 of

[0076] Referring to Figure 8 , the memory controller 1000 is coupled to a host (e.g., Figure 1 the host 300 of Figure 1 ) and a memory device (e.g.,

[0077] the memory device 100 of ). In response to a request from the host 300, the memory controller 1000 may access the memory device 100. For example, the memory controller 1000 may control write operations, read operations, erase operations, and background operations of the memory device 100. The memory controller 1000 may provide an interface between the memory device 100 and the host 300. The memory controller 1000 may drive firmware for controlling the memory device 100.The memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction code (ECC) circuit 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

[0078] The bus 1070 may provide a channel among the components of the memory controller 1000.

[0079] The processor 1010 may control all operations of the memory controller 1000 and perform logical operations. The processor 1010 may communicate with the host 300 through the host interface 1040 and with the memory device 100 through the memory interface 1060. Additionally, the processor 1010 may communicate with the memory buffer 1020 through the buffer controller 1050. The processor 1010 may control the operation of a storage device (e.g., Figure 1 storage device 50) by using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0080] The processor 1010 may perform the functions of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by the host 300 into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the LBA into the PBA by using a mapping table. The address mapping method using the FTL may be modified in various ways according to the mapping unit. Representative address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

[0081] The processor 1010 may randomize the data received from the host 300. For example, the processor 1010 may use a randomization seed to randomize the data received from the host 300. The randomized data may be provided as data to be stored to the memory device 100 and may be programmed into the memory cell array of the memory device 100.

[0082] During a read operation, the processor 1010 may derandomize the data received from the memory device 100. For example, the processor 1010 may use a derandomization seed to derandomize the data received from the memory device 100. The derandomized data may be output to the host 300.

[0083] In an embodiment, the processor 1010 may drive software or firmware to perform a randomization operation or a derandomization operation.

[0084] The memory buffer 1020 can be used as the operating memory, cache memory, or buffer memory of the processor 1010. The memory buffer 1020 can store the code and commands to be run by the processor 1010. The memory buffer 1020 can store the data to be processed by the processor 1010. The memory buffer 1020 can include static RAM (SRAM) or dynamic RAM (DRAM).

[0085] The ECC circuit 1030 can perform error correction. The ECC circuit 1030 can perform an ECC encoding operation based on the data to be written to the memory device 100 through the memory interface 1060. The ECC-encoded data can be transmitted to the memory device 100 through the memory interface 1060. The ECC circuit 1030 can perform an ECC decoding operation on the data received from the memory device 100 through the memory interface 1060. For example, the ECC circuit 1030 can be included in the memory interface 1060 as a component of the memory interface 1060.

[0086] The host interface 1040 can communicate with the external host 300 under the control of the processor 1010. The host interface 1040 can perform communication using at least one of various communication methods such as: Universal Serial Bus (USB), Serial ATA (SATA), Serial SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High-Speed PCI (PCIe), High-Speed Non-Volatile Memory (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low-Rank DIMM (LRDIMM) communication methods.

[0087] The buffer controller 1050 can control the memory buffer 1020 under the control of the processor 1010.

[0088] The memory interface 1060 can communicate with the memory device 100 under the control of the processor 1010. The memory interface 1060 can communicate commands, addresses, and data with the memory device 100 through a channel.

[0089] In another embodiment, the memory controller 1000 may neither include the memory buffer 1020 nor the buffer controller 1050 therein.

[0090] For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load the code from a non-volatile memory device (e.g., read-only memory) provided in the memory controller 1000. Alternatively, the processor 1010 may load the code from the memory device 100 through the memory interface 1060.

[0091] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transfer data in the memory controller 1000. The control bus may transfer control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be separated from each other and may neither interfere with nor affect each other. The data bus may be coupled to the host interface 1040, the buffer controller 1050, the ECC circuit 1030, and the memory interface 1060. The control bus may be coupled to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0092] In an embodiment, Figure 1 the processor 210 may be included in the processor 1010. Figure 1 the buffer memory 220 may be included in the memory buffer 1020.

[0093] Figure 9 is a block diagram of a memory card system 2000 to which a storage device according to an embodiment of the present disclosure is applied.

[0094] Referring to Figure 9 , the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0095] The memory controller 2100 is coupled to the memory device 2200. The memory controller 2100 may access the memory device 2200. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2200 and the host. The memory controller 2100 may drive firmware for controlling the memory device 2200. The memory controller 2100 may be implemented in the same manner as the memory controller 200 described with reference to Figure 1 .

[0096] In an embodiment, the memory controller 2100 may include components such as one or more of a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC circuit.

[0097] The memory controller 2100 can communicate with an external device (e.g., a host) via the connector 2300. The memory controller 2100 can communicate with the external device based on a specific communication protocol. In an embodiment, the memory controller 2100 can communicate with the external device via at least one of various communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In an embodiment, the connector 2300 can be defined via at least one of the various communication protocols described above.

[0098] In an embodiment, the memory device 2200 can be implemented as any one of various non-volatile memory devices such as: Electrically Erasable Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and Spin Transfer Torque Magnetic RAM (STT-MRAM).

[0099] In an embodiment, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as: Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF) card, SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, or microMMC), SD card (SD, miniSD, microSD, or SDHC), or Universal Flash Storage (UFS).

[0100] Figure 10 is a block diagram of a Solid State Drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

[0101] Referring to Figure 10 , the SSD system 3000 can include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals SIG with the host 3100 via the signal connector 3001 and can receive power PWR via the power connector 3002. The SSD 3200 can include an SSD controller 3210, a plurality of non-volatile memories (NVMs) 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0102] In an embodiment, the SSD controller 3210 may perform the functions of the memory controller 200 described above with reference to Figure 1 Description of the memory controller 200.

[0103] The SSD controller 3210 may control a plurality of NVMs 3221 to 322n in response to a signal SIG received from the host 3100. In an embodiment, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined through at least one of various interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and High-Speed Non-Volatile Memory (NVMe) interface.

[0104] The auxiliary power supply 3230 may be connected to the host 3100 through a power connector 3002. Power PWR may be supplied from the host 3100 to the auxiliary power supply 3230, and the auxiliary power supply 3230 may be charged through the power PWR. When the supply of power from the host 3100 is not stable, the auxiliary power supply 3230 may supply power to the SSD 3200. In an embodiment, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided on the motherboard and may supply auxiliary power to the SSD 3200.

[0105] The buffer memory 3240 serves as the buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of NVMs 3221 to 322n, or may temporarily store metadata (e.g., mapping table) of the plurality of NVMs 3221 to 322n. The buffer memory 3240 may include any one of volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, and non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0106] Figure 11 FIG. is a block diagram of a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

[0107] With reference to Figure 11, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0108] The application processor 4100 may run components, an operating system (OS), or user programs included in the user system 4000. In an embodiment, the application processor 4100 may include one or more of a controller, an interface, a graphics engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be configured as a system on a chip (SoC).

[0109] The memory module 4200 may function as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, or LPDDR3 SDRAM, or non-volatile memories such as PRAM, ReRAM, MRAM, or FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP), and then be configured as a single semiconductor package.

[0110] The network module 4300 may communicate with external devices. For example, the network module 4300 may support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communications. In an embodiment, the network module 4300 may be included in the application processor 4100.

[0111] The storage module 4400 may store data therein. For example, the storage module 4400 may store data received from the application processor 4100. Optionally, the storage module 4400 may transfer the data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 may be implemented as a non-volatile memory such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, NAND flash memory with a three-dimensional (3D) structure, etc. In an embodiment, the storage module 4400 may be configured as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

[0112] In an embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, and each of the plurality of non-volatile memory devices may operate in the same manner as the memory device 100 described above with reference to Figure 1 The storage module 4400 may operate in the same manner as the storage device 50 described above with reference to Figure 1 The storage module 4400 may operate in the same manner as the storage device 50 described above with reference to

[0113] The user interface 4500 may include one or more interfaces for inputting data or instructions to the application processor 4100 or outputting data to an external device. In an embodiment, the user interface 4500 may include one or more of the following user input interfaces: keyboard, keypad, button, touch panel, touch screen, touchpad, trackball, camera, microphone, gyro sensor, vibration sensor, piezoelectric device, etc. The user interface 4500 may further include one or more of the following user output interfaces: liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, monitor, etc.

[0114] As described above, various embodiments of the present disclosure may provide a storage device having improved firmware update performance and a method of operating the storage device.

[0115] Examples of embodiments have been disclosed herein. Although specific terms have been employed, their use and interpretation are for general and descriptive purposes only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art as of the filing of the present application, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory controller, comprising: A processor including a plurality of cores; And A buffer memory storing a bootloader image for firmware update operation, Wherein the processor loads the bootloader image from the buffer memory into the memory of a core arbitrarily selected from the plurality of cores, receives a new firmware image from a host in response to the bootloader image running in the selected core, and uses the new firmware image to update the firmware image stored in the memory of each of the plurality of cores, wherein the bootloader image is not included in the firmware image stored in the memory of the selected core.

2. The memory controller according to claim 1, wherein the selected core dynamically allocates an address of a target memory area in the memory of the selected core into which the bootloader image is to be loaded, and runs the bootloader image loaded into the target memory area.

3. The memory controller according to claim 2, wherein the selected core updates the firmware image stored in the memory of each of the plurality of cores with the new firmware image received in response to the bootloader image being run, in parallel with processing requests received from the host.

4. The memory controller according to claim 3, wherein the selected core uses the new firmware image to update the firmware image stored in a memory area other than the target memory area in the memory of the selected core.

5. The memory controller according to claim 1, wherein before power-off, the new firmware image updated in the memory of each of the plurality of cores is stored in a memory device controlled by the memory controller.

6. The memory controller according to claim 1, wherein the buffer memory includes a volatile memory device.

7. A method of operating a memory controller, the memory controller including a plurality of cores and a buffer memory and controlling a memory device, the method comprising: Loading a bootloader image into the memory of a core arbitrarily selected from the plurality of cores, the bootloader image being stored in the buffer memory and provided for firmware update operation; Receiving a new firmware image from a host in response to the bootloader image running in the selected core; And Using the new firmware image to update the firmware image stored in the memory of each of the plurality of cores, Wherein the bootloader image is not included in the firmware image stored in the memory of the selected core.

8. The method according to claim 7, wherein loading the bootloader image includes: Dynamically allocating an address of a target memory area in the memory of the selected core into which the bootloader image is to be loaded; And Loading the bootloader image into the target memory area.

9. The method according to claim 8, wherein updating the firmware image comprises: In parallel with processing requests received from the host, update the firmware image stored in the memory of each of the plurality of cores using the new firmware image received in response to the bootloader image being run.

10. The method according to claim 9, wherein updating the firmware image comprises: Update the firmware image of the selected core using the new firmware image, the firmware image of the selected core being stored in a memory area other than the target memory area in the memory of the selected core.

11. The method according to claim 7, further comprising: Before power-off, store the new firmware image updated in the memory of each of the plurality of cores in the memory device.

12. The method according to claim 7, wherein the buffer memory comprises a volatile memory device.

13. The method according to claim 12, wherein the boot loader image is stored in the memory device, and the method further comprises: After power-on, load the bootloader image stored in the memory device into the buffer memory.

14. The method according to claim 7, wherein the buffer memory comprises a non-volatile memory device.

15. A storage device, comprising: A memory device; And A memory controller comprising a plurality of cores, wherein the memory controller loads a bootloader image for firmware update operation into the memory of a core arbitrarily selected from the plurality of cores, receives a new firmware image from the host in response to the bootloader image running in the selected core, and updates the firmware image stored in the memory of each of the plurality of cores using the new firmware image, wherein the bootloader image is not included in the firmware image stored in the memory of the selected core.

16. The storage device according to claim 15, wherein the memory controller dynamically allocates an address of a target memory area into which the bootloader image is to be loaded in the memory of the selected core, and runs the bootloader image loaded into the target memory area.

17. The storage device according to claim 16, wherein the memory controller, in parallel with processing requests received from the host, updates the firmware image stored in the memory of each of the plurality of cores using the new firmware image received in response to the bootloader image being run.

18. The storage device according to claim 16, wherein the memory controller updates the firmware image of the selected core using the new firmware image, the firmware image of the selected core being stored in a memory area other than the target memory area in the memory of the selected core.

19. The storage device according to claim 15, wherein the memory controller controls the memory device to store the new firmware image updated in the memory of each of the plurality of cores in the memory device before power-off.

20. The storage device according to claim 15, wherein the boot loader image is stored in the memory device, the boot loader image is loaded into the volatile memory device of the memory controller after power-on, and the boot loader image loaded into the volatile memory device is loaded into the memory of the selected kernel.

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