A wafer center positioning, wafer gap positioning and wafer positioning calibration method

Abstract

The application provides a wafer center positioning, wafer gap positioning and wafer positioning calibration method, which comprises the following steps: acquiring a wafer circumference image, performing binary processing on the image by using a deep learning semantic segmentation model, screening a contour line to obtain a wafer edge, acquiring a wafer gap image, performing binary processing on the image by using a deep learning semantic segmentation model, screening a contour line to obtain a wafer gap edge curve, then acquiring a wafer gap top edge, and fitting a wafer center and a gap center to complete wafer positioning. The positioning method based on deep learning semantic segmentation has high precision, does not require prior information, is highly automated, can effectively improve wafer positioning precision, and can accurately measure a wafer center and a gap.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically, to a method for wafer center positioning, wafer notch positioning, and wafer positioning calibration. Background Technology

[0002] Wafer positioning is a crucial step in the manufacturing and testing of integrated circuits. Since defect detection and dimensional measurement of integrated circuits require measurements to be taken at specific locations, it's essential to ensure these locations are within the field of view (FOV) of the measuring equipment. Therefore, wafer positioning is necessary. Specifically, this involves measuring the positions of the wafer's center and notch using a specific method, then calculating the wafer's rotation angle relative to the measuring instrument. This yields the coordinate transformation relationship between the wafer and the instrument, encompassing two steps: wafer center positioning and wafer notch positioning.

[0003] Currently, most wafer positioning methods use optical detectors such as CCDs as image acquisition devices. However, due to the large field of view (FOV) of these detectors, the positioning accuracy is not high. When subsequently using a smaller FOV to detect defects, positioning errors can cause defects to deviate from the detection equipment's field of view, ultimately leading to missed defects. For wafers with etched patterns, more accurate positioning can be achieved through these special patterns. However, for unetched wafers, it is impossible to obtain additional information for positioning calibration. Therefore, it is necessary to improve the accuracy of wafer center positioning and notch positioning. Summary of the Invention

[0004] This invention addresses the technical problems existing in the prior art by providing a method for wafer center positioning, wafer notch positioning, and wafer positioning calibration.

[0005] According to a first aspect of the present invention, a method for locating the center of a wafer is provided, comprising:

[0006] Obtain a wafer circumference image;

[0007] The wafer circumference image is binarized based on a deep learning semantic segmentation model to extract all contour lines in the wafer circumference image.

[0008] Select the wafer edge contour line from all contour lines;

[0009] Based on the wafer edge contour line, the wafer center coordinates are obtained by fitting.

[0010] Based on the above technical solution, the present invention can also be improved as follows.

[0011] Optionally, the step of filtering wafer edge contour lines from all contour lines includes:

[0012] Obtain the length of all contour lines and the width or height of the wafer circumference image;

[0013] The outlines that meet the following conditions are selected as the wafer edge outlines;

[0014] The ratio of the length of the outline to the width or height of the wafer circumference image is greater than 1 and less than 1.1.

[0015] Optionally, the extraction of contour features for each contour line includes:

[0016] Based on the x-coordinates and y-coordinates of all edge points on any contour line, as well as the width and height of the wafer circumference image, the dispersion of the edge points on any contour line is calculated.

[0017] Calculate the curvature of any contour line based on the horizontal and vertical coordinates of all edge points on the contour line and the second-order gradient of the contour line.

[0018] Based on the horizontal and vertical coordinates of all edge points on any contour line, a straight line equation is fitted. Based on the straight line equation, the sum of squared residuals of the straight line fitting is calculated as the degree to which the contour line approximates a straight line.

[0019] Accordingly, the step of filtering wafer edge contour lines from all contour lines based on the contour features of each contour line includes:

[0020] The score of any contour line is the sum of one or more combinations of the dispersion of the edge points on the contour line, the curvature of the contour line, and the degree to which the contour line is approximately straight.

[0021] The profile with the lowest score is used as the wafer edge profile.

[0022] Optionally, the step of fitting the wafer center coordinates based on the wafer edge contour line further includes:

[0023] The wafer edge contour line is cut into multiple edge segments;

[0024] Select multiple edge points on the multi-segment edge line;

[0025] Based on the selected edge points, the coordinates of the wafer center are obtained by fitting.

[0026] According to a second aspect of the present invention, a wafer notch positioning method is provided, comprising:

[0027] Obtain wafer notch images;

[0028] The wafer notch image is binarized based on a deep learning semantic segmentation model, and all contour lines in the wafer notch image are extracted.

[0029] Select the wafer notch edge curve from all the contour lines;

[0030] The top edge curve of the wafer notch is determined from the edge curve of the wafer notch;

[0031] Based on the top edge curve of the wafer notch, the coordinates of the wafer notch center are obtained by fitting.

[0032] Optionally, the step of filtering out wafer notch edge curves from all contour lines includes:

[0033] Extract the contour features of each contour line, wherein the contour features include any one or a combination of two of the contour line’s curvature and its approximate quadratic curve degree;

[0034] Based on the contour features of each contour line, wafer notch edge curves are selected from all contour lines.

[0035] Optionally, the extraction of contour features for each contour line includes:

[0036] Calculate the curvature of any given contour line based on the x and y coordinates of all edge points on the contour line and the second gradient of the contour line.

[0037] Based on the horizontal and vertical coordinates of all edge points on any contour line, a quadratic curve equation is fitted. Based on the quadratic curve equation, the sum of squared residuals of the quadratic curve fitting is calculated as the degree of approximation of the quadratic curve of any contour line.

[0038] Accordingly, based on the contour features of each contour line, wafer notch edge curves are selected from all contour lines, including:

[0039] The score of any contour line is the sum of one or two combinations of the curvature of any contour line and the degree of approximation of a quadratic curve of any contour line.

[0040] The profile with the lowest score is used as the wafer notch edge profile.

[0041] Optionally, determining the top edge curve of the wafer notch from the wafer notch edge curve includes:

[0042] Obtain the center point of all edge points of the wafer notch edge curve, and use the center point as a reference to cut off the wafer notch edge curve. Remove the edge portions on both sides of the wafer notch edge curve to obtain the top edge curve of the wafer notch.

[0043] Optionally, based on the top edge curve of the wafer notch, the coordinates of the wafer notch center are fitted, including:

[0044] Obtain all top edge points on the top edge curve of the wafer notch, construct multiple top edge point sets, and ensure that the top edge points contained in each top edge point set do not overlap;

[0045] For each edge point in the set of top edge points, the coordinates of the corresponding wafer notch center are fitted.

[0046] The final wafer notch center coordinates are obtained by averaging the coordinates of all wafer notch center coordinates.

[0047] According to a third aspect of the present invention, a wafer positioning calibration method is provided, comprising:

[0048] The wafer center coordinates are obtained based on the wafer center positioning method;

[0049] Based on the wafer notch positioning method, the center coordinates of the wafer notch are obtained;

[0050] Based on the coordinates of the wafer center and the coordinates of the wafer notch center, the wafer rotation angle is obtained, and the wafer positioning calibration is completed.

[0051] This invention provides a method for wafer center positioning, wafer notch positioning, and wafer positioning calibration. It acquires a wafer circumference image, performs binarization processing on the image using a deep learning semantic segmentation model, filters contour lines to obtain the wafer edge, acquires a wafer notch image, performs binarization processing on the image using a deep learning semantic segmentation model, filters contour lines to obtain the wafer notch edge curve, determines the top edge curve of the wafer notch, and fits the wafer center and notch center to complete wafer positioning. This invention's positioning method, based on deep learning semantic segmentation, offers high accuracy, requires no prior information, and is highly automated, effectively improving wafer positioning accuracy and enabling precise measurement of the wafer center and notch. Attached Figure Description

[0052] Figure 1 A flowchart of a wafer center positioning method provided by the present invention;

[0053] Figure 2 This is a schematic diagram of the wafer center fitting.

[0054] Figure 3 Flowchart of wafer notch positioning method;

[0055] Figure 4 A schematic diagram of obtaining the top of the wafer notch during coarse positioning of the wafer notch;

[0056] Figure 5This is a schematic diagram of the circular fitting of the wafer notch;

[0057] Figure 6 This is a schematic diagram of a wafer center positioning system provided by the present invention;

[0058] Figure 7 This is a schematic diagram of a wafer notch positioning system provided by the present invention;

[0059] Figure 8 A schematic diagram of a possible hardware structure of an electronic device provided by the present invention;

[0060] Figure 9 This is a schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention. Detailed Implementation

[0061] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0062] In the process of wafer centering and wafer notch positioning, the positioning accuracy obtained by measuring the wafer center and notch using optical detectors such as CCDs is not high. For wafers without patterns, since there are no special patterns on the wafer, it is impossible to recalibrate the positioning to obtain high-precision positioning as with patterned wafers. This invention proposes a wafer positioning method based on a deep learning semantic segmentation model, which improves the wafer positioning accuracy. High-magnification, high-resolution imaging equipment is typically used for wafer positioning, such as charged particle beam scanning imaging equipment (e.g., SEM, FIB-SEM, etc.) and AFM imaging equipment. For ease of explanation, this invention uses SEM images acquired by a scanning electron microscope as an example. It should be understood that SEM images are not intended to limit the scope of this invention.

[0063] Example 1

[0064] A method for locating the center of a wafer, see [link to relevant documentation]. Figure 1 The wafer center positioning method mainly includes the following steps:

[0065] S1, acquire the wafer circumference image.

[0066] In this embodiment of the invention, a scanning electron microscope (SEM) is used to scan the wafer to obtain a circumferential SEM image of the wafer. Subsequent processing is all based on the circumferential SEM image of the wafer.

[0067] S2, the wafer circumference image is binarized based on a deep learning semantic segmentation model to extract all contour lines in the wafer circumference image.

[0068] Understandably, when a wafer circumference SEM image is obtained through scanning, contour lines are extracted from it. Specifically, the wafer circumference SEM image is binarized, and all contour lines are extracted from the binarized image. This can be achieved by denoising the wafer SEM image, scaling the image size to the input size of a deep neural network (DNN) model, such as 512*512, and then binarizing the wafer SEM image using a deep learning semantic segmentation model. Based on the binarized wafer circumference SEM image, the wafer edge contour lines can be obtained.

[0069] The wafer circumference image is characterized by high noise, blurriness, and large variations in brightness and contrast. The edges of the wafer circumference image may contain defects or machine parts similar to the wafer texture. Traditional computer vision methods, which rely on low-level features such as pixels or texture extraction for image segmentation, struggle to accurately obtain the wafer edges. This invention utilizes a deep learning semantic segmentation model to perform binarized segmentation of the wafer circumference image. Because the deep semantic segmentation model extracts image features at different scales and semantic levels, the segmented edges are more accurate and smoother. Furthermore, the model exhibits high robustness and strong generalization ability, thereby improving the accuracy of wafer center localization.

[0070] In some embodiments, obtaining the wafer edge profile includes extracting all the profiles therein and filtering out the wafer edge profile from all the profiles.

[0071] As an example, the contour features of each contour line are obtained. The contour features include any one or more combinations of the length of the contour line, the dispersion of the edge points on the contour line, the curvature of the contour line, and the degree of approximation of the contour line as a straight line. Based on the contour features, the wafer edge contour lines are selected from all contour lines.

[0072] As an example, the length of all contour lines and the width or height of the wafer circumference image are obtained; if the ratio of the length of the contour line to the width or height of the wafer circumference image is greater than 1 and less than 1.1, then the contour line is selected as the wafer edge contour line.

[0073] That is, contour lines shorter than the width or height of the wafer circumference image are screened out; contour lines longer than the width or height of the wafer circumference image are screened out; the more discrete the edge points on the contour line are, the more curved the contour line is, and the less the contour line is approximately a straight line is screened out.

[0074] It is understandable that wafer circumference SEM images include wafer edges and equipment sections. Wafer edges may contain elongated defects, and equipment sections may exhibit distinct contour textures. These defects and textures appear in the binarized image, affecting the identification of wafer edge contours. Considering that wafer edges are smooth arcs, while defects or equipment textures are irregular, non-smooth curves with concavities and convexities, this invention proposes a contour line scoring method for screening wafer edges. The wafer edge contour line is approximately a straight line, and its length is similar to the width or height of the wafer circumference image. The designed scoring method evaluates and selects wafer edge contour lines based on at least one or a combination of two of the following three aspects: the discreteness of edge points, the curvature of the contour line, and the degree to which the contour line approximates a straight line. This scoring and screening method for obtaining wafer edge contour lines improves the model's generalization ability to wafers, equipment, and images of different imaging qualities (e.g., maintaining high accuracy for low signal-to-noise ratio image processing), thereby improving the ability and accuracy of extracting wafer edge contour lines.

[0075] As an example, the step of selecting wafer edge contour lines from all contour lines based on any one or more combinations of the dispersion of edge points on the contour line, the curvature of the contour line, and the degree of approximation of the contour line as a straight line includes: for any contour line, calculating the dispersion score of edge points on the contour line based on the maximum and minimum values ​​of the abscissa and ordinate of all edge points on the contour line, as well as the width and height of the wafer circumference image. d The curvature score of any given contour line is calculated based on the x and y coordinates of all edge points on that contour line and the second-order gradient of the contour line. c Based on the x and y coordinates of all edge points along any given contour line, a straight line equation is fitted. Then, based on this equation, the sum of squared residuals (SSE) of the fitted straight line is calculated. line As the degree to which any of the contour lines approximates a straight line; correspondingly, the step of selecting wafer edge contour lines from all contour lines based on the contour features of each contour line includes: using the dispersion score of the edge points on any of the contour lines as the basis. d Score for the curvature of any of the contour lines c And the degree of approximation of the straightness of any of the contour lines SSE line The sum of one or more combinations is used as the score for any one of the contour lines.

[0076] Optionally, based on any one of the dispersion of edge points on any contour line, the curvature of the contour line, and the degree of approximation to a straight line, taking the dispersion of edge points on the contour line as an example, the score of any contour line can be calculated. edge =Scored Score edge The contour line is scored; the contour line with the lowest score is taken as the wafer edge contour line.

[0077] Optionally, a score for any contour line is calculated based on any two or more combinations of the dispersion of edge points on the contour line, the curvature of the contour line, and the degree of approximation to a straight line. For example, using three combinations: Score edge =λ d Score d +λ c Score c +λ line SSE line ; where λ d , λ c , λ line Score d Score c and SSE line In this embodiment of the invention, λ is the weight. d , λ c , λ line All scores are set to 1. edge The contour line is scored; the contour line with the lowest score is taken as the wafer edge contour line.

[0078] Specifically, for all the contour lines extracted from the wafer circumference image in step S2, the wafer edge contour lines are selected by scoring. This is mainly based on three aspects: the dispersion of edge points on the contour lines, the curvature of the contour lines, and the degree to which the contour lines approximate straight lines.

[0079] Each contour line is composed of a series of points (x i ,y i The points are arranged in order of i = 1, ..., N. X and Y represent the set of all x-coordinates and the set of all y-coordinates of the point sequence, respectively. i Y i Let x and y be the coordinates of the i-th point on the contour line.

[0080] As an example, the discreteness score of edge points on the contour line. d It is obtained from formulas (1)-(3).

[0081] Gap x =MAX(X)-MIN(X) (1);

[0082] Where MAX(X) and MIN(X) are the maximum and minimum values ​​of X.

[0083] Gap y=MAX(Y)-MIN(Y) (2);

[0084] Where MAX(Y) and MIN(Y) are the maximum and minimum values ​​of Y.

[0085]

[0086] Where STD(X) is the standard deviation of X, STD(Y) is the standard deviation of Y, W and H are the width and height of the image, and Score d It measures the degree of dispersion of the contour line points in the x and y directions.

[0087] As an example, the curvature score of the contour line c It is obtained from formulas (4)-(10).

[0088]

[0089]

[0090]

[0091] Score t =-N / (T) x +T y (7);

[0092] Among them, T x T y The degree of curvature of the contour line in the x and y directions is measured by the number of inflection points that appear on the contour line.

[0093] g i =(Y i -Y i-1 ) / (X i -X i-1 (8);

[0094]

[0095] Score c =λ t Score t +λ g Score g (10);

[0096] Among them, g i Score is the second-order gradient of the contour line. g The curvature of the contour line is measured from the perspective of the second-order gradient. λ t , λ g Score t and Score gThe weight, λ t +λ g =1, preferably λ t , λ g All scores are set to 0.5; Score t The Score represents the degree of curvature of the contour line, measured by the changes in the x and y coordinates of all edge points on the contour line. g This indicates that the curvature of any given contour line is measured by the angle of its second-order gradient.

[0097] As an example, the sum of squared residuals of the straight-line fitting is obtained by formulas (11)-(12).

[0098]

[0099] in, These are the arithmetic mean of X and Y, respectively. This is the equation of the straight line obtained by fitting the line using the least squares method.

[0100]

[0101] Among them, SSE line The sum of squared residuals from the least-squares fit is used to represent the degree to which any given contour line approximates a straight line.

[0102] With Score d Score c and SSE line The score is obtained by combining any one or more of the three factors to determine the wafer circumference profile. edge For example, taking three combinations, the Score edge =λ d Score d +λ c Score c +λ line SSE line ,in,

[0103] Score c =λ t Score t +λ g Score g So, the score for the wafer circumference profile. edge The expression is:

[0104] Score edge =λ d Score d +λ t Score t +λ gScore g +λ line SSE line (13);

[0105] Where, λ d , λ t , λ g , λ line Score d Score t Score g and SSE line In this embodiment of the invention, λ is the weight. d , λ c , λ line Take 1, λ t +λ g =1, preferred, λ t , λ g All scores are set to 0.5. edge This is a scoring formula for the circumferential profile of a wafer.

[0106] For all contour lines extracted from the wafer circumference SEM image, each contour line can be scored using any of the methods described above to obtain a corresponding score. The contour line with the lowest score is then taken as the wafer edge contour line. This method can accurately extract wafer edge contour lines, improving the accuracy of wafer edge contour line recognition.

[0107] S3, Based on the wafer edge contour line, the wafer center is obtained by fitting.

[0108] Optionally, the step of fitting the wafer center coordinates based on the wafer edge contour line includes: obtaining at least three edge point coordinates from the wafer edge contour line, and determining the wafer center coordinates based on the at least three edge point coordinates.

[0109] As an example, the step of fitting the wafer center coordinates based on the wafer edge contour line includes: cutting the wafer edge contour line into multiple edge line segments, and obtaining a score for each edge line segment using the same method as evaluating each contour line. edge From this, multiple optimal sub-edge lines are determined. For example, taking a wafer edge profile cut into 10 sub-edge lines, 5 of these sub-edge lines are selected based on their scores. edge The lowest is the optimal sub-edge line; edge points are selected from the multiple optimal sub-edge lines. For example, two edge points are selected from each of the five selected optimal sub-edge lines, for a total of ten edge points; based on the selected edge points, the circular shape of the wafer is fitted to obtain the wafer center coordinates.

[0110] Optionally, multiple wafer circumference images are acquired, preferably at least three wafer circumference images. These images are then processed using the method described above to extract corresponding edge points, thereby fitting the circular shape of the wafer and obtaining the wafer center coordinates. Taking the acquisition of three wafer circumference images as an example, the three wafer circumference images can be evenly distributed on the wafer circumference, meaning the central angle between the wafer circumference positions corresponding to the three wafer images and the wafer center is approximately 120 degrees. Optionally, the minimum central angle between the wafer circumference positions corresponding to the three wafer images and the wafer center is 90 degrees.

[0111] Understandably, for the wafer edge contour line determined in S2, this step divides the wafer edge contour line into multiple sub-edge lines. For example, the wafer edge contour line is divided into multiple equal sub-edge lines, and each sub-edge line is scored. The optimal sub-edge line is selected, i.e., the score. edge The lowest multi-segment sub-edge line. The scoring criteria for the sub-edge line are the same as those for each contour line, and will not be repeated here.

[0112] For each optimal sub-edge segment, edge points are selected. For example, several edge points are selected from each optimal sub-edge segment. Based on all selected edge points, the circular shape of the wafer is fitted. (See [reference needed]). Figure 2 This yields the coordinates of the wafer's center.

[0113] Example 2

[0114] A wafer notch positioning method, see [link to relevant documentation] Figure 3 The wafer notch positioning method mainly includes the following steps:

[0115] S1', acquire wafer notch image;

[0116] As an example, an optical image of the wafer notch can be obtained first, and the position of the top of the wafer notch can be determined based on the optical image of the wafer notch.

[0117] Understandably, in order to improve the accuracy of wafer notch positioning, the wafer notch is first coarsely positioned, and then finely positioned based on the coarse positioning results. The purpose of coarse positioning is mainly to obtain the top position of the wafer notch.

[0118] The coarse positioning steps mainly include: acquiring an optical image of the wafer notch using an optical detector; performing denoising preprocessing on the optical image of the wafer notch; and binarizing the optical image of the wafer notch based on the denoised preprocessed image, for example, using the Otsu method (OSTU), to extract all contour lines from the binarized optical image of the wafer notch. All contour lines are then comprehensively evaluated from two aspects: the degree of curve curvature and the degree of approximation to a quadratic curve. Contour lines are then filtered to obtain the wafer notch edge curve.

[0119] Understandably, because optical detectors can only scan objects within a large field of view, the final wafer location is not precise enough. Scanning electron microscopes (SEMs), on the other hand, can scan wafers within a small field of view. Therefore, this embodiment of the invention uses a scanning electron microscope (SEM) to scan the wafer notch and obtain a wafer notch SEM image.

[0120] For the selected wafer notch edge curves, the highest point on the vertical axis of the wafer notch edge curve is selected as the wafer notch top position. The obtained wafer notch top position is shown in [reference needed]. Figure 4 Because the rotation angle of the wafer notch is small, the accuracy of the selected point can meet the accuracy requirements of the coarse positioning of the wafer notch, that is, to ensure that the top of the wafer notch appears in the SEM image in the next step of fine positioning of the wafer notch.

[0121] Optionally, a wafer notch image can be obtained based on the wafer notch top position obtained during the wafer notch coarse positioning process.

[0122] Understandably, based on the coarsely located wafer notch tip position, a scanning electron microscope (SEM) is used to scan the wafer notch SEM image. The coarsely located wafer notch tip appears in the wafer notch SEM image. Alternatively, besides the above method, other methods can be used to obtain wafer SEM images. For example, based on the roughly determined positional relationship between the wafer notch and the scanning device when the wafer is placed on the stage, a low-magnification scan image can be obtained first, capturing the wafer notch. Then, based on the notch's position in the low-magnification scan image, the magnification of the scanning device can be continuously adjusted to gradually increase the magnification, ultimately obtaining a high-magnification, high-resolution scan image of the wafer notch.

[0123] S2': The wafer notch image is binarized based on a deep learning semantic segmentation model, and all contour lines in the wafer notch image are extracted.

[0124] Understandably, denoising the wafer notch SEM image involves scaling the image size to the input size of a deep neural network (DNN) model, such as 512*512, binarizing the wafer notch SEM image based on a deep learning semantic segmentation model, and extracting all contour lines from the binarized wafer notch SEM image.

[0125] This invention uses a deep learning semantic segmentation model to perform binarization segmentation on wafer notch SEM images. Because the deep semantic segmentation model extracts image features at different scales and semantic levels, the segmented edges are more accurate and smoother. In addition, the model has high robustness and strong generalization ability, which improves the accuracy of wafer notch edge curve recognition.

[0126] S3' filters out wafer notch edge curves from all contour lines.

[0127] As an example, the step of filtering out wafer notch edge curves from all contour lines includes: extracting contour features of each contour line, wherein the contour features include any one or a combination of the curvature of the contour line and the degree of approximation of a quadratic curve; and filtering out wafer notch edge curves from all contour lines based on the contour features of each contour line.

[0128] It is understood that the outline of a wafer notch approximates a quadratic curve. The scoring method for the wafer notch outline in this embodiment of the invention evaluates and selects wafer notch outlines based on the curvature of the curve and the degree of approximation to a quadratic curve. This scoring and selection method for obtaining wafer edges can improve the model's generalization ability to wafers, equipment, and images of different imaging qualities, thereby improving the positioning accuracy of the wafer notch.

[0129] As an example, the extraction of contour features for each contour line includes: calculating the curvature score of any contour line based on the range of values ​​of the horizontal and vertical coordinates of all edge points on any contour line and the second-order gradient of the contour line. c Based on the x and y coordinates of all edge points along any given contour line, a quadratic curve equation is fitted. Based on this equation, the sum of squared residuals (SSE) of the fitted quadratic curve is calculated. curve As an approximate quadratic curve degree for any of the contour lines; correspondingly, based on the contour features of each contour line, the wafer notch edge curve is selected from all contour lines, including: the curvature score of any of the contour lines. c And the degree of approximate quadratic curve SSE of any of the aforementioned contour lines curve The sum of one or two combinations is used as the score for any of the contour lines; the contour line with the lowest score is used as the wafer notch edge contour line.

[0130] Specifically, for each contour line extracted from the wafer notch SEM image, its curvature and approximate quadratic curve degree are calculated, where the curvature score of the contour line is... c It can be measured using formula (10). For calculating the degree of approximation to a quadratic curve, since the wafer notch curve approximates a quadratic curve, quadratic curve fitting is performed based on the edge points on the contour line:

[0131] y curve =w0+w1x+w2x 2 (14);

[0132] The above formula is the fitting formula for the wafer notch curve, obtained by fitting using the least squares method.

[0133]

[0134] Among them, SSE curve The sum of squared residuals of the quadratic equation obtained by least-squares fitting is used as the approximation of the quadratic curve.

[0135] Score notch =λ c Score c +λ curve SSE curve (16);

[0136] Where, λ c , λ curve Score c and SSE curve Weights, Score notch This is the scoring formula for the wafer notch profile. In this embodiment of the invention, λ c , λ curve All are set to 1.

[0137] For each wafer notch contour line, score it according to formula (16) to obtain the corresponding score, and take the contour line with the lowest score as the wafer notch edge curve.

[0138] In another embodiment, either the curvature of the contour line or the degree of approximation to a quadratic curve can be selected as the scoring criterion to filter out the wafer notch edge curve from all contour lines. Using the degree of approximation to a quadratic curve as the scoring criterion, the degree of approximation to a quadratic curve (SSE) of any contour line is obtained using the same method described above. curve The score at this point is Score notch =SSE curve The contour line with the lowest score is taken as the wafer notch edge curve.

[0139] Using the curvature of the contour line as the scoring criterion, the curvature score of any contour line is obtained using the same method described above. c The score at this point is Score notch =Score c The contour line with the lowest score is used as the wafer notch edge curve.

[0140] S4', determine the top edge curve of the wafer notch from the wafer notch edge curve.

[0141] The wafer notch edge curve is obtained through step S3' above. This step obtains the center point of all edge points of the wafer notch edge curve. Using the center point as a reference, the wafer notch edge curve is truncated, and the edge portions on both sides of the wafer notch edge curve are removed to obtain the top edge curve of the wafer notch. For example, using the center point of all edge points as a reference, the wafer notch edge curve is symmetrically truncated on the left and right sides, and the symmetrical edge portions on both sides are removed, leaving only the curve portion with the center point as the reference, which is the top edge curve of the notch. Figure 5 As shown in the figure, the dashed box represents the top edge curve of the obtained wafer notch.

[0142] S5' is obtained by fitting the center coordinates of the wafer notch based on the top edge curve of the wafer notch.

[0143] As an example, the method of fitting the wafer notch center coordinates based on the top edge curve of the wafer notch includes: obtaining all top edge points on the top edge curve, constructing multiple sets of top edge points, where the top edge points in each set do not overlap, fitting the corresponding wafer notch center coordinates to the edge points in each set, and averaging all the wafer notch center coordinates to obtain the final wafer notch center coordinates. Figure 5 As shown, based on the top edge curve of the wafer top notch within the dashed box, a corresponding circle is fitted, and the center coordinates of this circle are the center coordinates of the wafer notch. For example... Figure 5 The fitting results for only one set of top edge points are shown.

[0144] Understandably, due to potential defects at the wafer notch, the wafer notch contour obtained after image binarization may be uneven and not smooth enough, leading to inaccurate fitted circles. This invention removes the edge portion of the notch edge curve, selects multiple sets of top edge points based on the top edge curve of the wafer notch, fits each set separately, and obtains multiple wafer notch center coordinates. Finally, the average of all center coordinates in the set of center points is taken to obtain the wafer notch center coordinates. This method increases the accuracy and robustness of the method in finding the wafer notch center.

[0145] Example 3

[0146] A wafer positioning and calibration method requires obtaining the coordinates of the wafer center and the center of the wafer notch. The wafer center coordinates can be obtained using the method of Example 1, and the wafer notch center coordinates can be obtained using the method of Example 2.

[0147] Based on the coordinates of the wafer center and the center of the wafer notch, the wafer rotation angle is calculated, thereby completing the wafer positioning calibration.

[0148] By using the coordinates of the wafer center and the center of the wafer notch, the angle between the line connecting the two center coordinates and the y-axis of the wafer stage coordinate system can be obtained. This angle is the wafer rotation angle, which allows adjustment of the wafer's position and angle to complete wafer positioning and calibration.

[0149] Example 4

[0150] A wafer center positioning system, see Figure 6 The wafer center positioning system includes a first acquisition module 601, a first extraction module 602, a first screening module 603, and a first fitting module 604.

[0151] The first acquisition module 601 is used to acquire a wafer circumference image; the first extraction module 602 is used to perform binarization processing on the wafer circumference image based on a deep learning semantic segmentation model to extract all contour lines in the wafer circumference image; the first filtering module 603 is used to filter out the wafer edge contour lines from all contour lines; and the first fitting module 604 is used to fit the wafer center coordinates based on the wafer edge contour lines.

[0152] It is understood that the wafer center positioning system provided by the present invention corresponds to the wafer center positioning method provided in the foregoing embodiments. The relevant technical features of the wafer center positioning system can be referred to the relevant technical features of the wafer center positioning method, and will not be repeated here.

[0153] Example 5

[0154] A wafer notch positioning system, see Figure 7 The wafer notch positioning system includes a second acquisition module 701, a second extraction module 702, a second screening module 703, a determination module 704, and a second fitting module 705.

[0155] The second acquisition module 701 is used to acquire a wafer notch image; the second extraction module 702 is used to binarize the wafer notch image based on a deep learning semantic segmentation model and extract all contour lines in the wafer notch image; the second filtering module 703 is used to filter out the wafer notch edge curve from all contour lines; the determination module 704 is used to determine the top edge curve of the wafer notch from the wafer notch edge curve; and the second fitting module 705 is used to fit the wafer notch center coordinates based on the top edge curve of the wafer notch.

[0156] It is understood that the wafer notch positioning system provided by the present invention corresponds to the wafer notch positioning method provided in the foregoing embodiments. The relevant technical features of the wafer notch positioning system can be referred to the relevant technical features of the wafer notch positioning method, and will not be repeated here.

[0157] Example 6

[0158] Please see Figure 8 , Figure 8 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 8 As shown, an embodiment of the present invention provides an electronic device 800, including a memory 810, a processor 820, and a computer program 811 stored in the memory 810 and executable on the processor 820. When the processor 820 executes the computer program 811, it implements the wafer center positioning method of Embodiment 1, the wafer notch positioning method of Embodiment 2, or the wafer positioning calibration method of Embodiment 3.

[0159] Example 7

[0160] Please see Figure 9 , Figure 9 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 9 As shown, this embodiment provides a computer-readable storage medium 900, on which a computer program 911 is stored. When the computer program 911 is executed by a processor, it implements the wafer center positioning method of Embodiment 1, the wafer notch positioning method of Embodiment 2, or the wafer positioning calibration method of Embodiment 3.

[0161] This invention provides a method for wafer center positioning, wafer notch positioning, and wafer positioning calibration. The method involves acquiring a SEM image of the wafer edge, binarizing the image using a deep learning semantic segmentation model, obtaining the wafer edge by selecting contour lines through scoring, and fitting the wafer center using the least squares method. For coarse positioning of the wafer notch, an optical detector is used. The result of the coarse positioning is used to acquire a SEM image of the wafer notch, which is then binarized again using the deep learning semantic segmentation model. The contour lines are then selected by scoring to obtain the wafer notch edge curve, and the wafer notch center is fitted to complete fine positioning of the wafer notch. Finally, the wafer positioning is calibrated based on the acquired wafer center and wafer notch center. This invention discloses a wafer positioning method based on scanning electron microscopy (SEM) and deep learning, which can accurately measure the wafer center and notch. It improves the accuracy of wafer positioning by two orders of magnitude, from 100 μm to 5 μm, and can automatically measure the wafer center and notch without human intervention or other prior information.

[0162] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0163] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0164] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0165] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0166] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0167] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0168] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for locating the center of a wafer, characterized in that, include: Obtain a wafer circumference image; The wafer circumference image is binarized based on a deep learning semantic segmentation model to extract all contour lines in the wafer circumference image. Select the wafer edge contour line from all contour lines; Based on the wafer edge contour line, the wafer center coordinates are fitted to obtain the wafer center coordinates; The step of filtering out wafer edge contour lines from all contour lines includes: Extract the contour features of each contour line, which include any one or more combinations of the following: the length of the contour line, the dispersion of the edge points on the contour line, the curvature of the contour line, and the degree to which the contour line is approximately straight. Based on the contour features of each contour line, wafer edge contour lines are selected from all contour lines. The extraction of contour features for each contour line includes: Based on the x-coordinates and y-coordinates of all edge points on any contour line, as well as the width and height of the wafer circumference image, the dispersion of the edge points on any contour line is calculated. The process of selecting wafer edge contour lines from all contour lines based on the contour features of each contour line includes: The score of any contour line is the sum of one or more combinations of the dispersion of the edge points on the contour line, the curvature of the contour line, and the degree to which the contour line is approximately straight. The profile with the lowest score is used as the wafer edge profile.

2. The wafer center positioning method according to claim 1, characterized in that, The process of filtering wafer edge contour lines from all contour lines includes: Obtain the length of all contour lines and the width or height of the wafer circumference image; The contour lines that meet the following conditions are selected as the wafer edge contour lines: The ratio of the length of the outline to the width or height of the wafer circumference image is greater than 1 and less than 1.

1.

3. The wafer center positioning method according to claim 1, characterized in that, The extraction of contour features for each contour line includes: Calculate the curvature of any contour line based on the horizontal and vertical coordinates of all edge points on the contour line and the second-order gradient of the contour line. Based on the x and y coordinates of all edge points on any given contour line, a straight line equation is fitted. Based on the straight line equation, the sum of squared residuals of the fitted straight line is calculated as the degree to which the given contour line approximates a straight line.

4. The wafer center positioning method according to claim 1, wherein wafer center coordinates are obtained by fitting based on the wafer edge contour line, comprising: The wafer edge contour line is cut into multiple edge segments; Select multiple edge points on the multi-segment edge line; Based on the selected edge points, the coordinates of the wafer center are obtained by fitting.

5. A wafer notch positioning method, characterized in that, include: Obtain wafer notch images; The wafer notch image is binarized based on a deep learning semantic segmentation model, and all contour lines in the wafer notch image are extracted. Select the wafer notch edge curve from all the contour lines; The top edge curve of the wafer notch is determined from the edge curve of the wafer notch; Based on the top edge curve of the wafer notch, the coordinates of the wafer notch center are obtained by fitting. The step of selecting wafer notch edge curves from all contour lines includes: Extract the contour features of each contour line, wherein the contour features include any one or a combination of two of the contour line’s curvature and its approximate quadratic curve degree; Based on the contour features of each contour line, the wafer notch edge curve is selected from all contour lines. Determining the top edge curve of the wafer notch from the wafer notch edge curve includes: Obtain the center point of all edge points of the wafer notch edge curve, and use the center point as a reference to cut off the wafer notch edge curve. Remove the edge portions on both sides of the wafer notch edge curve to obtain the top edge curve of the wafer notch.

6. The wafer notch positioning method according to claim 5, characterized in that, The extraction of contour features for each contour line includes: Calculate the curvature of any given contour line based on the x and y coordinates of all edge points on the contour line and the second gradient of the contour line. Based on the horizontal and vertical coordinates of all edge points on any contour line, a quadratic curve equation is fitted. Based on the quadratic curve equation, the sum of squared residuals of the quadratic curve fitting is calculated as the degree of approximation of the quadratic curve of any contour line. Accordingly, based on the contour features of each contour line, wafer notch edge curves are selected from all contour lines, including: The score of any contour line is the sum of one or two combinations of the curvature of any contour line and the degree of approximation of a quadratic curve of any contour line. The profile with the lowest score is used as the wafer notch edge profile.

7. The wafer notch positioning method according to claim 5, characterized in that, Based on the top edge curve of the wafer notch, the coordinates of the wafer notch center are fitted, including: Obtain all top edge points on the top edge curve of the wafer notch, construct multiple top edge point sets, and ensure that the top edge points contained in each top edge point set do not overlap; For each edge point in the set of top edge points, the coordinates of the corresponding wafer notch center are fitted. The final wafer notch center coordinates are obtained by averaging the coordinates of all wafer notch center coordinates.

8. A wafer positioning and calibration method, characterized in that, The calibration method includes: Based on the wafer center positioning method according to any one of claims 1-4, the coordinates of the wafer center are obtained; Based on the wafer notch positioning method according to any one of claims 5-7, the center coordinates of the wafer notch are obtained; Based on the coordinates of the wafer center and the coordinates of the wafer notch center, the wafer rotation angle is obtained, and the wafer positioning calibration is completed.

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