A method and device for manufacturing a multi-size metal gate

Abstract

The embodiment of the present application discloses a method and device for manufacturing a multi-sized metal gate, the method comprising: forming gate trenches of at least two polysilicon gates on a substrate structure based on a polysilicon gate process, the original size of the gate trench being larger than the target size of the metal gate, the target size being the size for filling a metal filler; depositing a thin film layer on the inner sidewall of the gate trench according to the target size, the thin film layer being used to fill the gate trench, reducing the original size of at least two gate trenches to the target size, wherein different gate trenches correspond to different target sizes; filling the metal filler into at least two gate trenches to form a metal gate of the target size. The method provided by the present application does not require the generation of polysilicon metal gates of different sizes, and can achieve batch production, thereby improving the manufacturing efficiency of multi-sized metal gates.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method and device for manufacturing a multi-sized metal gate. Background Art

[0002] The gate is a polarity in the field effect tube, a mesh or spiral electrode composed of metal filaments. In the semiconductor manufacturing process of field effect tubes, the use of metal gate technology can reduce the leakage of field effect tubes by several times, so that power consumption can be well controlled. Moreover, if the power consumption is the same, the performance can be greatly improved in theory.

[0003] The existing technology is mainly based on the traditional polysilicon gate (poly gate) process, which removes polysilicon (poly) after forming the poly gate and fills it with metal materials. However, the traditional poly gate process cannot control the gate size. Due to the limitations of the photolithography process, the minimum size of the gate at the advanced process node is designed according to a fixed width and space, and cannot be flexibly set according to different devices. Summary of the invention

[0004] The embodiment of the present application provides a method and device for manufacturing a multi-size metal gate. The technical solution is as follows:

[0005] In one aspect, a method for manufacturing a multi-size metal gate is provided, the method comprising:

[0006] Forming at least two gate trenches of polysilicon gates on the substrate structure based on a polysilicon gate process, wherein the original size of the gate trench is larger than the target size of the metal gate, and the target size is the size for filling the metal filler;

[0007] Depositing a thin film layer on the inner sidewall of the gate trench according to the target size, wherein the thin film layer is used to fill the gate trench, and reduce the original size of at least two gate trenches to the target size, wherein different gate trenches correspond to different target sizes;

[0008] Filling the at least two gate trenches with metal fillers to form the metal gate of the target size.

[0009] Specifically, the substrate structure includes a first gate trench and a second gate trench, which are used to generate a first metal gate and a second metal gate respectively; and depositing a thin film layer on the inner sidewall of the gate trench according to the target size includes:

[0010] Depositing a first thin film layer on the inner sidewalls of the first gate trench and the second gate trench by atomic layer deposition technology; a first film size of the first thin film layer is a difference between the original size and the first target size, and the first target size is a gate size corresponding to the first metal gate;

[0011] A first photoresist layer is generated in the first gate region of the first gate trench, wherein the area covered by the first photoresist layer is a first photoresist protection area, and the first photoresist protection area is used to protect the first thin film layer in the first gate region, wherein the second gate region of the second gate trench not covered by the first photoresist layer is a first photoresist reserved area;

[0012] Etching the first thin film layer in the first photoresist reserved area;

[0013] removing the first photoresist layer by plasma ashing technology;

[0014] All gate trenches are subjected to chemical mechanical polishing and ground to a target height, wherein the metal gates on the substrate structure have the same target height.

[0015] Specifically, the substrate structure further includes a third gate trench; and depositing a thin film layer on the inner sidewall of the gate trench according to the target size includes:

[0016] Depositing a second thin film layer on the inner sidewalls of the first gate trench, the second gate trench, and the third gate trench by atomic layer deposition technology, wherein a second film size of the second thin film layer is a difference between the first target size and the second target size, and the second target size is a gate size corresponding to the second metal gate;

[0017] Generating a second photoresist layer in the first gate region of the first gate trench, wherein the second photoresist layer covers an area as a second photoresist protection area, and the second photoresist protection area is used to protect the second thin film layer in the first gate region;

[0018] Etching the second thin film layer in a second photoresist reserved area, wherein the second photoresist reserved area includes the second gate area and the third gate area of ​​the third gate trench;

[0019] removing the second photoresist layer by plasma ashing technology;

[0020] Depositing a third thin film layer on the inner sidewalls of the first gate trench, the second gate trench and the third gate trench by atomic layer deposition technology, wherein a third thin film size of the third thin film layer is a difference between the second target size and the original size;

[0021] Generating a third photoresist layer in the first gate region and the second gate region of the second gate trench, wherein the third photoresist layer covers an area that is a third photoresist protection area;

[0022] Etching the third thin film layer in a third photoresist reserved area, wherein the third photoresist reserved area includes the first gate area;

[0023] removing the third photoresist layer by plasma ashing technology;

[0024] All gate trenches are subjected to chemical mechanical polishing and ground to a target height, wherein the metal gates on the substrate structure have the same target height.

[0025] Specifically, the method of forming at least two gate trenches of polysilicon gates on a substrate structure based on a polysilicon gate process includes:

[0026] generating the at least two polysilicon gates on the substrate structure according to the target size of the metal gate;

[0027] Generating a dielectric layer outside the at least two polysilicon gates and on the substrate structure;

[0028] Performing a planarization process on the dielectric layer to obtain a first grinding surface, wherein the first grinding surface includes the polysilicon gate;

[0029] The exposed polysilicon material is removed to form the at least two gate trenches.

[0030] Specifically, the dielectric layer is a silicon oxide layer, and the thin film layer includes at least one of a silicon carbide thin film layer, a silicon nitride thin film layer and a silicon carbonitride thin film layer.

[0031] Specifically, the step of depositing a first thin film layer on the inner sidewalls of the first gate trench and the second gate trench by using an atomic layer deposition technique includes:

[0032] The first precursor and the second precursor of the first thin film layer are adsorbed on the inner wall respectively, and an adsorption reaction occurs, wherein the adsorption reaction is used to generate the first thin film layer on the inner wall, wherein the first precursor and the second precursor are gases constituting elements of the first thin film layer.

[0033] Specifically, the adsorption reaction includes:

[0034] A plasma of silane and ammonia is formed by glow discharge, and the first thin film layer is deposited on the inner sidewalls of the first gate trench and the second gate trench by the plasma, wherein the reaction temperature of the plasma is 350°C.

[0035] On the other hand, a device for manufacturing a multi-size metal gate is provided, the device comprising:

[0036] A trench generation module, used for forming at least two gate trenches of polysilicon gates on the substrate structure based on a polysilicon gate process, wherein the original size of the gate trench is larger than the target size of the metal gate, and the target size is the size for filling the metal filler;

[0037] a thin film layer generating module, used for depositing a thin film layer on the inner sidewall of the gate trench according to the target size, wherein the thin film layer is used for filling the gate trench, and reducing the original size of at least two gate trenches to the target size, wherein different gate trenches correspond to different target sizes;

[0038] The metal gate generation module is used to fill the at least two gate trenches with metal fillers to form the metal gate of the target size.

[0039] On the other hand, a computer device is provided, comprising a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method for manufacturing a multi-sized metal gate as described in the above aspect.

[0040] The beneficial effects of the technical solution provided by the embodiment of the present application include at least: by forming at least two gate trenches of polysilicon gates on the substrate structure, a thin film layer is subsequently deposited on the inner sidewall of the gate trench according to the target size of each metal gate, so as to reduce the original size of the gate trench to the target size, thereby forming metal gates of different target sizes. By depositing a thin film layer on the inner sidewall, metal gates of multiple sizes can be manufactured. Compared with the prior art method of only generating polysilicon gates according to the target size of the metal gate, the present application does not need to generate polysilicon metal gates of different sizes, and can achieve batch production, thereby improving the manufacturing efficiency of multi-sized metal gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of generating a polysilicon gate provided by an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of generating a metal gate provided in an embodiment of the present application;

[0043] Figure 3 is a flow chart of a method for manufacturing a multi-sized metal gate provided by an embodiment of the present application;

[0044] Figure 4 is a flow chart of a method for manufacturing a multi-sized metal gate provided by another embodiment of the present application;

[0045] Figure 5 is a schematic diagram of generating a first thin film layer provided in an embodiment of the present application;

[0046] Figure 6 is a schematic diagram of generating a first photoresist layer provided in an embodiment of the present application;

[0047] Figure 7 is a schematic diagram of removing the first thin film layer in the first photoresist retention area provided by an embodiment of the present application;

[0048] Figure 8 is a schematic diagram of etching the first thin film layer and removing the first photoresist layer provided in an embodiment of the present application;

[0049] Fig. 9 is a schematic diagram of generating a multi-sized metal gate provided by an embodiment of the present application;

[0050] Fig.10 is a flow chart of a method for manufacturing a multi-sized metal gate provided by another embodiment of the present application;

[0051] Fig.11 is a schematic diagram of etching the second thin film layer provided by another embodiment of the present application;

[0052] Fig.12 is a schematic diagram of depositing a third thin film layer provided by another embodiment of the present application;

[0053] Fig.13 is a schematic diagram of generating a multi-sized metal gate provided by another embodiment of the application;

[0054] Fig.14 This is a structural block diagram of a device for manufacturing multi-size metal gates provided in one embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0056] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0057] Grid: The grid is a mesh or spiral electrode composed of metal filaments. One or more electrodes with a mesh or spiral shape arranged between the anode and the cathode in a multipolar electron tube play the role of controlling the electric field strength on the cathode surface to change the cathode emission of electrons or capture secondary emission electrons. The grid can be thought of as a switch that controls a physical gate. This grid can allow or block the flow of electrons by creating or eliminating a channel between the source and the drain. If affected by an external voltage, the electron flow will flow from the source to the drain.

[0058] In the prior art, based on the traditional polysilicon gate process, polysilicon is removed after the poly gate is formed, and metal materials are filled in to prepare it. However, the traditional poly gate process cannot control the gate size. Once the gate size is fixed after etching, it will no longer change. Due to the limitations of the photolithography process, the minimum size of the gate at advanced process nodes is designed according to a fixed width and space, and cannot be flexibly set according to different devices. In some multi-size metal gate devices and manufacturing processes, it is impossible to improve manufacturing efficiency.

[0059] like Figure 1 As shown, a polysilicon gate 110 is formed on a substrate structure 120 by conventional poly gate process technology, and the size of the polysilicon gate 120 is determined according to the target size of the metal gate to be finally manufactured. For example, if a metal gate with a target size of 40nm is required to be manufactured, the width of the polysilicon gate 110 is 40nm. After the polysilicon gate 110 is formed, a first insulating layer 130 needs to be formed on the outside of the polysilicon gate 110. In addition, a second insulating layer 140 needs to be generated on the outside of the first insulating layer 130 and above the substrate structure 120. A dielectric layer 150 of the metal gate needs to be generated on the outside of the second insulating layer 140. The outer layers of the first insulating layer 130 and the second insulating layer 140 are used to separate the metal gate and the dielectric layer 150 to prevent electrical breakdown and leakage due to the quantum tunneling effect.

[0060] like Figure 2 As shown, after the first insulating layer 130, the second insulating layer 140 and the dielectric layer 150 are formed, the previously formed polysilicon gate needs to be removed to form a gate trench. Then, the gate trench is filled with a metal filler 160. Finally, the metal gate is polished according to the target height of the metal gate to obtain the metal gate. Figure 2 The target size of the metal gate in the method is the size of the polysilicon metal gate or the size of the gate trench. In other words, the method can only design the metal gate according to the target size of the metal gate, and for multi-size metal gates, batch production cannot be achieved, and the preparation efficiency is low.

[0061] Figure 3: is a flow chart of a method for manufacturing a multi-size metal gate provided in an embodiment of the present application, which specifically includes the following steps:

[0062] Step 301 , forming at least two gate trenches of polysilicon gates on a substrate structure based on a polysilicon gate process, wherein an original size of the gate trench is larger than a target size of a metal gate, and the target size is a size for filling a metal filler.

[0063] In the scenario of preparing multi-size metal gates, in order to improve the production efficiency, when generating polysilicon metal gates, the gate size of the polysilicon metal gate is directly designed according to the target size of the metal gate. For example, for the production process of the same batch of wafers, the metal gate with the largest target size is used as the benchmark to generate a polysilicon metal gate of uniform size. Assuming that the target size of metal gate A to be produced is 50nm, and the target size of metal gate B is 30nm, the original size of the generated polysilicon metal gate is uniformly set to 50nm, or set to above 50nm. Then, the metal gate is generated according to the target size of different metal gates. The target size of the metal gate indicates the size of the metal filler that needs to be filled in the end, that is, the size of the gate finally generated.

[0064] Step 302 , depositing a thin film layer on the inner sidewall of the gate trench according to the target size, the thin film layer is used to fill the gate trench, and reduce the original size of at least two gate trenches to the target size, wherein different gate trenches correspond to different target sizes.

[0065] After the gate trench is generated, a thin film layer is deposited on the inner sidewall of the corresponding gate trench according to the target size of different metal gates. The thickness of the thin film layer depends on the difference between the original size and the target size. After adding the thin film layer, the original size of the trench can be reduced to the target size. For two adjacent gate trenches, the target metal gate is deposited with a thin film layer according to the specific target size, and the other adjacent metal gate can be reduced to the target size by first depositing and then clearing.

[0066] Step 303: Fill at least two gate trenches with metal fillers to form metal gates of target sizes.

[0067] When the original sizes of different gate trenches are reduced to target sizes, metal fillers can be filled into the gate trenches of different target sizes. The metal fillers are used to generate metal gates. The metal fillers include metal mixtures such as silicon and titanium.

[0068] In summary, in the embodiment of the present application, at least two gate trenches of polysilicon gates are formed on the substrate structure, so that a thin film layer can be subsequently deposited on the inner sidewall of the gate trench according to the target size of each metal gate, so as to reduce the original size of the gate trench to the target size, thereby forming metal gates of different target sizes. By depositing a thin film layer on the inner sidewall, metal gates of multiple sizes can be manufactured. Compared with the prior art method of only generating polysilicon gates according to the target size of the metal gate, the present application does not need to generate polysilicon metal gates of different sizes, and can achieve batch production, thereby improving the manufacturing efficiency of multi-sized metal gates.

[0069] The following is a specific example to illustrate that when at least two metal gates of different sizes need to be manufactured on the substrate structure, such as Figure 4 As shown, the above method specifically includes the following steps:

[0070] Step 401 : forming two gate trenches of polysilicon gates in a substrate structure based on a polysilicon gate process.

[0071] The process of generating the gate trench needs to be determined according to the target size of the two metal gates, and an insulating layer and a dielectric layer need to be generated. The process specifically includes the following steps.

[0072] K1, generating at least two polysilicon gates on the substrate structure according to target sizes of the two metal gates.

[0073] The original size of the generated polysilicon gate is determined according to the target size of the metal gate. In this embodiment, the size of the generated metal gate is determined according to the maximum target size, such as setting the maximum target size equal to the size of the polysilicon metal gate. In some embodiments, the thickness of the metal gate is set to 50nm and the height is set to 80nm.

[0074] K2, generating a dielectric layer outside at least two polysilicon gates and on the substrate structure.

[0075] Before generating the dielectric layer, an insulating layer needs to be generated on the outside of the polysilicon gate and on top of the substrate structure, such as Figure 1 As shown in , the thickness of the first insulating layer and the second insulating layer is determined by the production process, wherein the first insulating layer and the second insulating layer can be made of materials such as silicon nitride, silicon carbide and silicon carbonitride, which play an insulating role. The outer dielectric layer can also play the role of insulating the adjacent gate and reducing leakage. The dielectric layer can be made of silicon dioxide material, and the thickness is also determined by the production process.

[0076] K3, planarizing the dielectric layer to obtain a first grinding surface, wherein the first grinding surface includes a polysilicon gate.

[0077] Since the thickness of the dielectric layer covers the polysilicon gate, it needs to be flattened. The flattening process can be performed by chemical mechanical polishing (CMP) until the polysilicon metal gate is polished out and the height of the polysilicon gate is polished to a preset height to obtain a first polished surface.

[0078] K4, removing the exposed polysilicon material to form at least two gate trenches.

[0079] After obtaining the first polished surface, the polysilicon gate covering the inside of the dielectric layer leaks out of the surface. At this time, the polysilicon material needs to be removed, which is also called dummy gate removal. The purpose of removing the dummy gate is to form a gate trench, and at least two gate trenches formed in this process have the same size.

[0080] Step 402, depositing a first thin film layer on the inner sidewalls of the first gate trench and the second gate trench by atomic layer deposition technology; a first film size of the first thin film layer is the difference between the original size and the first target size, and the first target size is the gate size corresponding to the first metal gate.

[0081] Since the original sizes of the gate trenches generated in the same batch are the same, and the purpose is to obtain metal gates of different target sizes, the original sizes need to be reduced, specifically by filling the first film layer on the inner sidewalls of the gate trenches.

[0082] When two metal gates with different target sizes need to be generated on the substrate structure, the first thin film layer can be simultaneously generated on the inner sidewalls of the first gate trench and the second gate trench by atomic deposition technology. Figure 5 As shown, the first gate trench 503 and the second gate trench 504 are separated by a dielectric layer 502, and the bottom of the first gate trench 503 and the second gate trench 504 is the surface of the substrate structure, and the inner sidewall at this time is the first insulating layer. The first film layer 505 generated by atomic deposition technology is adsorbed on the surface of the entire substrate structure, the dielectric layer and the inner sidewall. Among them, the first film size of the first film layer is the difference between the original size and the first target size, and the first target size is the gate size corresponding to the first metal gate.

[0083] In an embodiment of the present application, the first film layer is set to a silicon nitride film layer, and the atomic layer deposition technology generates a silicon nitride film layer, and the precursor for generating the silicon nitride film needs to be introduced into the reaction vessel. In this embodiment, to generate a silicon nitride film, the first precursor and the second precursor of the first film layer need to be adsorbed on the inner wall respectively, and an adsorption reaction occurs. The adsorption reaction is used to generate the first film layer on the inner wall, and the first precursor and the second precursor of silicon nitride are silane gas and ammonia, respectively. Silane gas and ammonia form a plasma of silane and ammonia through glow discharge. The plasma can greatly reduce the reaction temperature of the reaction vessel, and the reaction temperature of the plasma is 350°C. The two plasmas react at this temperature to generate a silicon nitride film on the inner wall. It should be noted that the precursors required for different film layer materials are different.

[0084] Step 403 , forming a first photoresist layer in the first gate region of the first gate trench, and the second gate region of the second gate trench not covered by the first photoresist layer is a first photoresist reserved region.

[0085] Since the first film size of the first film layer is the difference between the original size and the first target size, the gate size of the first gate trench can be reduced to the target size after one deposition, and the first film layer in the second gate trench needs to be removed. At this time, the first gate trench needs to be protected and the first film layer in the second gate trench needs to be removed. In this solution, a first photoresist layer is generated in the first gate region of the first gate trench, and the first photoresist layer fills the first gate trench and covers the surface of the first gate region to play a protective role. The second gate region of the second gate trench not covered by the first photoresist layer is the first photoresist reserved region.

[0086] like Figure 6 As shown, the first gate trench 503 and the first film layer 505 are covered with a first photoresist layer 506 (located in the first gate region), while the second gate region where the second gate trench 504 is located is not covered and belongs to the first photoresist reserved region. The first film layer in the first photoresist reserved region needs to be removed.

[0087] Step 404: etching the first thin film layer in the first photoresist reserved area.

[0088] The function of the first photoresist layer is to prevent the first thin film layer in the first gate area from being etched, while the first thin film layer in the second gate area will be etched. Since the size of the polysilicon metal gate in the embodiment of the present application is directly set to the target size of the second gate, the etching depth is directly set to the first thin film size of the first thin film layer.

[0089] like Figure 7As shown, the first film layer in the first photoresist retaining area is etched away (including the dielectric layer 502 and the inner sidewall and the surface of the substrate structure 501), while the first film layer 505 (the first gate region portion) under the first photoresist layer 506 is retained.

[0090] In another possible implementation, in order to achieve higher precision size control, the size of the polysilicon gate can be set to exceed the maximum target size of the metal gate, that is, the original size of the second gate groove is larger than the target size of the second gate. At this time, the etching depth of the first thin film layer needs to be determined according to the target size. For example, the original size is 60nm, the thickness of the first thin film layer is 20nm, and the target size of the second metal gate is 50nm, then the size of the second groove covering the first thin film layer is 40nm, so the depth of etching required at this time is 10nm, that is, the inner sidewall of the second groove needs to retain the first thin film layer of 10nm.

[0091] Step 405 , removing the first photoresist layer by plasma ashing technology.

[0092] After the etching is completed, the first photoresist layer needs to be removed, for example, by plasma ashing technology, and the removal process will not damage the first film layer. Figure 8 As shown, only the first photoresist layer is removed before and after the removal, and the dielectric layer and the first thin film layer are not affected.

[0093] Step 406 , performing chemical mechanical polishing on all gate trenches and grinding them to a target height, wherein the metal gates on the substrate structure have the same target height.

[0094] like Fig. 9 As shown in FIG. 1 , after the first film layer is removed, the dielectric layer is further subjected to mechanical polishing to grind the dielectric layer to a target height. The grinding process will grind away all the first film layers above the dielectric layer.

[0095] After the grinding is completed, the interior of the first gate trench is etched again to remove the first film layer covering the surface of the substrate.

[0096] Step 407 , filling at least two gate trenches with metal fillers to form metal gates of target sizes.

[0097] like Fig. 9 As shown, after filling the metal filler, a first metal gate and a second metal gate with different target sizes are generated.

[0098] The method provided in the embodiment of the present application determines the first film size of the first film layer by calculating the difference between the target sizes of the two metal gates, and removes the first film layer in the first photoresist retention area by setting a first photoresist layer in the first gate area, thereby retaining the first film layer in the first gate area; further, metal gates of various sizes are obtained by removing the first photoresist layer and performing mechanical chemical polishing on the gate grooves, and then filling them with metal fillers.

[0099] The above embodiments are described with reference to metal gates of two different target sizes. In some embodiments, it may be necessary to prepare metal gates of three or more sizes, such as Fig.10 As shown, the following steps may be specifically included:

[0100] Step 1001 , forming three gate trenches of polysilicon gates on a substrate structure based on a polysilicon gate process.

[0101] Step 1002 , depositing a second thin film layer on the inner sidewalls of the first gate trench, the second gate trench, and the third gate trench by atomic layer deposition technology.

[0102] It should be noted that the second film size of the second film layer is the difference between the first target size and the second target size, the second target size is the gate size corresponding to the second metal gate, and the second film layer can also be at least one of a silicon carbide film layer, a silicon nitride film layer and a silicon carbonitride film layer, and can be the same as the first film layer.

[0103] Step 1003 , forming a second photoresist layer in the first gate region of the first gate trench.

[0104] The area covered by the second photoresist layer is the second photoresist protection area, that is, the part where the first gate area is located, and the second photoresist protection area is used to protect the second film layer of the first gate area. Correspondingly, the part where the second gate area and the third gate area are located is the second photoresist reserved area.

[0105] Step 1004, etching the second thin film layer in the second photoresist reserved area.

[0106] like Fig.11 As shown, the first gate trench 1110, the second gate trench 1120 and the third gate trench 1130 are adjacent and separated by a dielectric layer 1150. The scheme covers the first gate region, the second gate region and the third gate region with a second film layer 1140 by atomic deposition technology. Similarly, the second film layer 1140 can be at least one of a silicon nitride film layer, a silicon carbide film layer and a silicon carbonitride film layer. The second photoresist layer 1160 covers the second film layer 1140 in the first gate region. The remaining area is the second photoresist reserved area.

[0107] Step 1005 , removing the second photoresist layer by plasma ashing technology.

[0108] After removing the second photoresist layer Fig.11 As shown, the second film layer 1140 is retained on the inner sidewall of the first gate region and above the dielectric layer 1150. The second film layer in the remaining portion is etched.

[0109] Step 1006 , depositing a third thin film layer on the inner sidewalls of the first gate trench, the second gate trench, and the third gate trench by atomic layer deposition technology.

[0110] A third thin film layer is deposited on the inner sidewalls of the first gate trench, the second gate trench and the third gate trench by atomic deposition technology again, such as Fig.12 As shown, the third film layer 1170 covers the second film layer 1140 in the first gate region, as well as the second gate region and the third gate region, and the third film size of the third film layer 1170 is the difference between the second target size and the original size. The third film layer can also be at least one of a silicon carbide film layer, a silicon nitride film layer, and a silicon carbonitride film layer, and can be the same as the first film layer and the second film layer.

[0111] Step 1007 , forming a third photoresist layer in the first gate region and the second gate region of the second gate trench.

[0112] like Fig.12 As shown, the third photoresist layer 1180 covers the third thin film layer 1170 in the first gate region and the second gate region, and the third thin film layer in the third gate region belongs to the third photoresist reserved region.

[0113] Step 1008 , etching the third thin film layer in the third photoresist retaining area.

[0114] Step 1009, removing the third photoresist layer by plasma ashing technology.

[0115] After removing the third photoresist layer, Fig.12 As shown, the second thin film layer 1140 and the third thin film layer are attached to the first gate trench; the third thin film layer 1170 is attached to the second trench; and the third gate trench does not contain any thin film layer.

[0116] Step 1010 , chemical mechanical polishing is performed on all gate trenches, and they are ground to a target height.

[0117] Step 1011, filling the gate trench with metal filler to form a metal gate of a target size.

[0118] like Fig.13 As shown, after the filling is completed and the metal filler is ground, three metal gates with different target sizes are obtained.

[0119] It should be noted that in this embodiment, the sizes of metal gates of various target sizes are not very different, so a thin film layer of corresponding thickness can be directly deposited on the inner side wall by the difference. In some embodiments, when the target sizes of the metal gates differ greatly, multiple deposition and etching methods can be used, that is, multiple thin film layers are deposited according to the accuracy of the machine to achieve the target thickness, and then the photoresist layer is selectively placed to continue. In some embodiments, when it is necessary to generate more metal gates of different target sizes, the substrate structure can also be divided into multiple gate regions, and the above method is used to deposit thin film layers for different gate regions. This solution does not limit the number of metal gates.

[0120] To summarize, in the embodiments of the present application, in order to achieve metal gates of different sizes, in the process of generating a polysilicon gate, the gate size of the polysilicon metal gate is determined according to the target size of the metal gate, so as to subsequently reduce the original size; when depositing the thin film layer, the second thin film layer is generated in the gate groove by atomic deposition technology; and then, after multiple times of setting the photoresist layer and etching means, the third thin film layer of corresponding thickness is deposited in different gate grooves, thereby finally achieving the generation of metal gates of different target sizes.

[0121] Fig.14 : is a structural block diagram of a device for manufacturing a multi-size metal gate provided by an embodiment of the present application, the device comprising:

[0122] A trench generation module 1401 is used to form at least two gate trenches of polysilicon gates on a substrate structure based on a polysilicon gate process, wherein an original size of the gate trench is larger than a target size of the metal gate, and the target size is a size for filling a metal filler;

[0123] A thin film layer generating module 1402 is used to deposit a thin film layer on the inner sidewall of the gate trench according to the target size, wherein the thin film layer is used to fill the gate trench and reduce the original size of at least two gate trenches to the target size, wherein different gate trenches correspond to different target sizes;

[0124] The metal gate generation module 1403 is used to fill the at least two gate trenches with metal fillers to form the metal gate of the target size.

[0125] An embodiment of the present application also provides a computer device, which includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used by the processor to execute the method for manufacturing a multi-sized metal gate provided by the above-mentioned various method embodiments.

[0126] The preferred embodiments of the present invention are described above; it should be understood that the present invention is not limited to the above-mentioned specific embodiments, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any technician familiar with the art can make many possible changes and modifications without departing from the technical solution of the present invention, or modify them into equivalent embodiments with equivalent changes, which does not affect the essential content of the present invention; therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a multi-size metal gate, characterized in that: The method comprises: Based on the polysilicon gate process, at least three gate trenches of the polysilicon gate are formed on the substrate structure, wherein the original size of the gate trench is larger than the target size of the metal gate, and the target size is the size for filling the metal filler; Depositing a thin film layer on the inner sidewall of the gate trench according to the target size, the thin film layer is used to fill the gate trench, and reducing the original size of at least three gate trenches to the target size, wherein different gate trenches correspond to different target sizes; specifically, depositing a second thin film layer on the inner sidewalls of the first gate trench, the second gate trench, and the third gate trench by atomic layer deposition technology, wherein a second film size of the second thin film layer is a difference between the first target size and the second target size, and the first target size and the second target size are gate sizes corresponding to the first metal gate and the second metal gate, respectively; Generating a second photoresist layer in the first gate region of the first gate trench, wherein the second photoresist layer covers an area which is a second photoresist protection area, and the second photoresist protection area is used to protect the second thin film layer in the first gate region; Etching the second thin film layer in the second photoresist reserved area, wherein the second photoresist reserved area includes the second gate area and the third gate area of ​​the third gate trench; removing the second photoresist layer by plasma ashing technology; Depositing a third thin film layer on the inner sidewalls of the first gate trench, the second gate trench and the third gate trench by atomic layer deposition technology, wherein a third thin film size of the third thin film layer is a difference between the second target size and the original size; Generating a third photoresist layer in the first gate region and the second gate region of the second gate trench, wherein the third photoresist layer covers an area that is a third photoresist protection area; Etching the third thin film layer in a third photoresist reserved area, wherein the third photoresist reserved area includes the first gate area; removing the third photoresist layer by plasma ashing technology; Performing chemical mechanical polishing on all gate trenches and grinding them to a target height, wherein the metal gates on the substrate structure have the same target height; Filling the at least three gate trenches with metal fillers to form the metal gate with the target size.

2. The method according to claim 1, characterized in that The method of forming at least three gate trenches of polysilicon gates on a substrate structure based on a polysilicon gate process includes: generating the at least three polysilicon gates on the substrate structure according to the target size of the metal gate; Generating a dielectric layer outside the at least three polysilicon gates and on the substrate structure; Performing a planarization process on the dielectric layer to obtain a first grinding surface, wherein the first grinding surface includes the polysilicon gate; The exposed polysilicon material is removed to form the at least three gate trenches.

3. The method according to claim 2, characterized in that The dielectric layer is a silicon oxide layer, and the thin film layer includes at least one of a silicon carbide thin film layer, a silicon nitride thin film layer and a silicon carbonitride thin film layer.

4. A device for manufacturing a multi-size metal gate, characterized in that: The device comprises: A trench generation module, used for forming at least three gate trenches of polysilicon gates on the substrate structure based on a polysilicon gate process, wherein the original size of the gate trench is larger than the target size of the metal gate, and the target size is the size for filling the metal filler; A thin film layer generation module, used for depositing a thin film layer on the inner sidewall of the gate trench according to the target size, the thin film layer is used to fill the gate trench, and reduce the original size of at least three gate trenches to the target size, wherein different gate trenches correspond to different target sizes; specifically, a second thin film layer is deposited on the inner sidewall of the first gate trench, the second gate trench, and the third gate trench by atomic layer deposition technology, the second film size of the second thin film layer is the difference between the first target size and the second target size, and the first target size and the second target size are the gate sizes corresponding to the first metal gate and the second metal gate, respectively; Generating a second photoresist layer in the first gate region of the first gate trench, wherein the second photoresist layer covers an area which is a second photoresist protection area, and the second photoresist protection area is used to protect the second thin film layer in the first gate region; Etching the second thin film layer in the second photoresist reserved area, wherein the second photoresist reserved area includes the second gate area and the third gate area of ​​the third gate trench; removing the second photoresist layer by plasma ashing technology; Depositing a third thin film layer on the inner sidewalls of the first gate trench, the second gate trench and the third gate trench by atomic layer deposition technology, wherein a third thin film size of the third thin film layer is a difference between the second target size and the original size; Generating a third photoresist layer in the first gate region and the second gate region of the second gate trench, wherein the third photoresist layer covers an area that is a third photoresist protection area; Etching the third thin film layer in a third photoresist reserved area, wherein the third photoresist reserved area includes the first gate area; removing the third photoresist layer by plasma ashing technology; All gate trenches are subjected to chemical mechanical polishing and ground to a target height, wherein the metal gates on the substrate structure have the same target height; a metal gate generation module is used to fill the at least three gate trenches with metal fillers to form the metal gates of the target size.

5. A computer device, characterized in that: The computer device includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method for manufacturing a multi-sized metal gate as described in any one of claims 1 to 3.

Images