3D Memory, Method for Manufacturing 3D Memory, and Storage System

Abstract

The present invention relates to a three-dimensional memory, a manufacturing method of the three-dimensional memory, and a storage system. The manufacturing method of the three-dimensional memory includes: forming a stacked structure on a substrate, the stacked structure including a plurality of stacked regions and a gate line gap region located between adjacent stacked regions in a first direction; forming a plurality of channel holes penetrating the stacked structure in the stacked regions and a plurality of dummy channel holes penetrating the stacked structure in the gate line gap region; forming a gate line slit penetrating the stacked structure in the gate line gap region to remove the plurality of dummy channel holes and separate the stacked structures in adjacent stacked regions, so that during the process of etching to form channel holes in the stacked regions, it is possible to avoid the problem that etching materials formed due to the gate line gap region are likely to accumulate in the channel holes near the gate line gap region, resulting in insufficient etching of the channel holes near the gate line gap region, thereby improving the performance of the finally formed three-dimensional memory.

Description

[Technical field]

[0001] The present invention relates to the field of memory technology, and in particular to a three-dimensional memory, a method for manufacturing the three-dimensional memory, and a storage system. [Background technology]

[0002] With the development of technology, the semiconductor industry is constantly looking for new production methods to enable each memory die in the memory device to have more memory cells. Among them, 3D NAND (three-dimensional) memory has become a cutting-edge and highly potential three-dimensional memory technology due to its advantages such as high storage density and low cost.

[0003] The existing three-dimensional memory usually includes multiple memory block areas, adjacent memory block areas are separated by gate line gap areas, and multiple channel structures are distributed in each memory block area. However, in the process of forming the channel holes, the channel holes near the gate line gap areas will have the problem of insufficient etching, which will affect the performance of the finally formed three-dimensional memory. [Summary of the invention]

[0004] The embodiments of the present invention provide a three-dimensional memory and a manufacturing method and a storage system thereof, so as to improve the problem of insufficient etching of channel holes near the gate line gap region, thereby improving the performance of the finally formed three-dimensional memory.

[0005] In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a three-dimensional memory, which comprises: forming a stacking structure on a substrate, the stacking structure comprising a plurality of stacking regions and a gate line gap region located between adjacent stacking regions in a first direction; forming a plurality of channel holes penetrating the stacking structure in the stacking regions, and a plurality of virtual channel holes penetrating the stacking structure in the gate line gap region; forming a gate line slit penetrating the stacking structure in the gate line gap region to remove the plurality of virtual channel holes and separate the stacking structures in adjacent stacking regions.

[0006] The plurality of channel holes are arranged in a plurality of rows in the first direction, and the plurality of virtual channel holes are arranged in at least one row in the first direction.

[0007] The spacing distance between a row of virtual channel holes and a row of channel holes adjacent thereto in the first direction is equal to the spacing distance between two adjacent rows of channel holes.

[0008] The plurality of channel holes have the same aperture.

[0009] The virtual channel holes and the channel holes have the same aperture, and the spacing distance between any two adjacent channel holes, the spacing distance between any two adjacent virtual channel holes, and the spacing distance between any adjacent channel hole and a virtual channel hole are equal.

[0010] Among them, a plurality of channel holes penetrating the stacked structure in the stacked region and a plurality of virtual channel holes penetrating the stacked structure in the gate line gap region specifically include: providing a mask plate, the mask plate including a first region and a second region distributed along a first direction, the mask plate in the first region having a plurality of first openings, and the mask plate in the second region having a plurality of second openings; etching the stacked structure according to the plurality of first openings to form a plurality of channel holes penetrating the stacked structure in the stacked region, and etching the stacked structure according to the plurality of second openings to form a plurality of virtual channel holes penetrating the stacked structure in the gate line gap region.

[0011] Among them, before forming the gate line slit of the stacked structure in the gate line gap region, it further includes: forming a virtual channel structure in the virtual channel hole; forming a channel structure in the channel hole.

[0012] Among them, forming the virtual channel structure in the virtual channel hole specifically includes: forming a mask layer covering the channel hole and the virtual channel hole on the stacked structure; etching the mask layer located on the gate line gap region to form a third opening, the third opening exposing the virtual channel hole; forming a virtual channel structure in the virtual channel hole according to the third opening.

[0013] Among them, before forming the mask layer covering the channel hole and the virtual channel hole on the stacked structure, it further includes: forming a protective layer on the inner walls of the channel hole and the virtual channel hole.

[0014] Among them, before forming the channel structure in the channel hole, it further includes: removing the mask layer located on the stacked region to expose the channel hole.

[0015] Among them, forming the gate line slit of the stacked structure in the gate line gap region specifically includes: removing the stacked structure and the virtual channel structure in the gate line gap region to form the gate line slit.

[0016] Among them, the material of the virtual channel structure is an insulating material.

[0017] To solve the above problems, an embodiment of the present invention further provides a three-dimensional memory, which includes: a substrate; a stacked structure located on the substrate, the stacked structure including a plurality of stacked regions and a gate line gap region located between adjacent stacked regions in a first direction; a gate line slit penetrating the stacked structure in the gate line gap region, the gate line slit separating the stacked structures in adjacent stacked regions, and a plurality of concave-convex structures being formed in the bottom surface of the gate line slit; a plurality of channel structures penetrating the stacked structure in the stacked region.

[0018] Among them, the bottom surface of the gate line slit locally protrudes in a direction away from the substrate to form a plurality of concave-convex structures, and the concave-convex structures are bosses.

[0019] Among them, the bottom surface of the gate line slit locally protrudes towards the substrate into the substrate to form a plurality of concave-convex structures on the substrate, and the concave-convex structures are grooves.

[0020] Among them, the plurality of channel structures are arranged in multiple rows in the first direction, and the plurality of concave-convex structures include at least one row arranged in the first direction.

[0021] Among them, the spacing distance in the first direction between a row of concave-convex structures adjacent to the stacking region in at least one row of concave-convex structures and a row of channel structures adjacent to the gate line slit region in the multiple rows of channel structures is equal to the spacing distance in the first direction between two adjacent rows of channel structures.

[0022] Among them, the plurality of channel structures have the same outer diameter.

[0023] Among them, the spacing distance in the first direction between any two adjacent channel structures, the spacing distance in the first direction between any two adjacent concave-convex structures, and the spacing distance in the first direction between any adjacent channel structure and a concave-convex structure are equal.

[0024] To solve the above problems, the present invention also provides a storage system, which includes a controller and the three-dimensional memory of any one of the above, the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

[0025] The beneficial effects of the present invention are: different from the prior art, the three-dimensional memory and its manufacturing method provided by the present invention form a stacked structure on the substrate, the stacked structure includes a plurality of stacking regions and a gate line slit region located between adjacent stacking regions in the first direction, and form a plurality of channel holes penetrating the stacked structure in the stacking region and a plurality of virtual channel holes penetrating the stacked structure in the gate line slit region, and then form a gate line slit penetrating the stacked structure in the gate line slit region to remove the plurality of virtual channel holes and separate the stacked structures in adjacent stacking regions, so that during the process of etching and forming channel holes in the stacking region, the etching material (for example, polymer) formed in the gate line slit region can be more evenly distributed, rather than concentratedly entering the channel holes near the gate line slit region, so as to effectively improve the problem of insufficient etching of the channel holes near the gate line slit region, and further improve the performance of the finally formed three-dimensional memory.

Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained according to these drawings.

[0027] Figure 1 It is a schematic flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention;

[0028] Figure 2 It is a schematic top view structure diagram after step S11 of the embodiment of the present invention is completed;

[0029] Figure 3 It is along Figure 2 The cross-sectional structure diagram taken along the line O-O' in;

[0030] Figure 4 It is a schematic top view structure diagram after step S12 of the embodiment of the present invention is completed;

[0031] Figure 5 It is along Figure 4 The cross-sectional structure diagram taken along the line O-O' in;

[0032] Figure 6 It is a schematic top view structure diagram of a semiconductor structure obtained after forming a channel hole provided by the prior art;

[0033] Figure 7 It is another schematic top view structure diagram of a semiconductor structure obtained after forming a channel hole provided by the prior art;

[0034] Figure 8 It is another schematic top view structure diagram after step S12 of the embodiment of the present invention is completed;

[0035] Figure 9 It is another schematic top view structure diagram after step S12 of the embodiment of the present invention is completed;

[0036] Figure 10 It is a schematic top view structure diagram of a mask provided by an embodiment of the present invention;

[0037] Figure 11 It is another schematic top view structure diagram of a mask provided by an embodiment of the present invention;

[0038] Figure 12 It is a schematic cross-sectional structure diagram after step S12 of the embodiment of the present invention is completed;

[0039] Figure 13 It is a schematic cross-sectional structure diagram after step S141 of the embodiment of the present invention is completed;

[0040] Figure 14 It is a schematic cross-sectional structure diagram after step S142 of the embodiment of the present invention is completed;

[0041] Figure 15 It is a schematic cross-sectional structure diagram after step S1431 of the embodiment of the present invention is completed;

[0042] Figure 16 is a schematic cross-sectional structure diagram after the completion of step S1432 provided by an embodiment of the present invention;

[0043] Figure 17 is a schematic cross-sectional structure diagram after the completion of step S15 provided by an embodiment of the present invention;

[0044] Figure 18 is another schematic cross-sectional structure diagram after the completion of step S15 provided by an embodiment of the present invention;

[0045] Figure 19 is a schematic cross-sectional structure diagram after the completion of step S13 provided by an embodiment of the present invention;

[0046] Figure 20 is a schematic cross-sectional structure diagram after the completion of step S13 provided by an embodiment of the present invention;

[0047] Figure 21 is a schematic top view structure diagram after the completion of step S16 provided by an embodiment of the present invention;

[0048] Figure 22 is along Figure 21 a schematic cross-sectional structure diagram taken along the line O-O' in;

[0049] Figure 23 is along Figure 21 another schematic cross-sectional structure diagram taken along the line O-O' in;

[0050] Figure 24 is a schematic structure diagram of a memory system provided by an embodiment of the present invention.

Detailed Implementation Modes

[0051] Next, with reference to the accompanying drawings and embodiments, the present invention will be further described in detail. It should be specifically noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0052] In addition, the directional terms mentioned in the present invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms used are for explaining and understanding the present invention, rather than for limiting the present invention. In each of the drawings, units with similar structures are denoted by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0053] The present invention can be presented in various forms, and some examples will be described below.

[0054] Please refer to Figure 1 , Figure 1 which is a schematic flow chart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present invention. The specific process of the method for manufacturing the three-dimensional memory can be as follows:

[0055] Step S11: Form a stacked structure on a substrate. The stacked structure includes a plurality of stacked regions and a gate line gap region located between adjacent stacked regions in a first direction.

[0056] Among them, the top view structure schematic diagram after step S11 is as shown in Figure 2 , and the cross-sectional structure schematic diagram after step S11 is as shown in Figure 3 . And Figure 3 specifically, it is a cross-sectional structure schematic diagram taken along the line O-O' in Figure 2 .

[0057] The material of the substrate 11 can be a semiconductor material such as silicon, germanium, or silicon-on-insulator (SOI). The stacked structure 12 can include a gate sacrificial layer 121 and an insulating layer 122 that are alternately stacked in multiple layers in a direction away from the substrate 11.

[0058] Specifically, the above-mentioned stacked structure 12 can include a first stacked region K1, a gate line gap region GLS, and a second stacked region K2 that are sequentially connected in a first direction Y parallel to the substrate 11. Among them, the gate line gap region GLS can be used to form a gate line gap in subsequent process steps, and the gate line gap can be used to separate the stacked structures 12 in two adjacent stacked regions (for example, the first stacked region K1 and the second stacked region K2). The above-mentioned stacked regions K1 / K2 can be used to form a channel structure in subsequent process steps.

[0059] In some embodiments, the above-mentioned stacked structure 12 can include a plurality of block regions, and each block region can include a plurality of finger regions. And the above-mentioned stacked regions K1 / K2 can refer to block regions or finger regions. That is, the above-mentioned gate line gap region GLS can refer to the gate line gap region GLS located between adjacent block regions in the first direction Y, or can refer to the gate line gap region GLS located between adjacent finger regions in the first direction Y, or can also refer to the gate line gap region GLS located between adjacent finger regions and block regions in the first direction Y.

[0060] In the above-mentioned stacked structure 12, the gate sacrificial layer 121 can be formed between adjacent insulating layers 122. The material of the gate sacrificial layer 121 can be, but is not limited to, silicon nitride, and the material of the insulating layer 122 can be, but is not limited to, silicon oxide, so as to form a stacked structure of silicon nitride layer / silicon oxide layer. Moreover, in subsequent steps, the above-mentioned gate sacrificial layer 121 will be replaced through a replacement process and a conductive material (such as tungsten) will be filled in the same position to form a gate layer.

[0061] In a 3D memory, the number of layers of the stacked structure 12 determines the number of memory cells it contains in the vertical direction (the direction perpendicular to the substrate 11). For example, the number of layers of the stacked structure 12 can be 32 layers, 64 layers, 96 layers, 128 layers, etc. Moreover, the more layers the stacked structure 12 has, the higher the integration degree of the corresponding 3D memory.

[0062] Step S12: Form a plurality of channel holes penetrating the stacked structure in the stacked area and a plurality of dummy channel holes penetrating the stacked structure in the gate line gap area.

[0063] Among them, the top view structure diagram after step S12 is as Figure 4 shown, and the cross-sectional structure diagram after step S12 is as Figure 5 shown, and Figure 5 specifically, it is a cross-sectional structure diagram intercepted along the line O-O' in Figure 4 .

[0064] Specifically, an anisotropic etching process can be adopted. For example, a dry etching process (such as a plasma etching process, a reactive ion etching process, etc.) is used to etch the above-mentioned stacked structure 12 located in the stacked area K1 / K2 from top to bottom to form a channel hole 13 penetrating the stacked structure 12 in the stacked area K1 / K2 from top to bottom, and at the same time, the above-mentioned stacked structure 12 located in the gate line gap area GLS is etched from top to bottom to form a dummy channel hole 14 penetrating the stacked structure 12 in the gate line gap area GLS from top to bottom. In a specific embodiment, as Figure 5 shown, the above-mentioned channel hole 13 and dummy channel hole 14 can penetrate the above-mentioned stacked structure 12 in the direction Z perpendicular to the substrate 11 and extend into the substrate 11 to form an opening 11A and an opening 11B on the substrate 11 respectively, so as to achieve sufficient etching to ensure that the substrate 11 can be exposed via the channel hole 13 and the dummy channel hole 14, and it is also beneficial to increase the support effect of the channel structure formed in the channel hole 13 on the stacked structure 12 in subsequent processes.

[0065] In this embodiment, each channel hole 13 can be completely located within the stacked region K1 / K2, that is, it does not exceed the boundary of the stacked region K1 / K2. Each virtual channel hole 14 can be completely located within the gate line gap region GLS, that is, it does not exceed the boundary of the gate line gap region GLS.

[0066] It should be noted that the present inventors have found that, according to a method for manufacturing a three-dimensional memory of an embodiment, as Figure 6 shown, during the process of etching the stacked structure 22 in the stacked region K1’ / K2’ to form the channel hole 23, since the stacked structure 22 located in the gate line gap region GLS’ for forming the gate line gap in subsequent process steps will be reserved and not etched and patterned, most of the etching material (for example, polymer) formed in the gate line gap region GLS’ during the etching process will enter the channel hole 23 close to the gate line gap region GLS’, thereby causing the channel hole 23 close to the gate line gap region GLS’ to not be etched to the corresponding depth, resulting in the problem of under-etching and affecting the performance of the finally formed three-dimensional memory.

[0067] Moreover, in some embodiments, as Figure 7 shown, in order to solve the problem of under-etching of the channel hole 23 close to the gate line gap region GLS’, when designing the channel hole pattern, the size of the channel hole pattern corresponding to the channel hole 23 close to the gate line gap region GLS’ can be designed to be larger, that is, the top size of the channel hole 23 close to the gate line gap region GLS’ is larger than the top size of the channel hole 23 far from the gate line gap region GLS’.

[0068] However, the present inventors have found that the above solution of designing the size of the channel hole pattern corresponding to the channel hole 23 close to the gate line gap region GLS’ to be larger, although it can improve the problem of under-etching of the channel hole 23 close to the gate line gap region GLS’, such a design of the channel hole pattern will cause a large difference between the top size of the channel hole 23 close to the gate line gap region GLS’ and the top size of the channel hole 23 far from the gate line gap region GLS’, thereby deteriorating the morphological consistency of the channel hole 23 close to the gate line gap region GLS’ and the channel hole 23 far from the gate line gap region GLS’, and thus affecting the uniformity of the electrical parameters of the memory cells in the finally formed three-dimensional memory.

[0069] It can be understood that, as Figure 4As shown in the figure, in the process of etching the channel holes 13 in the stacking region K1 / K2 in this embodiment, the virtual channel holes 14 are etched in the gate line gap region GLS at the same time. This not only enables the etching materials (such as polymers) formed in the gate line gap region GLS during the etching process to be distributed more evenly, rather than concentrating on entering the channel holes 13 near the gate line gap region GLS, thereby effectively improving the problem of insufficient etching of the channel holes 13 near the gate line gap region GLS, but also enables the sizes of the channel holes 13 near the gate line gap region GLS and the channel holes 13 far from the gate line gap region GLS to be the same. Therefore, it can also improve the morphological consistency of the channel holes 13 near the gate line gap region GLS and the channel holes 13 far from the gate line gap region GLS, so as to improve the uniformity of the electrical parameters of the memory cells in the 3D memory.

[0070] Specifically, as Figure 4 shown, the above-mentioned multiple channel holes 13 can have the same aperture diameter, and the above-mentioned multiple virtual channel holes 14 can have the same aperture diameter. For a specific example, the above-mentioned multiple channel holes 13 can have the same shape and size, and the above-mentioned multiple virtual channel holes 14 can have the same shape and size.

[0071] In this embodiment, the same aperture diameter, the same shape, and the same size can respectively refer to at least the same surface aperture diameter, the same surface shape, and the same surface size. For example, the surface aperture diameters at the ends far from the substrate 11 are the same, the surface shapes at the ends far from the substrate 11 are the same, and the surface sizes at the ends far from the substrate 11 are the same.

[0072] In some embodiments, the aperture diameter, shape, and / or size of the above-mentioned channel holes 13 may not change from top to bottom, that is, the aperture diameter, shape, and / or size of the above-mentioned channel holes 13 may be the same from top to bottom. In some other embodiments, the aperture diameter, shape, and / or size of the above-mentioned virtual channel holes 14 may also not change from top to bottom.

[0073] In some other embodiments, the aperture diameter, shape, and / or size of the above-mentioned channel holes 13 and virtual channel holes 14 may change from top to bottom. For example, the aperture diameter, shape, and / or size of the channel holes 13 and virtual channel holes 14 may gradually decrease from top to bottom. And the same aperture diameter, shape, and size of the above-mentioned multiple channel holes 13 may specifically refer to the same aperture diameter, shape, and size at the tops of the above-mentioned multiple channel holes 13, and the same aperture diameter, shape, and size of the above-mentioned multiple virtual channel holes 14 may specifically refer to the same aperture diameter, shape, and size at the tops of the above-mentioned multiple virtual channel holes 14.

[0074] Moreover, the aperture diameter, shape, and size at the top of the above-mentioned channel hole 13 and the aperture diameter, shape, and size at the top of the above-mentioned dummy channel hole 14 can be adjusted by changing the mask used in the etching process for forming the above-mentioned channel hole 13 and dummy channel hole 14.

[0075] In a specific embodiment, as Figure 8 shown, the channel hole 13 and the dummy channel hole 14 can have the same aperture diameter. Specifically, the channel hole 13 and the dummy channel hole 14 can have the same shape and size. For example, the cross-sectional shape of the channel hole 13 and the dummy channel hole 14 can be a circle with the same diameter.

[0076] In a specific embodiment, the above-mentioned multiple channel holes 13 and the above-mentioned multiple dummy channel holes 14 can be evenly distributed in the stacking regions K1 / K2 and the gate line gap region GLS of the stacking structure 12. Specifically, the spacing distance between any two adjacent channel holes 13, the spacing distance between any two adjacent dummy channel holes 14, and the spacing distance between any adjacent one channel hole 13 and one dummy channel hole 14 can all be equal.

[0077] In this embodiment, the spacing distance can refer to the center spacing distance or the closest edge spacing distance. Among them, the center spacing distance and the closest edge spacing distance can specifically refer to the center spacing distance at the end and the closest edge spacing distance at the end, respectively, and this end can be the top away from the above-mentioned substrate 11.

[0078] Moreover, in a possible embodiment, the above-mentioned channel hole 13 and the dummy channel hole 14 can have the same shape and size, and the distance between the center points of any two adjacent channel holes 13, the distance between the center points of any two adjacent dummy channel holes 14, and the distance between the center points of any adjacent one channel hole 13 and one dummy channel hole 14 can all be equal.

[0079] Correspondingly, the channel holes 13 located in the above-mentioned stacking region K1 / K2 and the dummy channel holes 14 located in the above-mentioned gate line gap region GLS can be arranged in a manner of sharing a layout pattern, so that the channel holes 13 located in the stacking region K1 / K2 and the dummy channel holes 14 located in the gate line gap region GLS have the same other features (such as shape, size, and the spacing distance between the center points of adjacent dummy channel holes 14 and / or channel holes 13) except for the different distribution positions.

[0080] Thus, during the process of etching the channel holes 13 in the stacked region K1 / K2, it is ensured that the etching materials formed in the stacked region K1 / K2 and the gate line gap region GLS are evenly distributed, thereby completely eliminating the differences in the etching materials entering each channel hole 13, being able to completely solve the problem of insufficient etching in the channel holes 13 near the gate line gap region GLS, and enabling the channel holes 13 near the gate line gap region GLS and the channel holes 13 far from the gate line gap region GLS to be completely consistent in topography, improving the consistency of the electrical parameters of each memory cell in the three-dimensional memory.

[0081] In some other embodiments, as Figure 4 shown, the above-mentioned multiple channel holes 13 can be arranged in multiple rows in the first direction Y parallel to the substrate 11, that is, the multiple channel holes 13 can include multiple rows of channel holes. The above-mentioned multiple virtual channel holes 14 can be arranged in at least one row in the first direction Y, that is, the above-mentioned multiple virtual channel holes 14 can include at least one row of virtual channel holes.

[0082] Among them, the interval distance between a row of virtual channel holes and a row of channel holes adjacent to it in the first direction Y can be equal to the interval distance between adjacent two rows of channel holes. For example, the interval distance between the row of virtual channel holes closest to the stacked region K1 / K2 in the above-mentioned at least one row of virtual channel holes and the row of channel holes closest to the gate line gap region GLS in the multiple rows of channel holes adjacent to it is equal to the interval distance between adjacent two rows of channel holes.

[0083] In this embodiment, the interval distance between adjacent two rows of channel holes can specifically be the interval distance between the tops of adjacent two rows of channel holes. The interval distance between an adjacent row of virtual channel holes and a row of channel holes can specifically be the interval distance between the top of an adjacent row of virtual channel holes and the top of a row of channel holes. The interval distance between adjacent two rows of virtual channel holes can specifically be the interval distance between the tops of adjacent two rows of virtual channel holes.

[0084] In some specific embodiments, the above-mentioned multiple channel holes 13 can have the same shape and size, and the multiple rows of channel holes and at least one row of virtual channel holes can be evenly distributed in the first direction Y.

[0085] In a specific application scenario, as Figure 8As shown, the channel holes 13 and the dummy channel holes 14 may have the same shape and size, and the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes may be equally spaced in the first direction Y. That is, the channel holes 13 and the dummy channel holes 14 have the same shape and size, and the spacing distance between any two adjacent rows of channel holes in the first direction Y, the spacing distance between any two adjacent rows of dummy channel holes in the first direction Y, and the spacing distance between any adjacent row of channel holes and a row of dummy channel holes in the first direction Y may all be equal.

[0086] Specifically, the width W1 of the above-mentioned gate line slit region GLS in the first direction Y may satisfy the condition for equally spacing the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes in the first direction Y, that is, not less than (m1*D1+(m1-1)*D2), and not greater than (m1*D1+(m1+1)*D2), where m1 is a positive integer greater than 0, D1 is the width of a row of channel holes in the first direction Y, and D2 is the spacing distance between two adjacent rows of channel holes 13.

[0087] It can be understood that in the application scenario where the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes are equally spaced in the first direction Y, when the width W1 of a gate line slit region GLS in the first direction Y satisfies not less than (m1*D1+(m1-1)*D2) and not greater than (m1*D1+(m1+1)*D2), m1 rows of dummy channel holes can be provided on the corresponding gate line slit region GLS.

[0088] Taking m1 equal to 2, that is, the width of the gate line slit region GLS in the first direction Y is not less than (2*D1+D2) and not greater than (2*D1+3*D2) as an example, in the application scenario where the above-mentioned multiple rows of channel holes and at least one row of dummy channel holes are equally spaced in the first direction Y, exactly two rows of dummy channel holes can be provided on the gate line slit region GLS.

[0089] In another specific application scenario, as Figure 4 shown, the above-mentioned multiple channel holes 13 may have the same shape and size, and the above-mentioned multiple rows of channel holes may be equally spaced in the first direction Y, the above-mentioned multiple dummy channel holes 14 may have the same shape and size, and the above-mentioned at least one row of dummy channel holes may be equally spaced in the first direction Y. That is, the above-mentioned multiple channel holes 13 may have the same shape and size, the above-mentioned multiple dummy channel holes 14 may have the same shape and size, and the spacing distance between any two adjacent rows of channel holes in the first direction Y may be equal, and, when the above-mentioned multiple dummy channel holes 14 include at least two rows of dummy channel holes, the spacing distance between any two adjacent rows of dummy channel holes in the first direction Y may also be equal.

[0090] Moreover, the width W2 of the above-mentioned gate line slit region GLS in the first direction Y may not satisfy the condition for equally spacing the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes in the first direction Y. That is, it may be less than ((m1 + 1)*D1 + m1*D2) and greater than (m1*D1 + (m1 + 1)*D2). The channel holes 13 corresponding to the above-mentioned stacked region K1 / K2 and the dummy channel holes 14 located on the above-mentioned gate line slit region GLS may be arranged in different arrangement patterns.

[0091] It can be understood that in the application scenario where the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes are not equally spaced in the first direction Y, when the width W1 of a gate line slit region GLS in the first direction Y satisfies being less than ((m1 + 1)*D1 + m1*D2) and greater than (m1*D1 + (m1 + 1)*D2), m1 rows of dummy channel holes can be arranged on the corresponding gate line slit region GLS. That is, the above-mentioned multiple dummy channel holes 14 can include m1 rows of dummy channel holes to ensure that the boundaries of the above-mentioned multiple dummy channel holes 14 do not extend beyond the boundaries of the gate line slit region GLS.

[0092] Taking m1 equal to 1, that is, the width of the gate line slit region GLS in the first direction Y is less than (2*D1 + D2) and greater than (D1 + 2*D2) as an example, in the application scenario where the above-mentioned multiple channel holes 13 and the above-mentioned multiple dummy channel holes 14 are unevenly distributed on the stacked region K1 / K2 and the gate line slit region GLS of the substrate 11, one row of dummy channel holes can be arranged on the gate line slit region GLS.

[0093] In some specific embodiments, in order to minimize the difference in etching materials entering the channel holes 13 close to the gate line slit region GLS and the channel holes 13 far from the gate line slit region GLS as much as possible during the process of etching the channel holes 13 in the stacked region K1 / K2 when the width of the above-mentioned gate line slit region GLS in the first direction Y does not satisfy the condition for equally spacing the above-mentioned multiple rows of channel holes and the above-mentioned at least one row of dummy channel holes in the first direction Y, so as to improve the problem of insufficient etching of the channel holes 13 close to the gate line slit region GLS, it can be set that: the spacing distance between the row of dummy channel holes closest to the stacked region K1 / K2 in the above-mentioned at least one row of dummy channel holes and the row of channel holes closest to the gate line slit region GLS in the above-mentioned multiple rows of adjacent channel holes is equal to the spacing distance between two adjacent rows of channel holes.

[0094] Moreover, when the multiple virtual channel holes 14 include multiple rows of virtual channel holes, the spacing distance between any two adjacent rows of virtual channel holes in the first direction Y and the spacing distance between any two adjacent rows of channel holes in the first direction Y can be equal. Thus, the multiple rows of channel holes and the at least one row of virtual channel holes can be equally spaced in the first direction Y, and further, the multiple channel holes 13 and the multiple virtual channel holes 14 can be as close to a uniform distribution as possible. Therefore, during the process of etching the channel holes 13 in the stacking region K1 / K2, the etching materials formed in the stacking region K1 / K2 and the gate line gap region GLS can be as close to a uniform distribution as possible, so as to eliminate the difference in etching materials entering each channel hole 13 as much as possible, effectively improving the problem of insufficient etching of the channel holes 13 near the gate line gap region GLS, and making the channel holes 13 near the gate line gap region GLS and the channel holes 13 far from the gate line gap region GLS as identical as possible in topography, so as to improve the consistency of the electrical parameters of each memory cell in the 3D memory.

[0095] In some embodiments, as Figure 9 shown, the cross-sectional area of the virtual channel hole 14 can be larger than the cross-sectional area of the channel hole 13. Specifically, in the application scenario where the multiple rows of channel holes and the at least one row of virtual channel holes are not equally spaced in the first direction Y, when the width W1 of a gate line gap region GLS in the first direction Y satisfies being less than ((m1 + 1)*D1 + m1*D2) and greater than (m1*D1+(m1 + 1)*D2), if m1 rows of virtual channel holes are equally spaced in the gate line gap region GLS, and the shape and size of the virtual channel hole 14 are the same as those of the channel hole 13, then the spacing distance between the row of virtual channel holes closest to the stacking region K1 / K2 in the m1 rows of virtual channel holes and the row of channel holes closest to the stacking region K1 / K2 in the adjacent multiple rows of channel holes will necessarily be greater than the spacing distance between two adjacent rows of channel holes. Therefore, the size of the virtual channel hole 14 in the first direction Y can be adaptively increased relative to the channel hole 13, so that the spacing distance between any two adjacent rows of channel holes in the first direction Y, the spacing distance between any two adjacent rows of virtual channel holes in the first direction Y, and the spacing distance between any adjacent row of channel holes and a row of virtual channel holes in the first direction Y can be equal, and further, the multiple channel holes 13 and the multiple virtual channel holes 14 can be as close to a uniform distribution as possible on the stacking region K1 / K2 and the gate line gap region GLS of the substrate 11.

[0096] Moreover, in specific implementation, it can be set that: the maximum width of the above-mentioned virtual channel hole 14 in the first direction Y is greater than the maximum width in the second direction X perpendicular to the first direction Y, and the cross-sectional shape corresponding to the virtual channel hole 14 can be a geometric shape such as an ellipse with a major axis and a minor axis. Specifically, the maximum width of the above-mentioned virtual channel hole 14 in the second direction X can also be equal to the maximum width of the above-mentioned channel hole 13 in the second direction X.

[0097] In the above embodiment, the above-mentioned step S12 can specifically include:

[0098] Step S121: Provide a mask plate, which includes a first region and a second region distributed along the first direction. The mask plate in the first region has a plurality of first openings, and the mask plate in the second region has a plurality of second openings.

[0099] Step S122: Etch the stacked structure according to the plurality of first openings to form a plurality of channel holes penetrating the stacked structure in the stacked region, and etch the stacked structure according to the plurality of second openings to form a plurality of virtual channel holes penetrating the stacked structure in the gate line slot region.

[0100] In this embodiment, as Figure 10 shown, the first region 30A of the above-mentioned mask plate 30 can correspond one-to-one with the stacked region K1 / K1 of the above-mentioned substrate 11, and the second region 30B can correspond one-to-one with the gate line slit region GLS of the above-mentioned substrate 11. The first openings 301 on the first region 30A can correspond one-to-one with the above-mentioned channel holes 13, and the second openings 302 on the second region 30B can correspond one-to-one with the above-mentioned virtual channel holes 14.

[0101] Specifically, as Figure 10 shown, the above-mentioned plurality of first openings 301 can be arranged in multiple rows in the first direction Y, and the above-mentioned plurality of second openings 302 can be arranged in at least one row in the first direction Y. Thus, the plurality of channel holes 13 formed by etching the stacked structure 12 through the plurality of first openings 301 can be arranged in multiple rows in the first direction Y, and the plurality of virtual channel holes 14 formed by etching the stacked structure 12 through the plurality of second openings 302 can be arranged in at least one row in the first direction Y.

[0102] In some embodiments, as Figure 10 shown, the above-mentioned plurality of first openings 301 can have the same shape and size to ensure that the channel holes 13 formed by etching the stacked structure 12 through the first openings 301 can have the same shape and size, thereby ensuring the electrical parameter uniformity of the storage units in the 3D memory.

[0103] In a specific embodiment, as Figure 11As shown, the spacing distance between the row of second openings closest to the first region 30A among the at least one row of second openings and the row of trench holes closest to the second region 30B among the multiple rows of first openings adjacent thereto can be equal to the spacing distance between adjacent two rows of first openings. Specifically, the spacing distance between any two adjacent rows of first openings in the first direction Y, the spacing distance between any two adjacent rows of second openings in the first direction Y, and the spacing distance between any adjacent row of first openings and a row of second openings in the first direction Y can all be equal, so that the multiple rows of trench holes formed by etching the stacked structure 12 through the first openings 301 and the at least one row of virtual trench holes formed by etching the stacked structure 12 through the second openings 302 can be equally spaced in the first direction Y on the stacked region K1 / K2 and the gate line gap region GLS. Thus, the multiple trench holes 13 and the multiple virtual trench holes 14 can be as evenly distributed as possible on the stacked region K1 / K2 and the gate line gap region GLS of the substrate 11.

[0104] In some embodiments, as Figure 11 shown, the cross-sectional area of the second opening 302 can be larger than the cross-sectional area of the first opening 301, so that the cross-sectional area of the virtual trench hole 14 formed by etching the stacked structure 12 through the second opening 302 can be larger than the cross-sectional area of the trench hole 13 formed by etching the stacked structure 12 through the first opening 301.

[0105] Specifically, the maximum width of the second opening 302 in the first direction Y can be larger than the maximum width in the direction X perpendicular to the first direction Y. And, the spacing distance between any two adjacent rows of first openings in the first direction Y, the spacing distance between any two adjacent rows of second openings in the first direction Y, and the spacing distance between any adjacent row of first openings and a row of second openings in the first direction Y can all be equal.

[0106] Moreover, in specific implementation, the maximum width of the second opening 302 in the first direction Y can be larger than the maximum width in the direction X perpendicular to the first direction Y, and the corresponding second opening 302 can be a geometric shape such as an ellipse with a major axis and a minor axis. Specifically, the maximum width of the second opening 302 in the direction X can also be equal to the maximum width of the first opening 301 in the direction X.

[0107] It can be understood that the number, shape, size, and arrangement manner of the first region 30A, the second region 30B, the first opening 301, and the second opening 302 on the mask 30 can be the same as the number, shape, size, and arrangement manner of the corresponding stacked region K1 / K1, the gate line gap region GLS, the trench hole 13, and the virtual trench hole 14, so details are not described herein again.

[0108] In the above embodiments, in order to increase the number of layers of the stacked structure 12 to increase the storage density of the 3D memory while not increasing the etching process difficulty of forming the channel holes 13 and the dummy channel holes 14, the stacked structure 12 may include a plurality of stack structures stacked in the direction Z away from the substrate 11, and correspondingly, the channel holes 13 and the dummy channel holes 14 penetrating through the stacked structure 12 may be formed by multiple etching processes.

[0109] Moreover, for the sake of easy understanding and explanation, as Figure 12 shown, in this embodiment, the stacked structure 12 including the first stack structure 12A and the second stack structure 12B stacked in the direction Z away from the substrate 11 is taken as an example for illustration. Correspondingly, the above step S12 may specifically include: forming a first channel hole 13A located on the stacking regions K1 / K2 and penetrating through the first stack structure 12A, and a first dummy channel hole 14A located on the gate line gap region GLS and penetrating through the first stack structure 12A; forming a sacrificial material layer in the first channel hole 13A and the first dummy channel hole 14A; forming the second stack structure 12B on the first stack structure 12A and the sacrificial material layer; forming a second channel hole 13B located on the stacking regions K1 / K2 and penetrating through the second stack structure 12B, and a second dummy channel hole 14B located on the gate line gap region GLS and penetrating through the second stack structure 12B, wherein the second channel hole 13B exposes the sacrificial material layer located in the first channel hole 13A, and the second dummy channel hole 14B exposes the sacrificial material layer located in the first dummy channel hole 14A; removing the sacrificial material layer through the second channel hole 13B and the second dummy channel hole 14B to obtain the channel hole 13 composed of the connected first channel hole 13A and the second channel hole 13B and the dummy channel hole 14 composed of the connected first dummy channel hole 14A and the second dummy channel hole 14B.

[0110] Specifically, both the first stack structure 12A and the second stack structure 12B in the stacked structure 12 may include multiple layers of the above-mentioned gate sacrificial layers 121 and gate insulating layers 122 stacked alternately in the longitudinal direction Z away from the substrate 11. Moreover, the number of layers of the second stack structure 12B may be the same as or different from the number of layers of the first stack structure 12A.

[0111] The above-mentioned first channel hole 13A and the first dummy channel hole 14A can be formed by etching the above-mentioned first stack structure 12A from top to bottom in the stacking region K1 / K2 and the gate line gap region GLS, respectively. The first channel hole 13A and the first dummy channel hole 14A penetrate through the first stack structure 12A and can extend into the substrate 11 in the longitudinal direction Z perpendicular to the substrate 11. The above-mentioned second channel hole 13B and the second dummy channel hole 14B can be formed by etching the above-mentioned second stack structure 12B from top to bottom in the stacking region K1 / K2 and the gate line gap region GLS, respectively. The second channel hole 13B and the second dummy channel hole 14B penetrate through the second stack structure 12B in the longitudinal direction Z perpendicular to the substrate 11 and reach the upper surface of the first stack structure 12A. Moreover, the bottom of the second channel hole 13B can expose the top surface of the sacrificial material layer in the first channel hole 13A, and the bottom of the second dummy channel hole 14B can expose the top surface of the sacrificial material layer in the first dummy channel hole 14A.

[0112] The above-mentioned sacrificial material layer can be formed by depositing and filling the sacrificial material in the first channel hole 13A and the first dummy channel hole 14A by using a chemical vapor deposition process and removing the sacrificial material located outside the first channel hole 13A and the first dummy channel hole 14A by using chemical mechanical planarization. Among them, the sacrificial material can be any one of polysilicon, carbon, and tungsten.

[0113] Correspondingly, the above-mentioned channel hole 13 can include a connected first channel hole 13A and a second channel hole 13B, and the above-mentioned dummy channel hole 14 can include a connected first dummy channel hole 14A and a second dummy channel hole 14B. Moreover, after forming the second channel hole 13B and the second dummy channel hole 14B, a selective etchant can be used to selectively remove the above-mentioned sacrificial material layer via the second channel hole 13B and the second dummy channel hole 14B.

[0114] Step S13: Form a gate line slit that penetrates the stack structure in the gate line gap region to remove a plurality of dummy channel holes and separate the stack structures in adjacent stacking regions.

[0115] Among them, before the above-mentioned step S13, it can further include:

[0116] Step S14: Form a dummy channel structure in the dummy channel hole.

[0117] Specifically, the above-mentioned step S14 can specifically include:

[0118] Step S141: Form a mask layer covering the channel hole and the dummy channel hole on the stack structure.

[0119] Among them, the schematic cross-sectional structure diagram after completing step S141 is as Figure 13 shown.

[0120] The material of the mask layer 15 may include insulating materials such as silicon oxide.

[0121] Step S142: Etch the mask layer located on the gate line gap region to form a third opening, and the third opening exposes the virtual channel hole.

[0122] Among them, the schematic cross-sectional structure diagram after step S142 is as Figure 14 shown.

[0123] Specifically, the third opening 151 can be formed by etching away the mask layer 15 located on the gate line gap region GLS.

[0124] Step S143: Form a virtual channel structure in the virtual channel hole according to the third opening.

[0125] Among them, the above step S143 may specifically include:

[0126] Step S1431: Form a virtual channel structure in the third opening and the virtual channel hole.

[0127] Among them, the schematic cross-sectional structure diagram after step S1431 is as Figure 15 shown.

[0128] The virtual channel structure 16 may include insulating materials such as silicon oxide. Specifically, an insulating material may be filled in the third opening 151 and the virtual channel hole 14 to form the virtual channel structure 16.

[0129] Step S1432: Align the virtual channel structure with the stacked structure.

[0130] Among them, the schematic cross-sectional structure diagram after step S1432 is as Figure 16 shown.

[0131] Specifically, the virtual channel structure 16 can be aligned with the stacked structure 12 by chemical mechanical polishing or wet etching. In a specific embodiment, as Figure 16 shown, the top gate sacrificial layer 121 in the stacked structure 12 can be used as a polishing stop layer, and the surface of the stacked structure 12 facing away from the substrate 11 (i.e., the top surface of the stacked structure 12) can be polished to expose the top surface of the top gate sacrificial layer 121 in the stacked structure 12 and enable the surface of the substrate 11 at the bottom of the channel hole 13 to be exposed again.

[0132] It can be understood that during the process of aligning the virtual channel structure 16 with the stacked structure 12, the mask layer 15 located on the stacked regions K1 / K2 will be removed, so that the channel holes 13 covered by the mask layer 15 in the previous process steps are re-exposed, facilitating the formation of a channel structure in the channel holes 13 in subsequent process steps.

[0133] Step S15: Form a channel structure in the channel hole.

[0134] Among them, the schematic cross-sectional structure diagram after step S15 is as Figure 17 shown.

[0135] The channel structure 17 may include a storage function layer and a channel layer sequentially arranged on the side walls of the channel hole 13. Specifically, the storage function layer may specifically include a first oxide layer as a charge blocking layer, a nitride layer as a charge trapping layer, and a second oxide layer as a tunneling layer sequentially arranged on the side walls of the channel hole 13. Among them, the materials of the first oxide layer, nitride layer, second oxide layer, and channel layer may be silicon oxide, silicon nitride, silicon oxide, and polysilicon respectively.

[0136] In some specific embodiments, as Figure 18 shown, before forming the virtual channel structure 16 in the virtual channel hole 14, a protective layer 20 may also be formed on the inner walls of the channel hole 13 and the virtual channel hole 14. Specifically, the inner walls of the channel hole 13 and the virtual channel hole 14 may be oxidized to form an oxide as the protective layer 20. Among them, the protective layer 20 can protect the inner walls of the channel hole 13 and the virtual channel hole 14 from being damaged in subsequent process steps.

[0137] In other specific embodiments, as Figure 18 shown, before forming the virtual channel structure 16 in the virtual channel hole 14, an epitaxial layer 21 may also be formed at the bottoms of the channel hole 13 and the virtual channel hole 14. Correspondingly, the above virtual channel structure 16 may be located on the epitaxial layer 21 at the bottom of the virtual channel hole 14, and the above channel structure 17 may be located on the epitaxial layer 21 at the bottom of the channel hole 13.

[0138] Moreover, in specific embodiments, after forming the above channel hole 13 and virtual channel hole 14, the above epitaxial layer 21 may be formed on the bottoms of the channel hole 13 and the virtual channel hole 14, then the above protective layer 20 may be formed on the inner walls of the channel hole 13 and the virtual channel hole 14 with the epitaxial layer 21 formed at the bottoms, and then the above channel structure 17 and virtual channel structure 16 may be formed in the remaining spaces of the channel hole 13 and the virtual channel hole 14 respectively.

[0139] In a possible embodiment, when the above-mentioned epitaxial layer 21 is not formed at the bottom of the virtual channel hole 14 in the previous process step, the schematic cross-sectional structure diagram after the completion of the above-mentioned step S13 can be as Figure 19 shown, and the above-mentioned step S13 may specifically include: removing the stacked structure 12, the virtual channel structure 16, and the protective layer 20 (if any) located on the gate line slit region GLS to form a gate line slit 18.

[0140] Specifically, a bottom surface portion of the above-mentioned gate line slit 18 may protrude toward the substrate 11 into the substrate 11 to form a plurality of grooves 18A on the substrate 11. And it can be understood that the grooves 18A may correspond one-to-one to the virtual channel holes 14 located in the gate line slit region GLS, and the groove 18A may specifically be the bottom end portion of its corresponding virtual channel hole 14, or may be formed by further extending into the substrate 11 in the direction toward the substrate 11 during the etching process of forming the gate line slit 18 for its corresponding virtual channel hole 14.

[0141] In another possible embodiment, when the above-mentioned epitaxial layer 21 is formed at the bottom of the virtual channel hole 14 in the previous process step, the schematic cross-sectional structure diagram after the completion of the above-mentioned step S13 can be as Figure 20 shown, and the above-mentioned step S13 may specifically include: removing the stacked structure 12, the virtual channel structure 16, the protective layer 20 (if any), and at least a part of the epitaxial layer 21 located in the gate line slit region GLS to form a gate line slit 18.

[0142] Specifically, a bottom surface portion of the above-mentioned gate line slit 18 may protrude in a direction away from the substrate 11 to form a plurality of protrusions 18B. And it can be understood that the protrusions 18B may correspond one-to-one to the virtual channel holes 14 located in the gate line slit region GLS, and the protrusion 18B may be formed during the etching process of forming the gate line slit 18 because the reaction rate of the epitaxial layer 21 directly below the virtual channel structure 16 in the gate line slit region GLS with the etchant is less than the reaction rates of the stacked structure 12 and the virtual channel structure 16 with the etchant, so that the substrate 11 directly below the virtual channel structure 16 reacts with the etchant later and is consumed less by the etchant.

[0143] In the above embodiment, after the above-mentioned step S13, it may further include:

[0144] Step S16: Forming a gate line slit structure in the gate line slit.

[0145] Among them, the schematic top view structure diagram after the completion of step S16 is as Figure 21 shown, the schematic cross-sectional structure diagram after the completion of step S16 is as Figure 22 or Figure 23 shown, and, Figure 22and Figure 23 may specifically be a schematic cross-sectional structure diagram taken along the line O - O' in Figure 21 .

[0146] Specifically, the gate line slit structure 19 can be formed by filling an insulating material (such as insulating materials with high dielectric constants like silicon oxide, silicon nitride, silicon oxynitride, etc.) in the above-mentioned gate line slit 18. In some alternative embodiments, the gate line slit structure 19 with a common source electrode can also be obtained by filling a spacer layer (such as an oxide layer) serving as an insulating layer and a conductive material (such as titanium or titanium nitride, polysilicon, and / or tungsten) serving as a common source electrode in the above-mentioned gate line slit 18.

[0147] In some embodiments, before forming the gate line slit structure 19 in the gate line slit 18, it may further include: replacing the gate sacrificial layer 121 in the stacked structure 12 with a gate layer through the gate line slit 18.

[0148] Specifically, the gate sacrificial layer 121 of the above-mentioned stacked structure 12 can be replaced through a replacement process, and a conductive material (such as tungsten) can be filled at the same position to form the gate layer of the stacked structure 12.

[0149] Different from the prior art, in the method for manufacturing a three-dimensional memory in this embodiment, a stacked structure is formed on a substrate. The stacked structure includes a plurality of stacked regions and a gate line slit region located between adjacent stacked regions in a first direction. Then, a plurality of channel holes penetrating the stacked structure in the stacked regions and a plurality of dummy channel holes penetrating the stacked structure in the gate line slit region are formed. After that, a gate line slit penetrating the stacked structure in the gate line slit region is formed to remove the plurality of dummy channel holes and separate the stacked structures in adjacent stacked regions. Thus, during the process of etching to form channel holes in the stacked regions, the etching material (such as polymer) formed in the gate line slit region can be distributed more evenly, rather than concentrating on entering the channel holes close to the gate line slit region, so as to effectively improve the problem of insufficient etching of the channel holes close to the gate line slit region, and further improve the performance of the finally formed three-dimensional memory.

[0150] The three-dimensional memory fabricated according to the method embodiment of the present invention as shown in Figure 21 , Figure 22 and Figure 23As shown, the three-dimensional memory may include: a substrate 11; a stacked structure 12 located on the substrate 11, the stacked structure 12 including a plurality of stacked regions K1 / K2 and a gate line gap region GLS located between adjacent stacked regions K1 / K2 (for example, the first stacked region K1 and the second stacked region K2) in the first direction Y; a gate line slit 18 passing through the stacked structure 12 in the gate line gap region GLS, the gate line slit 18 separating the stacked structure 12 in adjacent stacked regions K1 / K2, and a plurality of concavo-convex structures being formed in the bottom surface of the gate line slit GLS; and a plurality of channel structures 17 passing through the stacked structure 12 in the stacked regions K1 / K2.

[0151] In one embodiment, as Figure 22 shown, a part of the bottom surface of the above-mentioned gate line slit 18 may protrude toward the substrate 11 into the substrate 11 to form a plurality of grooves 18A on the substrate 11, thereby obtaining a plurality of concavo-convex structures that are the grooves 18A.

[0152] In another embodiment, as Figure 23 shown, a part of the bottom surface of the above-mentioned gate line slit 18 may protrude in a direction away from the substrate 11 to form a plurality of bosses 18B, thereby obtaining a plurality of concavo-convex structures that are the bosses 18B.

[0153] In one embodiment, the above-mentioned plurality of channel structures 17 may be arranged in multiple rows in the first direction Y, and the above-mentioned plurality of concavo-convex structures may be arranged in at least one row in the first direction Y.

[0154] Specifically, the interval distance in the first direction Y between a row of concavo-convex structures adjacent to the stacked regions K1 / K2 in the above-mentioned at least one row of concavo-convex structures and a row of channel structures adjacent to the gate line gap region GLS in the above-mentioned multiple rows of channel structures may be equal to the interval distance in the first direction Y between adjacent two rows of channel structures.

[0155] Wherein, the interval distance in the first direction Y between an adjacent row of concavo-convex structures and a row of channel structures may specifically be the interval distance in the first direction Y between the bottom of an adjacent row of concavo-convex structures and the bottom of a row of channel structures.

[0156] In this embodiment, the interval distance may refer to the center interval distance or the nearest edge interval distance. Wherein, the center interval distance and the nearest edge interval distance may specifically refer to the center interval distance at the end and the nearest edge interval distance at the end respectively, and the end may be the top away from the above-mentioned substrate 11.

[0157] In some embodiments, the cross-sectional area of the above-mentioned concavo-convex structure may be larger than the cross-sectional area of the channel structure 17. Specifically, the cross-sectional area of the concavo-convex structure and the cross-sectional area of the channel structure 17 may be respectively the cross-sectional area of the top of the concavo-convex structure and the cross-sectional area of the top of the channel structure 17.

[0158] Specifically, the maximum width of the above-mentioned concavo-convex structure in the first direction Y may be larger than its maximum width in the direction X perpendicular to the first direction Y.

[0159] In some embodiments, the above-mentioned multiple channel structures 17 may have the same outer diameter. Specifically, for example, the cross-sections of the above-mentioned multiple channel structures 17 may have the same shape and size. Among them, the outer diameter and cross-section of the channel structure 17 may be specifically the outer diameter and cross-section of the top of the channel structure 17.

[0160] In this embodiment, the same outer diameter, the same cross-sectional shape, and the same cross-sectional size may respectively refer to at least the same surface outer diameter, the same surface shape, and the same surface size. For example, the surface outer diameters at the ends far from the above-mentioned substrate 11 are the same, the surface shapes at the ends far from the above-mentioned substrate 11 are the same, and the surface sizes at the ends far from the above-mentioned substrate 11 are the same.

[0161] In some embodiments, the outer diameter, cross-sectional shape, and / or cross-sectional size of the above-mentioned channel structure 17 may remain unchanged from top to bottom, that is, the outer diameter, cross-sectional shape, and / or cross-sectional size of the above-mentioned channel structure 17 may be the same from top to bottom. In some other embodiments, the outer diameter (or inner diameter), cross-sectional shape, and / or cross-sectional size of the above-mentioned concavo-convex structure may also remain unchanged from top to bottom.

[0162] In some embodiments, the spacing distance in the first direction Y between any two adjacent channel structures 17, the spacing distance in the first direction Y between any two adjacent concavo-convex structures, and the spacing distance in the first direction Y between any adjacent channel structure 17 and concavo-convex structure may all be equal. Among them, the spacing distance may specifically refer to the central spacing distance at the top, or may specifically refer to the closest edge spacing distance at the top.

[0163] Moreover, the cross-sections of the above-mentioned channel structure 17 and the above-mentioned concavo-convex structure may have the same shape and size.

[0164] In a specific embodiment, the distances between the orthographic projection center points on the substrate 11 of any two adjacent channel structures 17, the distances between the orthographic projection center points on the substrate 11 of any two adjacent concavo-convex structures, and the distances between the orthographic projection center points on the substrate 11 of any adjacent channel structure 17 and concavo-convex structure may all be equal.

[0165] In some embodiments, the above three-dimensional memory may further include a gate line slit structure 19 located in the gate line slit 18.

[0166] It should be noted that the structures of the three-dimensional memory in this embodiment may refer to the specific implementation manners described in the above method embodiments, so details are not described herein again.

[0167] In the three-dimensional memory provided in this embodiment, during the process of etching the channel holes in the stacking region, virtual channel holes are etched in the gate line slit region at the same time, so that the etching materials (such as polymers) formed in the gate line slit region during the etching process can be more evenly distributed, rather than concentratedly entering the channel holes close to the gate line slit region, so as to effectively improve the problem of insufficient etching of the channel holes close to the gate line slit region, and further improve the performance of the finally formed three-dimensional memory.

[0168] Correspondingly, as Figure 24 shown, an embodiment of the present invention further provides a storage system 40, which includes a controller 41 and a three-dimensional memory 42. The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0169] Among them, the three-dimensional memory 42 may be the same as the three-dimensional memory described in any of the above embodiments, so details are not described herein again. The controller 41 can control the three-dimensional memory 42 through the channel CH, and the three-dimensional memory 42 can perform operations based on the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 can receive a command CMD and an address ADDR from the controller 41 through the channel CH and access the area selected from the memory cell array in response to the address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to the command on the area selected by the address.

[0170] In some embodiments, the storage system 40 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

[0171] In the storage system provided in this embodiment, during the process of etching to form channel holes in the stacked area, virtual channel holes are simultaneously etched in the gate line gap area, so that the etching materials (such as polymers) formed in the gate line gap area during the etching process can be more evenly distributed, rather than concentratedly entering the channel holes close to the gate line gap area, so as to effectively improve the problem of insufficient etching of the channel holes close to the gate line gap area, and further improve the performance of the finally formed three-dimensional memory.

[0172] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, comprising: forming a stacked structure on a substrate, the stacked structure including a plurality of stacked regions and gate line gap regions located between adjacent stacked regions in a first direction; forming a plurality of channel holes penetrating the stacked structure in the stacked regions, and forming a plurality of dummy channel holes penetrating the stacked structure in the gate line gap regions during the formation of the plurality of channel holes; forming a gate line slit penetrating the stacked structure in the gate line gap regions to remove the plurality of dummy channel holes and separate the stacked structures in adjacent stacked regions.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, the plurality of channel holes are arranged in multiple rows in the first direction, and the plurality of dummy channel holes include at least one row arranged in the first direction.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, the spacing distance between a row of dummy channel holes and a row of channel holes adjacent to it in the first direction is equal to the spacing distance between adjacent two rows of channel holes.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, the plurality of channel holes have the same aperture.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, the dummy channel holes and the channel holes have the same aperture, and the spacing distance between any two adjacent channel holes, the spacing distance between any two adjacent dummy channel holes, and the spacing distance between any adjacent one channel hole and one dummy channel hole are equal.

6. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, the forming of the plurality of channel holes penetrating the stacked structure in the stacked regions and the plurality of dummy channel holes penetrating the stacked structure in the gate line gap regions specifically includes: providing a mask plate, the mask plate including a first region and a second region distributed along the first direction, the mask plate in the first region having a plurality of first openings, and the mask plate in the second region having a plurality of second openings; etching the stacked structure according to the plurality of first openings to form a plurality of channel holes penetrating the stacked structure in the stacked regions, and etching the stacked structure according to the plurality of second openings to form a plurality of dummy channel holes penetrating the stacked structure in the gate line gap regions.

7. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, before forming the gate line slit penetrating the stacked structure in the gate line gap regions, further comprising: forming a dummy channel structure in the dummy channel holes; forming a channel structure in the channel holes.

8. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that, the forming of the dummy channel structure in the dummy channel holes specifically includes: forming a mask layer covering the channel holes and the dummy channel holes on the stacked structure; Etch the mask layer located on the gate line gap region to form a third opening, and the third opening exposes the virtual channel holes; Form a virtual channel structure in the virtual channel holes according to the third opening.

9. The method for manufacturing a three-dimensional memory according to claim 8, wherein, Before forming a mask layer covering the channel holes and the virtual channel holes on the stacked structure, it further includes: Form a protective layer on the inner walls of the channel holes and the virtual channel holes.

10. The method for manufacturing a three-dimensional memory according to claim 8, wherein, Before forming a channel structure in the channel holes, it further includes: Remove the mask layer located on the stacked area to expose the channel holes.

11. The method for manufacturing a three-dimensional memory according to claim 7, wherein, The forming of the gate line slit penetrating the stacked structure in the gate line gap region specifically includes: Removing the stacked structure and the virtual channel structure in the gate line gap region to form a gate line slit.

12. The method for manufacturing a three-dimensional memory according to claim 7, wherein, The material of the virtual channel structure is an insulating material.

13. A three-dimensional memory, wherein, includes: a substrate; a stacked structure located on the substrate, the stacked structure includes a plurality of stacked areas and a gate line gap region located between adjacent stacked areas in a first direction; a gate line slit penetrating the stacked structure in the gate line gap region, the gate line slit separates the stacked structures in adjacent stacked areas, and a plurality of concave and convex structures are formed on the bottom surface of the gate line slit; a plurality of channel structures penetrating the stacked structure in the stacked area, the dimension of the end of the concave and convex structure on the side of the bottom surface away from the gate line gap in the first direction is substantially the same as the dimension of the end of the channel structure on the side close to the substrate in the first direction.

14. The three-dimensional memory according to claim 13, wherein, The bottom surface of the gate line slit locally protrudes in a direction away from the substrate to form the plurality of concave and convex structures, and the concave and convex structures are bosses.

15. The three-dimensional memory according to claim 13, wherein, The bottom surface of the gate line slit locally protrudes towards the substrate into the substrate to form the plurality of concave and convex structures on the substrate, and the concave and convex structures are grooves.

16. The three-dimensional memory according to claim 13, wherein, The plurality of channel structures are arranged in multiple rows in the first direction, and the plurality of concave and convex structures are arranged in at least one row in the first direction.

17. The three-dimensional memory according to claim 16, wherein, The spacing distance in the first direction between a row of concave and convex structures adjacent to the stacked area in the at least one row of concave and convex structures and a row of channel structures adjacent to the gate line gap region in the multiple rows of channel structures is equal to the spacing distance in the first direction between adjacent two rows of channel structures.

18. The three-dimensional memory according to claim 13, Characterized in that, the plurality of channel structures have the same outer diameter.

19. The three-dimensional memory according to claim 13, characterized in that, the distance between any two adjacent channel structures in the first direction, the distance between any two adjacent concave-convex structures in the first direction, and the distance between any adjacent channel structure and concave-convex structure in the first direction are equal.

20. A storage system, characterized in that, the storage system includes a controller and the three-dimensional memory according to any one of claims 13 to 19, the controller is coupled to the three-dimensional memory and is configured to control the three-dimensional memory to store data.

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