Active discharge circuit and device

Abstract

The present application discloses an active discharge circuit and device. During the active discharge circuit's cessation of discharge, a first control circuit receives a first enable signal to control the discharge circuit to be disconnected, causing the first discharge device to stop discharging an energy storage device. A second control circuit receives a second enable signal to control the discharge circuit to be disconnected, causing the first discharge device to stop discharging the energy storage device. By controlling the discharge circuit to be disconnected using both the first and second control circuits, the purpose is to prevent one control circuit from failing and requiring the other control circuit to control the first discharge device to stop discharging the energy storage device. This prevents the first discharge device from being damaged by prolonged discharge, thereby ensuring the safety of the motor controller.

Description

Technical Field

[0001] The present application relates to active discharge technology, and in particular to an active discharge circuit and device. Background Art

[0002] After the existing motor controller is cut off from power and discharged, high voltage still exists inside the motor controller due to the presence of energy storage devices such as DC support capacitors. To prevent personal injury, after the motor controller is cut off from power, a special active discharge circuit must be switched on to quickly release the energy stored in the DC support capacitors in the motor controller to below the safe level.

[0003] Existing active discharge circuits typically include a discharge process and a stop-discharge process. During the stop-discharge process, the signal tube is controlled to conduct, lowering the MOS tube gate voltage, causing the discharge resistor to stop discharging the DC link capacitor. However, if the signal tube fails to conduct (i.e., fails to conduct), the discharge resistor will continue to discharge the DC link capacitor, overheating and burning the discharge resistor, seriously affecting the safety of the motor controller. Summary of the Invention

[0004] In order to solve the above technical problems, the present application hopes to provide an active discharge circuit and device.

[0005] The technical solution of this application is achieved as follows:

[0006] In a first aspect, an active discharge circuit is provided, comprising: a first control circuit, a second control circuit, and a discharge circuit; the discharge circuit comprising a switch device, a first discharge device, and an energy storage device; wherein a first end of the first control circuit serves as an input end for a first enable signal, and a second end of the first control circuit is connected to the first end of the switch device; a first end of the second control circuit serves as an input end for a second enable signal, and a second end of the second control circuit is connected to the first end of the switch device; a second end of the switch device is connected to the first end of the energy storage device, and a third end of the switch device is connected in series with the first discharge device and the second end of the energy storage device;

[0007] The first control circuit is used to control the switching device to be turned on or off based on the first enable signal, so that the first discharge device discharges or stops discharging the energy storage device;

[0008] When the first control circuit is configured to control the switching device to be disconnected based on the first enable signal and fails to do so, the second control circuit is configured to control the switching device to be disconnected based on the second enable signal.

[0009] In the above scheme, the active discharge circuit also includes a voltage source; the second control circuit includes: a first NPN transistor, a first NMOS transistor, a first capacitor and a first resistor; wherein the base of the first NPN transistor serves as the input end of the second enable signal; the collector of the first NPN transistor is connected to the voltage source through the first resistor, and is also connected to the gate of the first NMOS transistor; the emitter of the first NPN transistor is grounded; the first capacitor is connected in parallel between the gate and source of the first NMOS transistor, and the source of the first NMOS transistor is grounded; and the drain of the first NMOS transistor is connected to the first end of the switching device.

[0010] In the above scheme, the second control circuit also includes: a second resistor, a third resistor and a fourth resistor; wherein the second resistor is connected to the base of the first NPN transistor; the third resistor is connected in parallel between the gate and source of the first NMOS transistor; and the drain of the first NMOS transistor is connected to the first end of the switching device through the fourth resistor.

[0011] In the above solution, the first enable signal is a high-level signal, and the second enable signal is a low-level signal, which turns off the switch device.

[0012] In the above solution, the discharge circuit further includes: a second discharge device connected in parallel at both ends of the first discharge device.

[0013] In the above scheme, the first discharge device is a first discharge resistor, and the second discharge device is a second discharge resistor and a PMOS transistor; the active discharge circuit also includes: a second NPN transistor; wherein the source of the PMOS transistor is connected in series with the second discharge resistor and the first end of the first discharge resistor, and is also connected to the third end of the switching device; the drain of the PMOS transistor is connected to the second end of the first discharge resistor and is also connected to a voltage source; the gate of the PMOS transistor is connected to the collector of the second NPN transistor, the base of the second NPN transistor is connected to the emitter, the emitter of the second NPN transistor is grounded, and the base of the second NPN transistor serves as the input end of the third enable signal.

[0014] In the above solution, the active discharge circuit further includes: a fifth resistor and a sixth resistor; wherein the fifth resistor is connected to the base of the second NPN transistor, and the sixth resistor is connected in parallel between the drain and gate of the PMOS transistor.

[0015] In the above solution, the first enable signal is a low-level signal, the second enable signal is a high-level signal, and the third enable signal is a high-level signal, so that the switch device is turned on.

[0016] In the above solution, the first discharge device further includes: a fifth resistor and a sixth resistor; wherein the fifth resistor is connected to the base of the second NPN transistor, and the sixth resistor is connected in parallel between the drain and the gate of the PMOS transistor.

[0017] In the above solution, the switching device includes: a seventh resistor and a second NMOS transistor; the energy storage device is a second capacitor; wherein the gate of the second NMOS transistor is connected to the second end of the first control circuit, the drain of the second NPMOS transistor is connected in series with the first discharge device, then connected to the second end of the second capacitor, and also connected to a voltage source; the source of the second NPMOS transistor is connected to the first end of the second capacitor, the source of the second NPMOS transistor is grounded, and the seventh resistor is connected in parallel between the gate and source of the second NPMOS transistor.

[0018] In the above scheme, the first control circuit includes: a third NPN transistor, an eighth resistor and a ninth resistor; wherein the base of the third NPN transistor is connected in series with the eighth resistor as the input end of the first enable signal; the emitter of the third NPN transistor is grounded; the collector of the third NPN transistor is connected to the voltage source through the ninth resistor, and is also connected to the first end of the switching device.

[0019] In a second aspect, an active discharge device is provided, which includes: any active discharge circuit in the above embodiments.

[0020] The present application discloses an active discharge circuit and device. In the present application, the discharge circuit is controlled to be in an off state by means of a first control circuit, and the discharge circuit can also be controlled to be in an off state by means of a second control circuit. This is to prevent the first discharge device from stopping discharging the energy storage device by means of the other control circuit when one of the control circuits fails, thereby preventing the first discharge device from being burned out due to being in a discharge state for a long time and ensuring the safety of the motor controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of an active discharge circuit in the prior art;

[0022] Figure 2 This is a schematic diagram of the first component structure of the active discharge circuit in an embodiment of the present application;

[0023] Figure 3 This is a schematic diagram of the second component structure of the active discharge circuit in an embodiment of the present application;

[0024] Figure 4 Schematic diagram of the third component structure of the active discharge circuit in the embodiment of the present application;

[0025] Figure 5This is a timing diagram of the voltage signals of EN1, EN2 and NMOS2 in the embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0027] Figure 1 FIG. 1 is a schematic diagram of the structure of an active discharge circuit in the prior art. Figure 1 As shown, the active discharge circuit in the prior art includes: a triode NPN tube, a field effect tube NPN tube, resistors R00, R01, R02, R03, a capacitor C0 and a voltage source VDC; wherein, the base of the NPN tube is connected in series with R03 as the input end of the enable signal EN0, the emitter of the NPN tube is grounded, the collector of the NPN tube is connected to VDC through R01, the collector of the NPN tube is also connected to the gate of the NMOS tube, R02 is connected in parallel between the gate and source of the NMOS tube, the source of the NMOS tube is grounded, the drain of the NMOS tube is connected in series with R00 and VDC, and the drain of the NMOS tube is connected in series with R00 and in parallel with C0.

[0028] Here, when discharging stops, EN0 is a high-level signal, the NPN transistor is turned on, pulling down the voltage of the NMOS transistor, and the NMOS transistor is turned off. No current flows through R00, that is, the R00 discharge resistor stops discharging C0. Among them, R01, R02, and R03 are signal resistors.

[0029] However, when the NPN tube fails to open circuit, that is, it cannot conduct, the voltage of the NMOS tube is pulled up, the NMOS tube is continuously conducted, R00 continues to discharge C0, R00 overheats and burns, seriously affecting the safety of the motor controller.

[0030] In this regard, an embodiment of the present application proposes an active discharge circuit. Figure 2 Schematic diagram of the first component structure of the active discharge circuit in an embodiment of the present application.

[0031] like Figure 2As shown, the active discharge circuit includes: a first control circuit 20, a second control circuit 21 and a discharge circuit 22; the discharge circuit 22 includes a switch device 23, a first discharge device 24 and an energy storage device 25; wherein, the first end of the first control circuit 20 serves as the input end of the first enable signal, and the second end of the first control circuit 20 is connected to the first end of the switch device 23; the first end of the second control circuit 21 serves as the input end of the second enable signal, and the second end of the second control circuit 21 is connected to the first end of the switch device 23; the second end of the switch device 23 is connected to the first end of the energy storage device 25, and the third end of the switch device 23 is connected in series with the first discharge device 24 and the second end of the energy storage device 25;

[0032] The first control circuit 20 is used to control the switch device 23 to be turned on or off based on the first enable signal, so that the first discharge device 24 discharges or stops discharging the energy storage device 25;

[0033] When the first control circuit 20 fails to control the switch device 23 to be disconnected based on the first enable signal, the second control circuit 21 is used to control the switch device 23 to be disconnected based on the second enable signal.

[0034] It should be noted that each module of the active discharge circuit also includes other matching components, such as one or more combinations of resistors, transistors, field-effect transistors, and capacitors. When the first discharge device 24 stops discharging the energy storage device 25, the present application designs two control circuits to control the switch device 23 to be in an off state, so that no current passes through the first discharge device 24, and the first discharge device 24 stops discharging the energy storage device 25. Specifically, the first control circuit 20 controls the switch device 23 to be in an off state based on the first enable signal, no current passes through the first discharge device 24, and the first discharge device 24 stops discharging the energy storage device 25. The second control circuit 21 controls the switch device 23 to be in an off state based on the second enable signal, no current passes through the first discharge device 24, and the first discharge device 24 stops discharging the energy storage device 25. Among them, the first enable signal and the second enable signal are signals of different levels.

[0035] Here, the present application achieves the purpose of stopping the first discharge device 24 from discharging the energy storage device 25 by designing two control circuits. This is to avoid the problem of affecting the safety of the motor controller when only one control circuit fails to stop the discharge process. The other control circuit can be used to control the switch device 23 to be in the off state. No current flows through the first discharge device 24, and the first discharge device 24 stops discharging the energy storage device 25. This prevents the first discharge device 24 from being burned due to being in the discharge state for a long time, thereby ensuring the safety of the motor controller. If both control circuits are effective, they both control the switch device 23 to be in the off state at the same time.

[0036] Using the above technical solution, the present application utilizes a first control circuit to control the switch device to be in the off state, thereby stopping the first discharge device from discharging the energy storage device. Furthermore, a second control circuit can be used to control the switch device to be in the off state, thereby stopping the first discharge device from discharging the energy storage device. This design prevents failure of one control circuit by enabling the other control circuit to stop the first discharge device from discharging the energy storage device. This prevents the first discharge device 24 from burning out due to prolonged discharge, thereby ensuring the safety of the motor controller.

[0037] Based on the above embodiment, when the first discharge device stops discharging the energy storage device, the embodiment of the present application specifically provides an active discharge circuit. Figure 3 Schematic diagram of the second component structure of the active discharge circuit in the embodiment of the present application.

[0038] like Figure 3 As shown, the active discharge circuit further includes a voltage source VDC; the second control circuit includes: a first NPN transistor NPN1, a first NMOS transistor NMOS1, a first capacitor C1 and a first resistor R1;

[0039] Among them, the base of the NPN1 transistor (i.e., the first end of the second control circuit) serves as the input end of the second enable signal EN2; the collector of the NPN1 transistor is connected to VDC through R1, and the collector of the NPN1 transistor is also connected to the gate of the NMOS1 transistor; the emitter of the NPN1 transistor is grounded; C1 is connected in parallel between the gate and source of the NMOS1 transistor, and the source of the NMOS1 transistor is grounded; the drain of the NMOS1 transistor (i.e., the second end of the second control circuit) is connected to the first end of the switching device.

[0040] In some embodiments, the second control circuit further includes: a second resistor R2, a third resistor R3 and a fourth resistor R4; wherein R2 is connected to the base of the NPN1 tube; R3 is connected in parallel between the gate and source of the NMOS1 tube; and the drain of the NMOS1 tube is connected to the first end of the switching device through R4.

[0041] In some embodiments, the switching device includes: a seventh resistor R7 and a second NMOS transistor NMOS2; the energy storage device is a second capacitor C2; the first discharge device includes R11, R11 is a discharge resistor; wherein, the gate of the NMOS2 transistor (i.e., the first end of the switching device) is connected to the second end of the first control circuit; the drain of the NMOS2 transistor (i.e., the third end of the switching device) is connected in series with R11 and then connected to the second end of C2, the source of the NMOS2 transistor (i.e., the second end of the switching device) is connected to the first end of C2, the source of the NMOS2 transistor is grounded, and R7 is connected in parallel between the gate and source of the NMOS2 transistor.

[0042] In some embodiments, the first control circuit includes: a third NPN transistor NPN3, an eighth resistor R8 and a ninth resistor R9; wherein the base of the NPN3 transistor (i.e., the first end of the first control circuit) is connected in series with R8 as the input end of the first enable signal; the emitter of the NPN3 transistor is grounded; the collector of the NPN3 transistor (i.e., the second end of the first control circuit) is connected to VDC through R9, and the collector of the NPN3 transistor is also connected to the first end of the switching device.

[0043] based on Figure 3 As shown in the figure, when EN1 is a high-level signal, NPN3 turns on, lowering the voltage of NMOS2. NMOS2 turns off, and no current flows through discharge resistor R11, stopping R11 from discharging C2. Simultaneously, when EN2 is a low-level signal, NPN1 turns off, raising the voltage of NMOS1. NMOS1 turns on, lowering the voltage of NMOS2. NMOS2 turns off, and no current flows through discharge resistor R11, stopping R11 from discharging C2. R1, R2, R3, R4, R7, R8, and R9 are signal resistors.

[0044] EN1 is a high-level signal. If the NPN3 transistor cannot conduct, the voltage of the NMOS2 transistor is pulled up, and the NMOS2 transistor is turned on. Current continues to flow through the R11 discharge resistor, and R11 continues to discharge C2, which may cause R11 to overheat and burn, affecting the safety of the motor controller. To address this, the present application provides a low-level signal to EN2, which turns off the NPN1 transistor, pulls up the voltage of the NMOS1 transistor, turns on the NMOS1 transistor, and pulls down the voltage of the NMOS2 transistor, turning off the NMOS2 transistor. No current flows through the R11 discharge resistor, so that R11 stops discharging C2, ensuring that the R11 discharge resistor will not burn and the safety of the motor controller is guaranteed.

[0045] Here, when R11 stops discharging C2 with the help of the second control circuit, the time when NMOS2 is turned off can be adjusted by adjusting the parameters of R1 and C1. Specifically, EN2 is a low-level signal, the NPN1 tube is turned off, and VDC charges the charging circuit composed of R1 and C1. When charging is completed, the NMOS1 tube is enabled, that is, the NMOS1 tube is turned on and the NMOS2 tube is turned off, so that R11 stops discharging C2. For example, if it takes 5 seconds for the charging circuit composed of R1 and C1 to be fully charged, that is, the NMOS1 tube is turned on after 5 seconds, then the NMOS2 tube is turned off after 5 seconds, that is, R11 stops discharging C2 after 5 seconds.

[0046] Using the above technical solution, the present application utilizes a first control circuit to control the discharge circuit to be in an off state, thereby stopping the first discharge device from discharging the energy storage device. Furthermore, a second control circuit can be used to control the discharge circuit to be in an off state, thereby stopping the first discharge device from discharging the energy storage device. This design prevents the NPN3 transistor in the first control circuit from failing (i.e., failing to conduct) due to an open circuit. This second control circuit can be used to stop R11 from discharging C1, thereby preventing R11 from burning out and ensuring the safety of the motor controller.

[0047] Based on the above embodiment, the first control circuit is used to control the conduction of the switching device based on the first enable signal, so that when the first discharge device discharges the energy storage device, EN1 is a low-level signal, the NPN3 tube is cut off, the voltage of the NMOS2 tube is pulled up, the NMOS2 tube is turned on, and a current flows through R11, causing R11 to discharge C1. When EN2 is a high-level signal, the NPN1 tube is turned on, the voltage of the NMOS1 tube is pulled down, the NMOS1 tube is turned on, the voltage of the NMOS2 tube is pulled up, the NMOS2 tube is turned on, and a current flows through R11, causing R11 to discharge C1. However, if the discharge resistor R11 is burned out after long-term use, R11 will not be able to discharge C1, affecting the safety of the motor controller. In response to this, the present application proposes an active discharge circuit that can still complete the discharge of C1 even if R11 is burned out.

[0048] Figure 4 FIG. 1 is a schematic diagram of a third component structure of the active discharge circuit in an embodiment of the present application. Figure 4 As shown, the discharge circuit further includes: a second discharge device connected in parallel across the first discharge device, wherein the first discharge device is a first discharge resistor R11, and the second discharge device is a second discharge resistor R12 and a PMOS transistor; the active discharge circuit further includes: a second NPN transistor NPN2; wherein the source of the PMOS transistor is connected in series with R12 to the first end of R11 (i.e., the first end of the first discharge device), and is also connected to the third end of the switch device (i.e., the drain of the PMOS transistor); the drain of the PMOS transistor is connected to the second end of R11 (i.e., the second end of the first discharge device), and is also connected to VDC; the gate of the PMOS transistor is connected to the collector of the NPN2 transistor, the base of the NPN2 transistor is connected to the emitter, the emitter of the NPN2 transistor is grounded, and the base of the NPN2 transistor serves as the input end of the third enable signal EN3.

[0049] In some embodiments, the active discharge circuit further includes: a fifth resistor R5 and a sixth resistor R6; wherein R5 is connected to the base of the NPN2 transistor, and R6 is connected in parallel between the drain and gate of the PMOS transistor. Here, R5 and R6 are signal resistors.

[0050] based on Figure 4As shown in the figure, during the discharge process, EN3 is a high-level signal, NPN2 is turned on, the voltage of the PMOS tube is pulled down, the PMOS tube is turned on, and current flows through R12. In this way, even if R11 burns out and no current flows, by forcibly opening R12, R12 is used to discharge C2, ensuring the normal discharge process and the safety of the motor controller.

[0051] Here, if R11 is not burned, when current flows through, R11 and R12 jointly discharge C2.

[0052] Here, the resistance value of R12 can be adjusted according to different projects, making the discharge time of the discharge resistor (including R11 and / or R12) more flexible. Specifically, when the resistance value of the discharge resistor is smaller, the current flowing through it is larger and the discharge time is shortened.

[0053] By adopting the above technical solution, during the discharge process, if R11 burns out and no current flows, R12 is forced to open and used to discharge C2, thereby ensuring the normal discharge process and the safety of the motor controller.

[0054] Based on the above embodiment, the embodiment of the present application also provides a timing diagram of the voltage signals of EN1, EN2 and NMOS2, Figure 5 This is a timing diagram of the voltage signals of EN1, EN2 and NMOS2 in the embodiment of the present application, as shown in FIG. Figure 5 As shown, during the discharge process, EN1 is a low-level signal, EN2 is a high-level signal, and NMOS2 is a high-level signal; during the stop-discharge process, EN1 is a high-level signal, EN2 is a low-level signal, and NMOS2 is a low-level signal.

[0055] An embodiment of the present application further discloses an active discharge device, which includes: an active discharge circuit according to any one of the above embodiments of the present application.

[0056] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An active discharge circuit, characterized in that: The active discharge circuit includes: a first control circuit, a second control circuit and a discharge circuit; the discharge circuit includes a switch device, a first discharge device and an energy storage device; Wherein, the first end of the first control circuit serves as the input end of the first enable signal, and the second end of the first control circuit is connected to the first end of the switching device; the first end of the second control circuit serves as the input end of the second enable signal, and the second end of the second control circuit is connected to the first end of the switching device; the second end of the switching device is connected to the first end of the energy storage device, and the third end of the switching device is connected in series with the first discharge device and the second end of the energy storage device; The first control circuit is used to control the switching device to be turned on or off based on the first enable signal, so that the first discharge device discharges or stops discharging the energy storage device; When the first control circuit is used to control the switching device to be disconnected based on the first enable signal and fails, the second control circuit is used to control the switching device to be disconnected based on the second enable signal; The active discharge circuit further includes a voltage source; the second control circuit includes: a first NPN transistor, a first NMOS transistor, a first capacitor, and a first resistor; wherein the base of the first NPN transistor serves as the input end of the second enable signal; the collector of the first NPN transistor is connected to the voltage source via the first resistor and is also connected to the gate of the first NMOS transistor; the emitter of the first NPN transistor is grounded; the first capacitor is connected in parallel between the gate and source of the first NMOS transistor, and the source of the first NMOS transistor is grounded; the drain of the first NMOS transistor is connected to the first end of the switching device; The switching device includes: a seventh resistor and a second NMOS transistor; the energy storage device is a second capacitor; wherein the gate of the second NMOS transistor is connected to the second end of the first control circuit, the drain of the second NMOS transistor is connected in series with the first discharge device, and then connected to the second end of the second capacitor, and is also connected to a voltage source; the source of the second NMOS transistor is connected to the first end of the second capacitor, the source of the second NMOS transistor is grounded, and the seventh resistor is connected in parallel between the gate and source of the second NMOS transistor.

2. The circuit according to claim 1, wherein: The second control circuit further includes: a second resistor, a third resistor and a fourth resistor; Among them, the second resistor is connected to the base of the first NPN transistor; the third resistor is connected in parallel between the gate and source of the first NMOS transistor; the drain of the first NMOS transistor is connected to the first end of the switching device through the fourth resistor.

3. The circuit according to claim 1, wherein: The first enable signal is a high level signal, and the second enable signal is a low level signal, which turns off the switch device.

4. The circuit according to claim 1, wherein: The discharge circuit further includes a second discharge device connected in parallel at both ends of the first discharge device.

5. The circuit according to claim 4, characterized in that The first discharge device is a first discharge resistor, and the second discharge device is a second discharge resistor and a PMOS tube; The active discharge circuit further includes: a second NPN transistor; The source of the PMOS transistor is connected to the first end of the first discharge resistor via the second discharge resistor, and is also connected to the third end of the switch device; the drain of the PMOS transistor is connected to the second end of the first discharge resistor, and is also connected to a voltage source; The gate of the PMOS tube is connected to the collector of the second NPN tube, the base of the second NPN tube is connected to the emitter, the emitter of the second NPN tube is grounded, and the base of the second NPN tube serves as the input end of the third enable signal.

6. The circuit according to claim 5, characterized in that The active discharge circuit further includes: a fifth resistor and a sixth resistor; The fifth resistor is connected to the base of the second NPN transistor, and the sixth resistor is connected in parallel between the drain and the gate of the PMOS transistor.

7. The circuit according to claim 5, characterized in that The first enable signal is a low level signal, the second enable signal is a high level signal, and the third enable signal is a high level signal, which turns on the switch device.

8. The circuit according to claim 1, wherein: The first control circuit includes: a third NPN transistor, an eighth resistor and a ninth resistor; Among them, the base of the third NPN tube is connected in series with the eighth resistor as the input end of the first enable signal; the emitter of the third NPN tube is grounded; the collector of the third NPN tube is connected to the voltage source through the ninth resistor, and is also connected to the first end of the switching device.

9. An active discharge device, characterized in that: The active discharge device comprises: The active discharge circuit according to any one of claims 1 to 8.

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