Multi-stage amplifier circuit

Abstract

A multi-stage amplifier circuit includes a pre-stage amplifier circuit and a floating control circuit. The pre-stage amplifier circuit is used to amplify the voltage difference at the input end and generate corresponding pre-stage transduction currents at multiple pre-stage transduction nodes. The floating control circuit is coupled to the multiple pre-stage transduction nodes. The floating control circuit includes a floating reference transistor coupled as a source follower, and a floating amplifier. The floating amplifier and the floating reference transistor are coupled in a feedback manner and generate an upper side drive signal and a lower side drive signal in a feedback manner according to a floating reference level inside the floating control circuit, wherein there is a preset voltage difference between the upper side drive signal and the lower side drive signal. The floating control circuit is floating corresponding to the multiple pre-stage transduction nodes.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, in particular to a multi-stage amplifier circuit with output stage floating control. The present invention also relates to an output stage floating control circuit in the multi-stage amplifier circuit. Background Art

[0002] Figure 1 A conventional multi-stage amplifier circuit (multi-stage amplifier circuit 101) is disclosed. The pre-stage amplifier circuit 70 of the multi-stage amplifier circuit 101 is an operational transconductance amplifier (OTA) that amplifies the voltage difference between a first input terminal IN1 and a second input terminal IN2 to generate a pre-stage output signal VO1. Subsequently, a shift circuit 80, biased by a power supply and a fixed bias current, generates an upper drive signal DRU and a lower drive signal DRL based on the pre-stage output signal VO1. These signals are used to drive an upper transistor MN1 and a lower transistor MP1 in an output stage circuit 90, respectively.

[0003] Figure 2 A conventional multi-stage amplifier circuit (multi-stage amplifier circuit 102) is disclosed. Multi-stage amplifier circuit 102 is similar to multi-stage amplifier circuit 101. A shift circuit 80', comprising a source-follower-connected transistor MN2 and a diode-connected shift transistor MP2, shifts a previous-stage output signal VO1 to generate an upper drive signal DRU and a lower drive signal DRL.

[0004] Figure 1 and Figure 2 The disadvantage of conventional multi-stage amplifier circuits is that the addition of a shift circuit creates an additional parasitic pole, which affects the overall bandwidth of the multi-stage amplifier circuit. Furthermore, when the upper transistor MN1 and the lower transistor MN2 in the output stage are relatively large, the fixed bias current in the shift circuit must be significantly increased to maintain the stability of the multi-stage amplifier circuit, which in turn increases the power consumption of the multi-stage amplifier circuit. Furthermore, the use of a shift circuit to offset the gate-source voltages of the upper transistor MN1 and the lower transistor MN2 can affect the output amplitude and potentially increase distortion due to the mismatch between the gate-source voltages.

[0005] For other related prior art, see “A compact power-efficient 3VCMOS rail-to-rail input / output operational amplifier for VLSI cell libraries, R. Hogervorst,” “Current gain high-frequency CMOS operational amplifiers, M. Milkovic,” “Datasheet of AD829, Analog Devices,” “A high-performance micropower switched-capacitor filter, R. Castello,” US Pat. No. 6,333,623, and “Analog Design Essentials, Willy Sansen.”

[0006] Compared to the prior art, the present invention has a substantially completely floating output stage floating control circuit. In addition to being able to precisely control the upper and lower side transistors of the output stage, it also does not cause additional bandwidth loss. Furthermore, under the architecture of the present invention, an AC positive feedback acceleration loop is also included, which can further improve the overall response speed of the multi-stage amplifier circuit without affecting stability. Furthermore, the multi-stage amplifier circuit of the present invention can operate at a lower current, thereby significantly saving power consumption compared to the prior art. Summary of the Invention

[0007] From one viewpoint, the present invention provides a multi-stage amplifier circuit, comprising: a pre-stage amplifier circuit for amplifying the voltage difference between a first input terminal and a second input terminal and generating corresponding multiple pre-stage transduction currents at multiple pre-stage transduction nodes, the multiple pre-stage transduction currents including a first pre-stage transduction current and a second pre-stage transduction current that are in phase with each other; and a floating control circuit for generating an upper drive signal and a lower drive signal according to the first pre-stage transduction current and the second pre-stage transduction current, wherein the floating control circuit comprises a first sub-floating control circuit and a second sub-floating control circuit coupled to each other, for generating a first sub-floating control signal and a second sub-floating control signal, respectively, the first sub-floating control signal and the second sub-floating control signal corresponding to the upper drive signal and the lower drive signal, respectively. one of the signals and another; wherein the first sub-floating control circuit includes: a first floating reference transistor, receiving the first previous stage transduction current and coupled as a source follower; and a first floating amplifier, coupled to the first floating reference transistor in a feedback manner, generating the first sub-floating control signal in a feedback manner according to a floating reference level inside the floating control circuit, the first sub-floating control signal controlling the gate of the first floating reference transistor, wherein the floating reference level is generated according to the second previous stage transduction current; wherein the first sub-floating control signal and the second sub-floating control signal are floating relative to the voltage of the multiple previous stage transduction nodes, and there is a preset voltage difference between the first sub-floating control signal and the second sub-floating control signal, wherein the preset voltage difference is related to the gate-source voltage of the first floating reference transistor.

[0008] In a preferred embodiment, the preset voltage difference is determined according to the first front-stage transduction current.

[0009] In a preferred embodiment, the first sub-floating control circuit is configured to be one of the following options: (1A) the first floating amplifier adjusts the drain voltage of the first floating reference transistor through feedback so that it is positively correlated with the floating reference level inside the floating control circuit, thereby generating the first sub-floating control signal; or (2A) the first floating amplifier adjusts the source voltage of the first floating reference transistor through feedback so that it is positively correlated with the floating reference level inside the floating control circuit, thereby generating the first sub-floating control signal.

[0010] In a preferred embodiment, the power supply and bias current of the first floating amplifier are generated from other pre-stage transduction currents except the first pre-stage transduction current among the plurality of pre-stage transduction currents.

[0011] In a preferred embodiment, the first sub-floating control circuit is configured as option (1A); the first floating amplifier includes a first floating amplifier transistor, the first floating amplifier transistor is configured as a source follower and is biased by the second pre-stage transduction current, the gate of the first floating amplifier transistor is used to receive the drain voltage of the first floating reference transistor for feedback control, and the first sub-floating control signal is generated at the source of the first floating amplifier transistor; the source of the first floating amplifier transistor receives the second pre-stage transduction current and generates the floating reference level.

[0012] In a preferred embodiment, all common-mode voltages of the floating control circuit respond in phase with the voltages of the plurality of previous-stage transduction nodes.

[0013] In a preferred embodiment, the floating control circuit forms a super node relative to the plurality of previous stage transduction nodes.

[0014] In a preferred embodiment, the floating control circuit also includes a compensation capacitor coupled between a first internal node and a second internal node inside the first floating amplifier; wherein relative to the outside of the first floating amplifier, the common-mode voltage on the first internal node and the common-mode voltage of the second internal node are respectively determined according to two same-phase pre-stage transduction currents among the multiple pre-stage transduction currents, and both respond in phase to the voltages of the multiple pre-stage transduction nodes; and relative to the inside of the first floating amplifier, the first internal node and the second internal node respond in anti-phase.

[0015] In a preferred embodiment, the transient response bandwidth of the floating control circuit is lower than the transient response bandwidth of the multi-stage amplifier circuit.

[0016] In a preferred embodiment, the floating control circuit also includes: a synchronous amplifier for generating a synchronous amplified signal based on one of the upper drive signal or the lower drive signal; and a feedback capacitor for coupling the synchronous amplified signal to the other of the upper drive signal or the lower drive signal; wherein the synchronous amplifier, the feedback capacitor and the first sub-floating control circuit form a voltage positive feedback path to accelerate the in-phase response of the upper drive signal and the lower drive signal, thereby accelerating the transient response of the multi-stage amplifier circuit.

[0017] In a preferred embodiment, the synchronous amplifier includes: a synchronous transistor, which is biased by a third pre-stage transduction current among the multiple pre-stage transduction currents, and the synchronous transistor is coupled as a source follower, whose gate receives one of the upper side drive signal or the lower side drive signal, and generates the synchronous amplified signal at its source; wherein the synchronous transistor, the feedback capacitor and the first sub-floating control circuit form the voltage positive feedback path.

[0018] In a preferred embodiment, the multi-stage amplifier circuit further includes an output stage circuit for generating an amplified output signal based on the upper drive signal and the lower drive signal. The output stage circuit includes: an upper transistor and a lower transistor, coupled to form an AB-class output amplifier circuit in a source-follower coupler with their sources connected, wherein the upper transistor and the lower transistor are respectively controlled by the upper drive signal and the lower drive signal to generate the amplified output signal.

[0019] In a preferred embodiment, the second sub-floating control circuit is configured as one of the following: (1B) wherein the first sub-floating control circuit is configured as option (1A), wherein the second sub-floating control circuit includes: a second floating reference transistor receiving the first pre-stage conduction current and coupled as a source follower, wherein the source of the first floating reference transistor and the source of the second floating reference transistor are coupled to each other; and a second floating amplifier coupled to the second floating reference transistor in a feedback manner, generating the second sub-floating control signal in a feedback manner according to the floating reference level inside the floating control circuit to control the gate of the second floating reference transistor, wherein the second floating amplifier adjusts the drain voltage of the second floating reference transistor by feedback so that it is positively correlated with the floating reference level, thereby generating the second sub-floating control signal; (2B) wherein the first sub-floating control circuit is configured as option (2A), wherein the second sub-floating control circuit includes: a second floating reference transistor a transistor receiving the first pre-stage transduction current and coupled as a source follower, wherein the source of the first floating reference transistor and the source of the second floating reference transistor are coupled to each other; and a second floating amplifier coupled to the second floating reference transistor in a feedback manner, generating the second sub-floating control signal in a feedback manner according to the floating reference level inside the floating control circuit to control the gate of the second floating reference transistor, wherein the second floating amplifier adjusts the source voltage of the second floating reference transistor by feedback so that it is positively correlated with the floating reference level, thereby generating the second sub-floating control signal; (3B) wherein the first sub-floating control circuit is set to option (1A) or (2A), wherein the second sub-floating control circuit includes: a floating control transistor biased by the first pre-stage transduction current, whose gate and drain are coupled to each other, whose source is coupled to the source of the first floating reference transistor, and the drain of the floating control transistor is used to generate the second sub-floating control signal.

[0020] In a preferred embodiment, the quiescent currents of the upper transistor and the lower transistor are determined according to the bias current of a differential amplifier stage of the pre-amplifier circuit.

[0021] In a preferred embodiment, the pre-stage amplifier circuit includes multiple push-side branches and corresponding multiple pull-side branches, the floating control circuit is coupled between the multiple push-side branches and the multiple pull-side branches, and the floating control circuit is floating corresponding to the multiple push-side branches and the multiple pull-side branches, wherein the multiple pre-stage transduction currents also include a fourth pre-stage transduction current that is anti-phase with the first pre-stage transduction current, and a fifth pre-stage transduction current that is anti-phase with the second pre-stage transduction current, wherein the first pre-stage transduction current and the fourth pre-stage transduction current respectively correspond to the first push-side branch among the multiple push-side branches and the first pull-side branch among the multiple pull-side branches, and the second pre-stage transduction current and the fifth pre-stage transduction current respectively correspond to the second push-side branch among the multiple push-side branches and the second pull-side branch among the multiple pull-side branches.

[0022] In a preferred embodiment, the pre-stage amplifier circuit includes multiple push-side branches and corresponding multiple pull-side branches, the floating control circuit is coupled between the multiple push-side branches and the multiple pull-side branches, and the floating control circuit is floating corresponding to the multiple push-side branches and the multiple pull-side branches, wherein the pre-stage amplifier circuit includes a first load current and a second load current with fixed current values, wherein the first pre-stage transduction current and the first load current respectively correspond to the first push-side branch among the multiple push-side branches and the first pull-side branch among the multiple pull-side branches, and the second pre-stage transduction current and the second load current respectively correspond to the second push-side branch among the multiple push-side branches and the second pull-side branch among the multiple pull-side branches.

[0023] From another point of view, the present invention provides a multi-stage amplifier circuit, comprising: a pre-stage amplifier circuit for amplifying the voltage difference between a first input terminal and a second input terminal and generating corresponding multiple pre-stage transduction currents at multiple pre-stage transduction nodes, the multiple pre-stage transduction currents including a first pre-stage transduction current and a second pre-stage transduction current that are in phase with each other; and a floating control circuit for generating an upper side drive signal and a lower side drive signal according to the first pre-stage transduction current and the second pre-stage transduction current, wherein the floating control circuit comprises a first sub-floating control circuit and a second sub-floating control circuit coupled to each other, for generating a first sub-floating control signal and a second sub-floating control signal, respectively, the first sub-floating control signal and the second sub-floating control signal corresponding to the upper side drive signal respectively. The first sub-floating control signal and one of the lower-side driving signals and the other; wherein the first sub-floating control signal and the second sub-floating control signal are floating relative to the voltage of the multiple previous-stage transfer nodes, and there is a preset voltage difference between the first sub-floating control signal and the second sub-floating control signal; wherein the floating control circuit includes: a synchronous amplifier for generating a synchronous amplified signal according to one of the upper-side driving signal or the lower-side driving signal; and a feedback capacitor for coupling the synchronous amplified signal to the other of the upper-side driving signal or the lower-side driving signal; wherein the synchronous amplifier, the feedback capacitor and the first sub-floating control circuit form a voltage positive feedback path to accelerate the in-phase response of the upper-side driving signal and the lower-side driving signal, thereby accelerating the transient response of the multi-stage amplifier circuit.

[0024] In a preferred embodiment, the synchronous amplifier includes: a synchronous transistor, which is biased by a third pre-stage transduction current among the multiple pre-stage transduction currents, and the synchronous transistor is coupled as a source follower, whose gate receives one of the upper side drive signal or the lower side drive signal, and generates the synchronous amplified signal at its source; wherein the synchronous transistor, the feedback capacitor and the first sub-floating control circuit form the voltage positive feedback path.

[0025] In a preferred embodiment, the multi-stage amplifier circuit further includes an output stage circuit for generating an amplified output signal based on the upper drive signal and the lower drive signal, wherein the output stage circuit includes: an upper transistor and a lower transistor, coupled to form an AB-class output amplifier circuit in a source-follower coupler with their sources connected, wherein the upper transistor and the lower transistor are respectively controlled by the upper drive signal and the lower drive signal to generate the amplified output signal.

[0026] The following detailed description is made through specific embodiments, which should make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Disclosed is a multi-stage amplifier circuit of the prior art.

[0028] Figure 2 Disclosed is a multi-stage amplifier circuit of the prior art.

[0029] Figure 3 A schematic diagram showing an embodiment of a multi-stage amplifier circuit according to the present invention.

[0030] Figure 4 A schematic diagram showing an embodiment of a multi-stage amplifier circuit according to the present invention.

[0031] Figure 5 A schematic diagram showing an embodiment of a multi-stage amplifier circuit according to the present invention.

[0032] Figure 6A A schematic diagram showing a specific embodiment of a multi-stage amplifier circuit according to the present invention.

[0033] Figure 6B A schematic diagram showing a more specific embodiment of the multi-stage amplifier circuit according to the present invention.

[0034] Figure 7A and Figure 7B Schematic diagrams showing two embodiments of the multi-stage amplifier circuit according to the present invention.

[0035] Figure 8 A schematic diagram showing an embodiment of a multi-stage amplifier circuit according to the present invention.

[0036] Figure 9A and Figure 9B Schematic diagrams showing two embodiments of the multi-stage amplifier circuit according to the present invention.

[0037] Figure 10 A schematic diagram showing a specific embodiment of a multi-stage amplifier circuit according to the present invention.

[0038] Figures 11A and 11B Schematic diagrams showing two embodiments of a multi-stage amplifier circuit including floating diodes according to the present invention.

[0039] Figure 12 A schematic diagram showing a specific embodiment of a multi-stage amplifier circuit according to the present invention.

[0040] Explanation of symbols in the figure

[0041] 10: Preamplifier circuit

[0042] 11: Differential amplifier stage

[0043] 101~105,108,110,112: Multi-stage amplifier circuit

[0044] 106A~106B: Multi-stage amplifier circuit

[0045] 107A: Multi-stage amplifier circuit

[0046] 109A~109B: Multi-stage amplifier circuit

[0047] 111A~111B: Multi-stage amplifier circuit

[0048] 20: Floating control circuit

[0049] 21,22,21',22': Sub-floating control circuit

[0050] 23: Synchronous Amplifier

[0051] 211,211',221,221': floating amplifier

[0052] 30: Output stage circuit

[0053] 70: Preamplifier circuit

[0054] 80: Displacement Circuit

[0055] 90: Output stage circuit

[0056] CC: Compensation capacitor

[0057] CFB: Feedback capacitor

[0058] DRU,DRL: upper drive signal, lower drive signal

[0059] Ib: bias current

[0060] IU1-IUx, ID1-IDx,: pre-stage transduction current

[0061] ID1'~IDx': current load

[0062] IN1, IN2: input terminal

[0063] MAF1, MAF2: floating amplifier transistors

[0064] Md1, Md2: transistors

[0065] MFC1, MFC2: floating control transistors

[0066] Mm1, Mm1A, Mm1B, Mm11~Mm1x: transistors

[0067] Mm2, Mm21~Mm2x: transistors

[0068] MN1: upper transistor

[0069] MP1: bottom side transistor

[0070] MN2: Transistor

[0071] MP2: Transistor

[0072] MRF1, MRF2: Reference transistors

[0073] Msnc: Synchronous Transistor

[0074] ND1, ND2: internal nodes

[0075] NI1, NI2: internal nodes

[0076] NU1-NUx, ND1-NDx: pre-transduction nodes

[0077] PPFB: Voltage positive feedback path

[0078] SNC: Synchronous Amplification Signal

[0079] VBP,VBN: bias voltage

[0080] VD: preset voltage difference

[0081] VF, VF1, VF2: floating reference level

[0082] VO1: Preamplifier output signal

[0083] VOUT: amplified output signal DETAILED DESCRIPTION

[0084] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0085] Figure 3 A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (a multi-stage amplifier circuit 103 ) is shown. The multi-stage amplifier circuit 103 includes a pre-stage amplifier circuit 10 and a floating control circuit 20 .

[0086] The pre-amplifier circuit 10 is configured to transduce and amplify the voltage difference between the first input terminal IN1 and the second input terminal IN2, thereby generating a plurality of pre-stage transduction currents (IU1-IUx, ID1-IDx) corresponding to a plurality of branches at a plurality of pre-stage transduction nodes (NU1-NUx, ND1-NDx, where x is a positive integer greater than 1). It should be noted that, in a preferred embodiment, the pre-stage transduction currents IU1 and ID1 correspond to the push and pull currents of one branch, respectively; the pre-stage transduction currents IU2 and ID2 correspond to the push and pull currents of another branch, respectively; and so on.

[0087] Specifically, in one embodiment, transistors Md1 and Md2 are biased by bias current Ib to form a differential amplifier stage 11. Transistors Mm1, Mm1A, Mm1B, Mm11-Mm1x are used to generate multiple pre-stage transconductance currents on the pull side, while transistors Mm2, Mm21-Mm2x are used to generate multiple pre-stage transconductance currents on the push side, and the same applies hereinafter. In this embodiment, the pre-stage amplifier circuit 10 is a fully differential transconductance amplifier circuit. Furthermore, the other transistors biased by bias voltages VBP and VBN are cascaded transistors to increase the output impedance of each current branch. This is well known to those skilled in the art and will not be described in detail here.

[0088] The floating control circuit 20 is used to generate an upper drive signal DRU and a lower drive signal DRL according to the aforementioned multiple pre-stage transduction currents (IU1-IUx, ID1-IDx), wherein the floating control circuit 20 includes a first sub-floating control circuit 21 and a second sub-floating control circuit 22 coupled to each other, for respectively generating a first sub-floating control signal and a second sub-floating control signal. In this embodiment, the first sub-floating control signal and the second sub-floating control signal correspond to one and the other of the upper drive signal DRU and the lower drive signal DRL, respectively; as shown in the figure, in this embodiment, the first sub-floating control signal corresponds to the lower drive signal DRL, and the second sub-floating control signal corresponds to the upper drive signal DRU.

[0089] Please continue reading Figure 3 In one embodiment, the multi-stage amplifier circuit 103 further includes an output stage circuit 30 for generating an amplified output signal VOUT according to the upper driving signal DRU and the lower driving signal DRL.

[0090] Figure 4A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 104) is shown. In this embodiment, the multiple pre-stage transconductance currents include a first pre-stage transconductance current IU1 and a second pre-stage transconductance current IU2. The floating control circuit 20 is configured to generate an upper drive signal DRU and a lower drive signal DRL based on the first pre-stage transconductance current IU1 and ID1, and the second pre-stage transconductance current IU2 and ID2. In this embodiment, the first sub-floating control circuit 21 includes a floating reference transistor MRF1 and a floating amplifier 211. According to the present invention, the floating control circuit 20 can also generate the upper drive signal DRU and the lower drive signal DRL based on the first pre-stage transconductance current IU1 and the second pre-stage transconductance current IU2, without necessarily requiring the first pre-stage transconductance current ID1 and the second pre-stage transconductance current ID2. Details will be described later.

[0091] The floating reference transistor MRF1 receives the first pre-stage transduction current IU1 and is coupled as a source-follower. A floating amplifier 211 is coupled to the floating reference transistor MRF1 in a feedback manner. The floating amplifier 211 generates a first sub-floating control signal in a feedback manner based on a floating reference level VF within the floating control circuit 20. The first sub-floating control signal (corresponding to the low-side drive signal DRL in this embodiment) controls the gate of the first floating reference transistor MRF1. The floating reference level VF is generated based on the second pre-stage transduction current IU2.

[0092] Please continue reading Figure 4 In one embodiment, the second sub-floating control circuit 22 includes a floating reference transistor MRF2 and a floating amplifier 221. In one embodiment, the floating reference transistor MRF2 and the floating amplifier 221 in the second sub-floating control circuit 22 are coupled and controlled in a similar manner to generate a second sub-floating control signal (corresponding to the upper drive signal DRU in this embodiment). The floating reference transistor MRF2 is configured as a source follower, and the source of the floating reference transistor MRF2 and the source of the floating reference transistor MRF1 are coupled to the node NF1. In other embodiments, the second sub-floating control circuit 22 may also use other methods to generate the second sub-floating control signal.

[0093] Please continue reading Figure 4 In this embodiment, the first floating amplifier 211 adjusts the drain voltage of the first floating reference transistor MRF1 through feedback so that it is positively correlated with the floating reference level VF within the floating control circuit 20, thereby generating the first sub-floating control signal.

[0094] In this embodiment, the second floating amplifier 221 also adjusts the drain voltage of the second floating reference transistor MRF2 through feedback to be positively correlated with the floating reference level within the floating control circuit 20, thereby generating a second sub-floating control signal. In one embodiment, the drain voltage of the floating reference transistor MRF2 is positively correlated with the floating reference level VF.

[0095] In this embodiment, the first sub-floating control signal and the second sub-floating control signal float relative to the voltages of multiple previous-stage transduction nodes, and a predetermined voltage difference VD exists between the first sub-floating control signal and the second sub-floating control signal. In one embodiment, the predetermined voltage difference VD is related to the gate-source voltage of the first floating reference transistor MRF1 or the gate-source voltage of the second floating reference transistor MRF2. In one embodiment, the predetermined voltage difference VD is related to the sum of the gate-source voltage of the first floating reference transistor MRF1 and the gate-source voltage of the second floating reference transistor MRF2. As shown in the figure, in one embodiment, the predetermined voltage difference VD is determined based on the first previous-stage transduction current IU1.

[0096] Please continue reading Figure 4 In this embodiment, the output stage circuit 30 includes an upper transistor MN1 and a lower transistor MP1, which are coupled to form an AB-class output amplifier circuit in a source-follower manner with their source terminals connected. The upper transistor MN1 and the lower transistor MP1 are respectively controlled by an upper drive signal DRU and a lower drive signal DRL to generate an amplified output signal VOUT.

[0097] The following Figure 4 The operation of the present invention is further described in detail in the following embodiments. In one embodiment, the gate of the first floating reference transistor MRF1 is coupled to the gate of the bottom transistor MP1, and the sources of the first floating reference transistor MRF1 and the bottom transistor MP1 are coupled in the same direction. From one perspective, the first floating reference transistor MRF1 and the bottom transistor MP1 can be considered as a virtual current mirror in a steady state. In transient conditions, because a predetermined voltage difference VD exists between the upper drive signal DRU and the lower drive signal DRL (the first sub-floating control signal and the second sub-floating control signal), and the signals are floating relative to the voltages of multiple previous-stage transfer nodes, the upper transistor MN1 and the bottom transistor MP1 can be controlled to perform a push-pull operation to generate the amplified output signal VOUT.

[0098] In addition, it is worth noting that the above feedback method of adjusting the floating reference transistor and controlling the upper transistor MN1 and / or lower transistor MP1 of the output stage circuit 30 can increase the transient response speed and improve the stability of the multi-stage amplifier circuit.

[0099] Furthermore, according to the aforementioned configuration, the quiescent currents of the upper transistor MN1 and the lower transistor MP1 in the output stage circuit 30 are determined by the bias current Ib of the differential amplifier stage 11 of the pre-amplifier circuit 10 .

[0100] In addition, it should be noted that, in one embodiment, Figure 4 As shown, the upper transistor MN1 and the lower transistor MP1 are complementary transistors. Specifically, the upper transistor MN1 is an NMOS transistor, and the lower transistor MP1 is a PMOS transistor. In this case, the first floating reference transistor MRF1 corresponds to a PMOS transistor (used to control the P-type lower transistor MP1), and the second floating reference transistor MRF2 corresponds to an NMOS transistor (used to control the N-type upper transistor MN1).

[0101] Figure 5 A schematic diagram of another embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 105) is shown. In this embodiment, the first floating amplifier 211' adjusts the source voltage of the first floating reference transistor MRF1 through feedback so that it is positively correlated with the floating reference level VF within the floating control circuit 20, thereby generating a first sub-floating control signal (corresponding to the lower drive signal DRL). This embodiment is similar to Figure 4 Similarly, although the floating reference transistor is regulated at a different endpoint, all of the above control functions can still be achieved.

[0102] It should be noted that the floating amplifier (e.g., 211, 211') is used to adjust the source voltage or drain voltage of the floating reference transistor (e.g., MRF1) through feedback so that it is positively correlated with the floating reference level (e.g., VF) within the floating control circuit 20. In one embodiment, the positive input terminal and the negative input terminal of the floating amplifier can be locked to be equal. In another embodiment, a preset offset voltage can be provided between the positive input terminal and the negative input terminal of the floating amplifier, so that the source voltage or drain voltage of the floating reference transistor (e.g., MRF1) is adjusted to be positively correlated with, but not equal to, the floating reference level (e.g., VF).

[0103] In addition, if Figure 4 and Figure 5 As shown, the second floating amplifier 221 or 221' is configured in a manner similar and complementary to the first floating amplifier 211 and 211' to control the floating reference transistor MRF2 which is complementary to the floating reference transistor MRF1. In one embodiment, the above-mentioned floating amplifier configurations can be used in combination. For example, Figure 4 The first sub-floating control circuit can be matched with Figure 5 The second sub-floating control circuit, and so on.

[0104] Figure 6A A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 106A) is shown. In this embodiment, a first floating amplifier 211' includes a first floating amplifier transistor MAF1. The first floating amplifier transistor MAF1 is configured as a source follower and is biased by a second pre-stage transduction current IU2. The gate of the first floating amplifier transistor MAF1 receives the drain voltage of the first floating reference transistor MRF1 for feedback control, and a first sub-floating control signal (corresponding to DRL) is generated at the source of the first floating amplifier transistor MAF1. In this embodiment, the source of the first floating amplifier transistor MAF1 receives the second pre-stage transduction current IU2 and generates a floating reference level VF1.

[0105] In one aspect, the first floating amplifier transistor MAF1 in the multi-stage amplifier circuit 106A regulates the drain voltage of the first floating reference transistor MRF1 in a feedback manner so that the drain voltage thereof differs from the floating reference level VF1 by approximately the gate-source voltage difference of the first floating amplifier transistor MAF1 .

[0106] Figure 6B A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 106B) is shown. This embodiment is similar to the multi-stage amplifier circuit 106A, except that in the multi-stage amplifier circuit 106B, the second floating amplifier 221' is configured in a manner similar to and complementary to the first floating amplifier 211'. Figure 6B As shown, in this embodiment, the second floating amplifier 221' includes a second floating amplifier transistor MAF2, which is configured as a source follower and biased by the third pre-stage transduction current IU3, wherein the gate of the second floating amplifier transistor MAF2 is used to receive the drain voltage of the second floating reference transistor MRF2 for feedback control, and the second sub-floating control signal (corresponding to DRU) is generated at the source of the second floating amplifier transistor MAF2; in this embodiment, the source of the second floating amplifier transistor MAF1 receives the third pre-stage transduction current IU3 and generates a floating reference level VF2.

[0107] In one aspect, the second floating amplifier transistor MAF2 in the multi-stage amplifier circuit 106B regulates the drain voltage of the second floating reference transistor MRF2 in a feedback manner so that the drain voltage thereof differs from the floating reference level VF2 by a gate-source voltage difference of the second floating amplifier transistor MAF2.

[0108] In one embodiment, the power supply and bias current of the first floating amplifier 211' are generated from other pre-stage transconductance currents except the first pre-stage transconductance current IU1 among the plurality of pre-stage transconductance currents. Figure 6AFor example, the first floating amplifier transistor MAF1 in the first floating amplifier 211' is powered and biased by the second pre-stage conduction current IU2 to perform the aforementioned amplification adjustment function. Figure 6B For example, the second floating amplifying transistor MAF2 in the second floating amplifier 221 is powered and biased by the third pre-stage conduction current IU3 to perform the aforementioned amplification and adjustment function.

[0109] It should be noted that, in one embodiment, the aforementioned floating amplifier transistor MAF1 corresponds to a PMOS transistor, and the floating amplifier transistor MAF2 corresponds to an NMOS transistor.

[0110] From one perspective, all common-mode voltages in the floating control circuit 20 are determined by a plurality of pre-stage transduction currents. From another perspective, all common-mode voltages in the first floating amplifier 211 and the second floating amplifier 221 are determined by a plurality of pre-stage transduction currents. Figure 4 、 Figure 5 and Figures 6A-6B For example, the common-mode voltages at nodes NU1-NUx, ND1-NDx, and NF1-NFx are determined by the preceding-stage transconductance currents IU1-IUx and ID1-IDx, respectively. In fact, this characteristic also corresponds to the aforementioned concept of "the first sub-floating control signal and the second sub-floating control signal floating relative to the voltages of the multiple preceding-stage transconductance nodes." The common-mode voltage mentioned above refers to the common-mode voltage relative to the ground node of the multi-stage amplifier circuit.

[0111] Furthermore, the aforementioned common-mode voltage characteristics also provide the multi-stage amplifier circuit of the present invention with another characteristic: the floating control circuit 20 is floating relative to the aforementioned multiple preceding-stage transconductance nodes, or the floating control circuit 20 is floating relative to the aforementioned multiple preceding-stage transconductance currents. Therefore, from another perspective, the floating control circuit 20 forms a supernode relative to the aforementioned multiple preceding-stage transconductance nodes or the aforementioned multiple preceding-stage transconductance currents of the multiple branches. Specifically, the sum of all branch currents coupled to the floating control circuit 20 and outside the floating control circuit 20 is zero.

[0112] Furthermore, due to the aforementioned characteristics, the floating control circuit 20 and the multi-stage amplifier circuit of the present invention have the following characteristics: all common-mode voltages of the floating control circuit 20 respond in phase with the voltages of the multiple previous-stage transfer nodes.

[0113] Figure 7A and Figure 7BSchematic diagrams showing two embodiments of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuits 107A and 107B) are provided. In this embodiment, the floating control circuit 20 further includes a compensation capacitor CC coupled between a first internal node (e.g., ND1) and a second internal node (e.g., ND2) within the first floating amplifier 211. Relative to the exterior of the first floating amplifier 211, the common-mode voltage on the first internal node (e.g., ND1) and the common-mode voltage on the second internal node (e.g., ND2) are respectively determined by the pre-stage transconductance currents (e.g., IU1 and IU2) of two branches among the plurality of pre-stage transconductance currents, and both respond in phase to the voltages of the plurality of pre-stage transconductance nodes. Furthermore, in this embodiment, relative to the interior of the first sub-floating control circuit, the first internal node (e.g., ND1) and the second internal node (e.g., ND2) respond in anti-phase.

[0114] It should be noted that, relative to the voltage difference between the first input terminal IN1 and the second input terminal IN2, the pre-stage transduction currents of the various branches used to determine the common-mode voltage are all in phase. For example, the pre-stage transduction current IU1 and the pre-stage transduction current IU2 are in phase, or for example, the pre-stage transduction current ID1 and the pre-stage transduction current ID2 are in phase, or, from another point of view, the push-pull branch composed of the pre-stage transduction current IU1 and the pre-stage transduction current ID1 (IU1 is the push-side branch, ID1 is the pull-side branch) and the push-pull branch composed of the pre-stage transduction current IU2 and the pre-stage transduction current ID2 are in phase (IU2 is the push-side branch, ID2 is the pull-side branch).

[0115] Specifically, Figure 7A For example, the compensation capacitor CC is coupled between the first internal node ND1 and the second internal node ND2 inside the first floating amplifier 211, that is, coupled between the gate and drain of the first floating amplifier transistor MAF1 (that is, between the nodes ND1 and ND2). Relative to the interior of the first sub-floating control circuit, the gate and drain of the first floating amplifier transistor MAF1 respond in anti-phase. However, the gate-drain voltages of the first floating amplifier transistor MAF1 (that is, the internal nodes ND1 and ND2) all respond in phase to the voltage changes of the multiple pre-stage transduction nodes caused by the multiple pre-stage transduction currents (such as IU1, IU2).

[0116] The aforementioned features of the present invention can stabilize the internal structure of the floating control circuit 20 or a sub-floating control circuit (e.g., the first sub-floating control circuit 21), while still enabling the pre-stage amplifier circuit 10 to provide high-speed transient response control over the output stage circuit 30. In a preferred embodiment, the transient response bandwidth of the floating control circuit 20 can even be lower than that of a multi-stage amplifier circuit while still maintaining the aforementioned performance.

[0117] above Figure 7AThe specific embodiment is only an example. In other embodiments, such as Figure 7B As shown, the compensation capacitor CC in the sub-floating control circuit 21 is coupled between an internal node (e.g., NI1) and an internal node (e.g., NI2) within the first floating amplifier 211, and has the aforementioned common-mode in-phase and out-of-phase amplification responses, thereby achieving the aforementioned performance. Where IUx, IUy, IDx, and IDy represent the pre-stage transduction current associated with the first internal node (e.g., NI1) and the second internal node (e.g., NI2).

[0118] Figure 8 A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 108) is shown. In one embodiment, the floating control circuit 20 further includes a synchronous amplifier 23 and a feedback capacitor CFB. The synchronous amplifier 23 is configured to generate a synchronous amplified signal SNC based on either the upper drive signal DRU or the lower drive signal DRL. The feedback capacitor CFB is configured to couple the synchronous amplified signal SNC to the other of the upper drive signal DRU or the lower drive signal DRL.

[0119] Specifically, Figure 8 For example, synchronous amplifier 23 generates a synchronous amplified signal SNC based on the lower drive signal DRL. Feedback capacitor CFB couples synchronous amplified signal SNC to the upper drive signal DRU. Synchronous amplifier 23, feedback capacitor CFB, second sub-floating control circuit 22, and first sub-floating control circuit 21 form a voltage positive feedback path PPFB to accelerate the in-phase response of upper drive signal DRU and lower drive signal DRL, thereby accelerating the transient response of the multi-stage amplifier circuit.

[0120] Figures 9A and 9B and Figure 10 Schematic diagrams showing several more specific implementations of the multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuits 109A, 109B, 110). In one embodiment, as Figure 9A and Figure 9B As shown, the synchronous amplifier 23 includes a synchronous transistor Msnc, which is biased by the pre-stage transduction current IU4 among the multiple pre-stage transduction currents. The synchronous transistor Msnc is coupled as a source follower. In this embodiment, the gate of the synchronous transistor Msnc receives the low-side drive signal DRL, and generates a synchronous amplified signal SNC at its source, and feeds the synchronous amplified signal SNC to the high-side drive signal DRU through the feedback capacitor CFB, wherein the synchronous transistor Msnc, the feedback capacitor CFB, the second sub-floating control circuit 22 and the first sub-floating control circuit 21 form a voltage positive feedback path PPFB ( Figures 9A and 9B) to accelerate the in-phase response of the upper drive signal DRU and the lower drive signal DRL, thereby accelerating the transient response of the multi-stage amplifier circuit. More specifically, in this embodiment, the synchronous transistor Msnc, the feedback capacitor CFB, the second floating reference transistor MRF2 and the first floating reference transistor MRF1 form a voltage positive feedback path PPFB ( Figure 10 ).

[0121] Figures 11A and 11B Two schematic diagrams of multi-stage amplifier circuits according to the present invention including floating diodes are shown (multi-stage amplifier circuits 111A and 111B). In one embodiment, one of the sub-floating control circuits in the floating control circuit can be configured as a simpler shift circuit, such as a diode. Figures 11A and 11B For example, in these embodiments, the sub-floating control circuit (21' or 22') includes a diode-connected floating control transistor MFC1 or MFC2. The source of the floating control transistor MFC1 or MFC2 is coupled to the source of the floating reference transistor MRF1 or MRF2. The drain of the floating control transistor MFC1 or MFC2 is used to generate a corresponding sub-floating control signal. The gate-source voltage of the floating control transistor MFC1 or MFC2 is determined by the previous stage conduction current IU1.

[0122] Figure 12 A schematic diagram of an embodiment of a multi-stage amplifier circuit according to the present invention (multi-stage amplifier circuit 112) is shown. Figure 3 The embodiment is similar to the multi-stage amplifier circuit 103, with the difference being that, in this embodiment, the pre-stage amplifier circuit 10 is not a fully differential transconductance amplifier circuit. Specifically, in this embodiment, the pre-stage transconductance currents IU1-IUx are still generated by transconducting and amplifying the voltage difference between the first input terminal IN1 and the second input terminal IN2 in the pre-stage amplifier circuit 10, but the corresponding pull-side currents ID1'-IDx' are fixed current loads. This embodiment can still generate the aforementioned upper drive signal DRU and lower drive signal DRL, and still have all the aforementioned performance.

[0123] The advantages of the multi-stage amplifier circuit of the present invention are summarized below. First, because the quiescent currents of the upper transistor MN1 and the lower transistor MP1 are determined by the bias current Ib of the differential amplifier stage 11 of the pre-stage amplifier circuit 10, the quiescent current of the entire multi-stage amplifier circuit can be precisely controlled to achieve high efficiency. Furthermore, because the internal control loop of the floating control circuit 20, including its reference voltage, floats relative to the voltages at the multiple pre-stage transconductance nodes, the high gain of the pre-stage amplifier circuit and the excellent floating performance of the floating control circuit 20 enable precise and high-speed control of the AB-class output amplifier circuit. Furthermore, the aforementioned positive voltage feedback path PPFB accelerates the in-phase response of the upper drive signal DRU and the lower drive signal DRL, thereby accelerating the transient response of the multi-stage amplifier circuit without compromising the overall stability of the multi-stage amplifier circuit. Furthermore, because the floating control circuit 20 floats relative to the multiple pre-stage transconductance nodes, the aforementioned compensation capacitor CC ensures the stability of the internal loop of the floating control circuit 20 without compromising the transient response speed of the entire multi-stage amplifier circuit.

[0124] The present invention has been described above with reference to preferred embodiments. However, the above description is intended solely to facilitate understanding of the present invention by those skilled in the art and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual application and may also be combined. For example, two or more embodiments may be combined, and components of one embodiment may replace corresponding components of another embodiment. For example, the first sub-floating control circuit and the second sub-floating circuit described above may be combined using the various embodiments described above, and are not limited to the combinations listed. Furthermore, within the spirit of the present invention, those skilled in the art may conceive of various equivalent variations and combinations. For example, the phrase "processing, calculating, or generating an output result based on a signal" in the present invention is not limited to processing the signal itself but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. Therefore, within the spirit of the present invention, those skilled in the art may conceive of various equivalent variations and combinations, and the number of such combinations is too numerous to be fully enumerated here. Therefore, the scope of the present invention encompasses the aforementioned and all other equivalent variations.

Claims

1. A multi-stage amplifier circuit comprising: a pre-stage amplifier circuit for amplifying a voltage difference between a first input terminal and a second input terminal to generate corresponding pre-stage transconductance currents at a plurality of pre-stage transconductance nodes, the pre-stage transconductance currents including a first pre-stage transconductance current and a second pre-stage transconductance current having the same phase as each other; and a floating control circuit for generating an upper driving signal and a lower driving signal according to the first pre-stage transduction current and the second pre-stage transduction current, wherein the floating control circuit includes a first sub-floating control circuit and a second sub-floating control circuit coupled to each other, for generating a first sub-floating control signal and a second sub-floating control signal, respectively, the first sub-floating control signal and the second sub-floating control signal corresponding to one and the other of the upper driving signal and the lower driving signal, respectively; The first sub-floating control circuit includes: a first floating reference transistor receiving the first pre-stage conduction current and coupled as a source follower; and a first floating amplifier coupled to the first floating reference transistor in a feedback manner, generating the first sub-floating control signal in a feedback manner according to a floating reference level within the floating control circuit, wherein the first sub-floating control signal controls the gate of the first floating reference transistor, wherein the floating reference level is generated according to the second pre-stage transduction current; The first sub-floating control signal and the second sub-floating control signal are floating relative to the voltage of the multiple previous stage transfer nodes, and there is a preset voltage difference between the first sub-floating control signal and the second sub-floating control signal, wherein the preset voltage difference is related to the gate-source voltage of the first floating reference transistor. 2 . The multi-stage amplifier circuit as claimed in claim 1 , wherein the predetermined voltage difference is determined according to the first pre-stage transduction current.

3. The multi-stage amplifier circuit according to claim 1 , wherein the first sub-floating control circuit is configured to be one of the following options: (1A) the first floating amplifier adjusts the drain voltage of the first floating reference transistor by feedback so that the drain voltage is positively correlated with the floating reference level within the floating control circuit, thereby generating the first sub-floating control signal; or (2A) The first floating amplifier adjusts the source voltage of the first floating reference transistor through feedback so that it is positively correlated with the floating reference level inside the floating control circuit, thereby generating the first sub-floating control signal.

4. The multi-stage amplifier circuit according to claim 1, wherein The power supply and bias current of the first floating amplifier are generated from other pre-stage transconductance currents except the first pre-stage transconductance current among the plurality of pre-stage transconductance currents.

5. The multi-stage amplifier circuit according to claim 3, The first sub-floating control circuit is set to option (1A); The first floating amplifier includes a first floating amplifying transistor configured as a source follower and biased by the second pre-stage transduction current, wherein a gate of the first floating amplifying transistor receives a drain voltage of the first floating reference transistor for feedback control, and a source of the first floating amplifying transistor generates the first sub-floating control signal; The source of the first floating amplifying transistor receives the second pre-stage transduction current and generates the floating reference level.

6. The multi-stage amplifier circuit according to claim 1, wherein All common-mode voltages of the floating control circuit respond in phase to the voltages of the plurality of preceding-stage transduction nodes.

7. The multi-stage amplifier circuit according to claim 1, wherein The floating control circuit forms a super node relative to the plurality of previous stage transduction nodes.

8. The multi-stage amplifier circuit according to claim 6, wherein The floating control circuit further includes a compensation capacitor coupled between a first internal node and a second internal node within the first floating amplifier; in relative to the exterior of the first floating amplifier, the common-mode voltage at the first internal node and the common-mode voltage at the second internal node are respectively determined by two in-phase pre-stage transconductance currents among the plurality of pre-stage transconductance currents, and both respond in-phase to the voltages of the plurality of pre-stage transconductance nodes; and With respect to the interior of the first floating amplifier, the first internal node and the second internal node have anti-phase responses.

9. The multi-stage amplifier circuit according to claim 8, wherein The transient response bandwidth of the floating control circuit is lower than the transient response bandwidth of the multi-stage amplifying circuit.

10. The multi-stage amplifier circuit according to claim 1, wherein The floating control circuit further includes: a synchronous amplifier for generating a synchronous amplified signal according to one of the upper driving signal or the lower driving signal; and a feedback capacitor for coupling the synchronous amplified signal to the other of the upper driving signal and the lower driving signal; The synchronous amplifier, the feedback capacitor and the first sub-floating control circuit form a voltage positive feedback path to accelerate the in-phase response of the upper drive signal and the lower drive signal, thereby accelerating the transient response of the multi-stage amplifier circuit.

11. The multi-stage amplifier circuit according to claim 10, wherein The synchronous amplifier includes: a synchronous transistor biased by a third pre-stage transduction current among the plurality of pre-stage transduction currents, the synchronous transistor being coupled as a source follower, having a gate receiving one of the high-side drive signal or the low-side drive signal and generating the synchronous amplified signal at a source thereof; The synchronous transistor, the feedback capacitor and the first sub-floating control circuit form the voltage positive feedback path.

12. The multi-stage amplifier circuit of claim 1 , further comprising an output stage circuit for generating an amplified output signal according to the upper driving signal and the lower driving signal, wherein the output stage circuit comprises: An upper transistor and a lower transistor are coupled to form an AB-class output amplifier circuit in a source-follower manner with their sources connected to each other, wherein the upper transistor and the lower transistor are respectively controlled by the upper drive signal and the lower drive signal to generate the amplified output signal.

13. The multi-stage amplifier circuit according to claim 3 , wherein the second sub-floating control circuit is configured as one of the following: (1B) wherein the first sub-floating control circuit is configured as option (1A), wherein the second sub-floating control circuit comprises: a second floating reference transistor receiving the first pre-stage conduction current and coupled as a source follower, wherein a source of the first floating reference transistor and a source of the second floating reference transistor are coupled to each other; and a second floating amplifier coupled to the second floating reference transistor in a feedback manner, and generating the second sub-floating control signal in a feedback manner according to the floating reference level within the floating control circuit to control the gate of the second floating reference transistor, wherein the second floating amplifier adjusts the drain voltage of the second floating reference transistor to be positively correlated with the floating reference level through feedback, thereby generating the second sub-floating control signal; (2B) wherein the first sub-floating control circuit is configured as option (2A), wherein the second sub-floating control circuit includes: a second floating reference transistor receiving the first pre-stage conduction current and coupled as a source follower, wherein a source of the first floating reference transistor and a source of the second floating reference transistor are coupled to each other; and a second floating amplifier coupled to the second floating reference transistor in a feedback manner, and generating the second sub-floating control signal in a feedback manner according to the floating reference level within the floating control circuit to control the gate of the second floating reference transistor, wherein the second floating amplifier adjusts the source voltage of the second floating reference transistor to be positively correlated with the floating reference level through feedback, thereby generating the second sub-floating control signal; (3B) wherein the first sub-floating control circuit is configured as option (1A) or (2A), wherein the second sub-floating control circuit includes: A floating control transistor biased by the first pre-stage transduction current has its gate and drain coupled to each other, and its source coupled to the source of the first floating reference transistor. The drain of the floating control transistor is used to generate the second sub-floating control signal. 14 . The multi-stage amplifier circuit as claimed in claim 12 , wherein the quiescent currents of the upper transistor and the lower transistor are determined according to a bias current of a differential amplifier stage of the pre-amplifier circuit.

15. A multi-stage amplifier circuit as described in claim 1, wherein the pre-stage amplifier circuit includes a plurality of push-side branches and a corresponding plurality of pull-side branches, the floating control circuit is coupled between the plurality of push-side branches and the plurality of pull-side branches, and the floating control circuit is floating corresponding to the plurality of push-side branches and the plurality of pull-side branches, wherein the plurality of pre-stage transduction currents also include a fourth pre-stage transduction current that is anti-phase with the first pre-stage transduction current, and a fifth pre-stage transduction current that is anti-phase with the second pre-stage transduction current, wherein the first pre-stage transduction current and the fourth pre-stage transduction current respectively correspond to a first push-side branch among the plurality of push-side branches and a first pull-side branch among the plurality of pull-side branches, and the second pre-stage transduction current and the fifth pre-stage transduction current respectively correspond to a second push-side branch among the plurality of push-side branches and a second pull-side branch among the plurality of pull-side branches.

16. The multi-stage amplifier circuit of claim 1 , wherein the pre-stage amplifier circuit comprises a plurality of push-side branches and a corresponding plurality of pull-side branches, the floating control circuit is coupled between the plurality of push-side branches and the plurality of pull-side branches, and the floating control circuit is floating corresponding to the plurality of push-side branches and the plurality of pull-side branches, wherein the pre-stage amplifier circuit comprises a first load current and a second load current with fixed current values, wherein the first pre-stage transduction current and the first load current respectively correspond to a first push-side branch among the plurality of push-side branches and a first pull-side branch among the plurality of pull-side branches, and the second pre-stage transduction current and the second load current respectively correspond to a second push-side branch among the plurality of push-side branches and a second pull-side branch among the plurality of pull-side branches.

17. A multi-stage amplifier circuit comprising: a pre-stage amplifier circuit for amplifying a voltage difference between a first input terminal and a second input terminal to generate corresponding pre-stage transconductance currents at a plurality of pre-stage transconductance nodes, the pre-stage transconductance currents including a first pre-stage transconductance current and a second pre-stage transconductance current having the same phase as each other; as well as A floating control circuit for generating an upper drive signal and a lower drive signal according to the first pre-stage transduction current and the second pre-stage transduction current, wherein the floating control circuit includes a first sub-floating control circuit and a second sub-floating control circuit coupled to each other, for generating a first sub-floating control signal and a second sub-floating control signal, respectively, the first sub-floating control signal and the second sub-floating control signal corresponding to one and the other of the upper drive signal and the lower drive signal, respectively; wherein the first sub-floating control signal and the second sub-floating control signal are floating relative to the voltage of the plurality of pre-stage transduction nodes, and there is a preset voltage difference between the first sub-floating control signal and the second sub-floating control signal; wherein the floating control circuit includes: a synchronous amplifier for generating a synchronous amplified signal according to one of the upper driving signal or the lower driving signal; as well as a feedback capacitor for coupling the synchronous amplified signal to the other of the upper driving signal and the lower driving signal; The synchronous amplifier, the feedback capacitor and the first sub-floating control circuit form a voltage positive feedback path to accelerate the in-phase response of the upper drive signal and the lower drive signal, thereby accelerating the transient response of the multi-stage amplifier circuit.

18. The multi-stage amplifier circuit according to claim 17, wherein The synchronous amplifier includes: a synchronous transistor biased by a third pre-stage transduction current among the plurality of pre-stage transduction currents, the synchronous transistor being coupled as a source follower, having a gate receiving one of the high-side drive signal or the low-side drive signal and generating the synchronous amplified signal at a source thereof; The synchronous transistor, the feedback capacitor and the first sub-floating control circuit form the voltage positive feedback path.

19. The multi-stage amplifier circuit of claim 17 , further comprising an output stage circuit for generating an amplified output signal according to the upper driving signal and the lower driving signal, wherein the output stage circuit comprises: An upper transistor and a lower transistor are coupled to form an AB-class output amplifier circuit in a source-follower manner with their sources connected to each other, wherein the upper transistor and the lower transistor are respectively controlled by the upper drive signal and the lower drive signal to generate the amplified output signal.

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