A method for slicing massive simulation waveform data for FPGA parallel simulation

Abstract

The present invention discloses a method for slicing massive simulation waveform data for FPGA parallel simulation, the method comprising: setting simulation waveform slicing information and dividing the imported FPGA project into multiple independent submodules, and then downloading the corresponding generated FPGA bit stream to the FPGA for parallel simulation; selecting a debugging signal and caching the simulation waveform data in a DDR memory; accessing the simulation waveform data and generating an index file, and saving the transferred VCD simulation waveform slice file together with the index file; parsing the index file to obtain a debugging signal list; selecting the debugging signal to be restored to restore the simulation waveform. The present invention slices massive simulation waveform files into a large number of micro files based on the functional module and time axis of the debugging signal, and organizes the micro files by creating an index, focusing on the signal and time period required for debugging, filtering out a large amount of redundant data, reducing the requirements for network bandwidth and CPU processing speed, thereby reducing the delay in restoring the simulation waveform and improving debugging efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of computer program data processing, and in particular to a method for slicing massive simulation waveform data for FPGA parallel simulation. Background Art

[0002] In the prior art, the simulation waveform of FPGA (Field Programmable Gate Array) simulation is usually recorded in VCD format (Value Change Dump, which is an ASCII file defined in IEEE1364 standard (Verilog HDL language standard) and is a universal file format). VCD format file is an ASCII file (ASCII File file, which refers to data and text files containing characters encoded with standard ASCII character set) defined in IEEE1364 standard (Verilog HDL language standard), which records the complete change information of the signal and can be used to reproduce the simulation. Because VCD format is part of Verilog HDL language standard, all Verilog simulators can view VCD format files. VCD format files usually consist of three parts: header information area, node information area and value change area, wherein the header information area includes information such as VCD generation date, simulator version and simulation time accuracy; the node information area mainly records which variable signals will be recorded in VCD and the identifiers corresponding to these variable signals in VCD; the value change area mainly records those variable signals that change as the simulation time passes. Generally speaking, VCD only records the changes in signals, so it is necessary to create a checkpoint, at which all signals to be recorded are recorded as a benchmark. By default, a checkpoint will be created at the beginning of the VCD value change area to record the initial values ​​of all signals to be recorded. To reproduce the simulation, the waveform data must be analyzed and restored sequentially from the checkpoint, and random access cannot be performed to obtain the simulation waveform data.

[0003] During FPGA parallel simulation, the user design is divided into sub-designs and distributed to multiple FPGAs for execution. Each FPGA will be equipped with DDR (Double Data Rate SDRAM) memory. The simulation waveform data is first cached in the standard DDR memory of dozens or hundreds of FPGAs. After the simulation is completed, it is calibrated and merged using the global clock timestamp, and then transferred to a VCD format simulation waveform file and saved on the server. The user needs to download it through the network for local display and analysis.

[0004] FPGA parallel simulation will generate massive amounts of simulation waveform data. According to industry practice, the simulation needs to record signal changes within at least 1ms (usually at intervals of 1ns). Even a signal with a single bit of bandwidth records more than 1M bits of binary data. A simulation often requires observing thousands of signal waveforms, and the recorded VCD simulation waveform files are as large as tens of GB. In addition, during large-scale FPGA parallel simulation, the simulation waveform files are stored on the server side, and the access speed is limited by the network bandwidth. The main problem with the analysis, processing and display of ultra-large simulation waveform files is latency. Current mainstream simulators / simulation waveform tools require waiting from tens of minutes to hours to process such simulation waveform file data. The reason is the network speed bottleneck and the CPU performance bottleneck. Both downloading and sequentially parsing ultra-large simulation waveform files require a lot of time.

[0005] In view of this, it is a technical problem that technicians in this field urgently need to solve to study a method for slicing massive simulation waveform data for FPGA parallel simulation to reduce latency and improve debugging efficiency. Summary of the invention

[0006] In view of this, the present invention proposes a method for slicing massive simulation waveform data for FPGA parallel simulation to overcome the problems of current simulation waveform file access speed and analysis and processing delay. This method can reduce the delay in restoring simulation waveforms and effectively improve debugging efficiency.

[0007] The massive simulation waveform data slicing method for FPGA parallel simulation proposed by the present invention comprises:

[0008] S1. Set simulation waveform segmentation information and import FPGA project, divide the imported FPGA project into multiple independent sub-modules and generate FPGA bit streams one by one, and then download the generated FPGA bit streams to FPGAs synchronized with global clock signals for parallel simulation, wherein the simulation waveform segmentation information includes RLM division, time axis segmentation granularity and simulation file saving path;

[0009] S2, select the debug signal to be debugged and set the debug signal trigger condition, add the global clock timestamp to the simulation waveform data generated by the debug signal during the simulation process and cache it in the DDR memory;

[0010] S3, using the simulation waveform segmentation module to access the simulation waveform data cached in step S2, calibrate, merge and reorganize the accessed simulation waveform data based on the global clock timestamp and generate an index file, then save the VCD simulation waveform slice file of the simulation waveform data transferred together with the index file to the simulation file saving path configured in step S1 and provide network file access service;

[0011] S4, using the simulation waveform display module to download the index file, and obtain the debugging signal list by parsing the index file;

[0012] S5. Based on the debugging signal list obtained in step S4, the debugging signal and / or time point to be restored is selected, and the corresponding VCD simulation waveform slice file is loaded into the DDR memory by using the simulation waveform display module to restore the simulation waveform.

[0013] In the above-mentioned method for slicing massive simulation waveform data of FPGA parallel simulation, optionally, the RLM division in step S1 is performed based on the closeness of the functional relationship between the debugging signals.

[0014] In the above-mentioned method for slicing massive simulation waveform data for FPGA parallel simulation, optionally, the index file generated in step S3 is an ASCII file, which includes a header information area, a node information area and a node URL mapping area.

[0015] The above-mentioned method for slicing massive simulation waveform data of FPGA parallel simulation, optionally, the specific implementation method of transferring the simulation waveform data into a VCD simulation waveform slice file in step S3 is: transferring the simulation waveform data into a VCD simulation waveform slice file according to the time axis segmentation granularity and the signal URL mapping table in the index file.

[0016] In the above-mentioned method for slicing massive simulation waveform data of FPGA parallel simulation, optionally, the specific step of saving the VCD simulation waveform slice file of the simulation waveform data transferred together with the index file to the simulation file saving path configured in step S1 in step S3 includes:

[0017] S31. Query the index file according to the information of the debugging signal, and then generate the RLM simulation waveform slice file name to which the debugging signal belongs, wherein the RLM simulation waveform slice file name is expressed as: RLM simulation waveform slice file name simulation waveform slice serial number.vcd, and the calculation formula of the simulation waveform slice serial number is expressed as:

[0018]

[0019] In formula (1), [] indicates rounding;

[0020] S32. Based on the name of the simulation waveform slice file generated in step S31, a VCD simulation waveform slice file can be obtained, and the VCD simulation waveform slice file and the index file are saved together to the simulation file saving path configured in step S1.

[0021] The above-mentioned method for slicing massive simulation waveform data for FPGA parallel simulation, optionally, in step S3, when transferring the simulation waveform data to a VCD simulation waveform slice file, it is necessary to create a checkpoint at the starting position of the numerical change area, and then record the current values ​​of all signals of the RLM simulation waveform slice file at that moment.

[0022] The above-mentioned method for slicing massive simulation waveform data of FPGA parallel simulation, optionally, the specific steps of restoring the simulation waveform by loading the corresponding VCD simulation waveform slice file into the DDR memory using the simulation model display module in step S5 include:

[0023] S51, using the simulation model display module to search in the local cache whether there is a corresponding VCD simulation waveform slice file, if it exists, it is directly loaded into the DDR memory to restore the simulation waveform, if not, go to step S52;

[0024] S52. Download the corresponding VCD simulation waveform slice file to the local computer through the file sharing module, and then load the downloaded VCD simulation waveform slice file into the DDR memory to restore the simulation waveform.

[0025] The above-mentioned method for slicing massive simulation waveform data for FPGA parallel simulation, optionally, the simulation model display module downloads and / or loads the VCD simulation waveform slicing file through an asynchronous thread, thereby being able to fully utilize the CPU multi-core advantage to reduce latency.

[0026] The present invention proposes a method for slicing massive simulation waveform data for FPGA parallel simulation. According to the characteristics of FPGA parallel simulation that the restored simulation waveform is highly concentrated on the debugging signal and time point, the slicing method divides a very large simulation waveform file containing massive simulation data into a large number of micro files based on the functional modules and time axis of the debugging signal, and organizes the large number of micro files by creating indexes. The method focuses on the signals and time periods required for debugging, can filter out a large amount of redundant data, and thus reduces the requirements for network bandwidth and CPU processing speed, making it feasible to use the CPU multi-core advantage to download and / or parse the VCD simulation waveform segmented files in parallel, thereby reducing the delay in restoring the simulation waveform and greatly improving the debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are only used to provide further explanation of the present invention, constitute a part of the application, and do not constitute a limitation of the present invention. In the drawings:

[0028] Figure 1 It is a flow chart of a method for slicing massive simulation waveform data for FPGA parallel simulation in the present invention.

[0029] Figure 2 The present invention is a flow chart of the method for loading a simulation waveform slice file into a DDR memory. DETAILED DESCRIPTION

[0030] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0031] Specifically, a method for slicing massive simulation waveform data for FPGA parallel simulation is proposed in a specific embodiment of the present invention. Figure 1 As shown, the following steps are included:

[0032] S1. Set the simulation waveform segmentation information and import the FPGA project (the FPGA project refers to the Verilog source code, the IP core used, the netlist and the constraints, which are used to describe the hardware circuit to generate the FPGA bit stream), divide the imported FPGA project into multiple independent sub-modules and generate FPGA bit streams one by one, and then download the generated FPGA bit streams to the FPGA synchronized with the global clock signal for parallel simulation, wherein the simulation waveform segmentation information includes RLM (RLM is the proposed receiver-driven layered multicast algorithm) division, time axis segmentation granularity and simulation file save path, and the RLM division is based on the functional relationship between the debug signals. The RLM division is as follows:

[0033] The FPGA project in the RLM partition is an instance tree with the top module as the root node. Each node in the instance tree corresponds to an instance of a module. The subtree corresponding to each node represents that all nodes under the subtree are instantiated by the instance of the module corresponding to the node. The root node corresponds to the top module itself. Initially, all module instances belong to RLM0 by default. In this embodiment, giving the top-level module instance node of RLM means that all nodes under the subtree corresponding to this node are divided into a certain RLM. The RLM partition example is as follows: / / rlm sequence number rlm name rlm top-level module instance path

[0034] rlm 0top top_tb

[0035] rlm 1u_dut1 top_tb|u_dut1

[0036] rlm 2u_dut2 top_tb|u_dut2;

[0037] Based on RLM division of debugging signals, when debugging functions, only the corresponding RLM corresponding simulation waveform files need to be downloaded without downloading all the simulation waveform files of debugging signals. The simulation waveform files are divided based on the time axis segmentation granularity, and the debugging signal simulation waveform data is saved in time periods according to the given time axis segmentation granularity. After segmentation, although the VCD simulation waveform slice files cannot be randomly accessed according to the simulation accuracy, the simulation waveform data slice files saved in the corresponding time period can be located according to the simulation time of interest, which can achieve on-demand access and greatly reduce latency.

[0038] S2. Select the debug signal to be debugged and set the debug signal trigger condition. Add the global clock timestamp to the simulation waveform data generated by the debug signal during the simulation process and cache it in the DDR memory. The DDR memory is the standard DDR memory of the FPGA.

[0039] S3, using the simulation waveform segmentation module to access the simulation waveform data cached in step S2, calibrate, merge and reorganize the accessed simulation waveform data based on the global clock timestamp and generate an index file, then save the VCD simulation waveform slice file of the simulation waveform data together with the index file to the simulation file save path configured in step S1 and provide network file access service (since the file of the simulation waveform data is very large, the present invention uses the simulation waveform segmentation module to pre-process the simulation waveform data for subsequent information retrieval, and uses the simulation waveform segmentation module to generate an index file and save the simulation waveform data as a VCD simulation waveform slice file), wherein the simulation waveform data is saved as a VCD simulation waveform slice file according to the time axis segmentation granularity and the signal url (Uniform Resource Locator) mapping table in the index file, and the index file is an ASCII file, which includes a header information area, a node information area and a node url mapping area, and the header information area and the node information area corresponding to the index file should be compatible with the information area and the node information area in the VCD simulation waveform file. An example of an index file is as follows:

[0040]

[0041]

[0042] The time axis segmentation granularity in the index file comes from the time axis segmentation granularity in the simulation waveform segmentation information configuration in step S1, the simulation duration comes from the global clock count, the project directory in the signal url mapping table comes from the simulation file save path configured in step S1, the identifier is generated according to the IEEE-1364 standard based on the debug signal selected in step S2, and the rlm name is obtained by querying the RLM partition table based on the module hierarchy structure of the debug signal;

[0043] S4, using the simulation waveform display module to download the index file, and obtain the debugging signal list by parsing the index file;

[0044] S5. Based on the debugging signal list obtained in step S4, the debugging signal and / or time point to be restored is selected, and the simulation waveform display module is used to load the corresponding VCD simulation waveform slice file into the DDR memory to restore the simulation waveform.

[0045] In this embodiment, the simulation display module and the simulation waveform segmentation module are both conventional technologies in the field, and as long as they have the corresponding functions in this embodiment, they are all acceptable and will not be described in detail here. The slicing method is based on the characteristics of FPGA parallel simulation to restore the simulation waveform with a high concentration of debugging signals and time points. Based on the functional modules and time axes of the debugging signals, the super-large simulation waveform file containing massive simulation data is segmented into a large number of micro files, and a large number of micro files are organized by creating indexes. This method focuses on the signals and time periods required for debugging, and can filter out a large amount of redundant data, thereby reducing the requirements for network bandwidth and CPU processing speed, making it feasible to use the advantages of CPU multi-core to download and / or parse the VCD simulation waveform segmentation files in parallel, thereby reducing the delay in restoring the simulation waveform and greatly improving the debugging efficiency.

[0046] like Figure 2 As shown, the specific steps of saving the VCD simulation waveform file of the simulation waveform data transferred together with the index file to the simulation file saving path configured in step S1 in step S3 include:

[0047] S31. Query the index file according to the information of the debugging signal, and then generate the RLM simulation waveform slice file name to which the debugging signal belongs, wherein the RLM simulation waveform slice file name is expressed as: RLM simulation waveform slice file name simulation waveform slice serial number.vcd, and the calculation formula of the simulation waveform slice serial number is expressed as:

[0048]

[0049] In formula (1), [] indicates rounding;

[0050] S32. Based on the RLM simulation waveform slice file name generated in step S31, a VCD simulation waveform slice file can be obtained, and the VCD simulation waveform slice file and the index file are saved together to the simulation file saving path configured in step S1.

[0051] In this embodiment, the information of the debugging signal refers to the number of the debugging signal in the index file. The index file contains a signal URL mapping table, which includes the name of the RLM simulation waveform slice file, as follows:

[0052] $url / / Signal url mapping table, format: identifier project directory / rlm name

[0053] ! / home / ubisectech / project / rlm1

[0054] The debug signal is numbered as the symbol in the index file!, and the RLM simulation waveform slice file is named rlm1 and stored in the path / home / ubisectech / project / .

[0055] Among them, when transferring the simulation waveform data to a VCD simulation waveform slice file in step S3, a checkpoint needs to be created at the starting position of the value change area, thereby recording the current values ​​of all signals of the RLM simulation waveform slice file at that moment. Since a VCD simulation waveform slice file generally records the current value of a signal only when the signal changes, the signals in the RLM at the initial time point of the slice may not all be recorded. By creating a checkpoint at the starting position of the value change area to record the current values ​​of all signals of the RLM simulation waveform slice file at that moment, it can effectively avoid the need to trace back to a VCD simulation waveform slice file when accessing it.

[0056] The specific steps of using the simulation model display module to load the corresponding VCD simulation waveform slice file into the DDR memory to restore the simulation waveform in step S5 include:

[0057] S51, using the simulation model display module to search in the local cache whether there is a corresponding VCD simulation waveform slice file, if it exists, it is directly loaded into the DDR memory to restore the simulation waveform, if not, go to step S52;

[0058] S52. Download the corresponding VCD simulation waveform slice file to the local computer through the file sharing module, and then load the downloaded VCD simulation waveform slice file into the DDR memory to restore the simulation waveform.

[0059] The simulation model display module downloads and / or loads the VCD simulation waveform slice file through an asynchronous thread, thereby being able to fully utilize the CPU multi-core advantage to reduce latency.

[0060] In this embodiment, since the simulation waveform index file and the VCD simulation waveform slice file are not cached locally initially, the simulation waveform display module needs to use the file sharing module to download the simulation waveform index file and the VCD simulation waveform slice file to the local and then load them into the DDR memory. At the same time, the VCD simulation waveform slice file is downloaded and / or loaded through an asynchronous thread, which can fully utilize the CPU multi-core advantage, further reduce latency, and improve debugging efficiency.

[0061] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for slicing massive simulation waveform data for FPGA parallel simulation, characterized in that: include: S1. Set simulation waveform segmentation information and import the FPGA project, divide the imported FPGA project into multiple independent sub-modules and generate FPGA bit streams one by one, and then download the generated FPGA bit streams to the FPGA synchronized with the global clock signal for parallel simulation, wherein the simulation waveform segmentation information includes RLM division, time axis segmentation granularity and simulation file saving path, and the RLM is a proposed receiver-driven layered multicast algorithm; S2, select the debug signal to be debugged and set the debug signal trigger condition, add the global clock timestamp to the simulation waveform data generated by the debug signal during the simulation process and cache it in the DDR memory; S3, using the simulation waveform segmentation module to access the simulation waveform data cached in step S2, calibrate, merge and reorganize the accessed simulation waveform data based on the global clock timestamp and generate an index file, then save the VCD simulation waveform slice file of the simulation waveform data transferred together with the index file to the simulation file saving path configured in step S1 and provide network file access service; S4, using the simulation waveform display module to download the index file, and obtain the debugging signal list by parsing the index file; S5. Based on the debugging signal list obtained in step S4, the debugging signal and / or time point to be restored is selected, and the simulation waveform display module is used to load the corresponding VCD simulation waveform slice file into the DDR memory to restore the simulation waveform.

2. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 1, characterized in that: The RLM division in step S1 is performed based on the closeness of the functional relationship between the debugging signals.

3. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 2, characterized in that: The index file generated in step S3 is an ASCII file, which includes a header information area, a node information area and a node URL mapping area.

4. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 3, characterized in that: The specific implementation method of transferring the simulation waveform data into a VCD simulation waveform slice file in step S3 is: transferring the simulation waveform data into a VCD simulation waveform slice file according to the time axis segmentation granularity and the signal URL mapping table in the index file.

5. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 4, characterized in that: The specific steps of saving the VCD simulation waveform slice file and the index file of the simulation waveform data transferred to the simulation file saving path configured in step S1 in step S3 include: S31. Query the index file according to the information of the debugging signal, and then generate the RLM simulation waveform slice file name to which the debugging signal belongs, wherein the RLM simulation waveform slice file name is expressed as: RLM simulation waveform slice file name simulation waveform slice serial number.vcd, and the calculation formula of the simulation waveform slice serial number is expressed as: In formula (1), [] indicates rounding; S32. Based on the RLM simulation waveform slice file name generated in step S31, a VCD simulation waveform slice file can be obtained, and the VCD simulation waveform slice file and the index file are saved together to the simulation file saving path configured in step S1.

6. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 5, characterized in that: When transferring the simulation waveform data to a VCD simulation waveform slice file in step S3, a checkpoint needs to be created at the starting position of the numerical change area, and then the current values ​​of all signals in the RLM simulation waveform slice file at the corresponding moment on the time axis at the starting position of the numerical change area are recorded.

7. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 6, characterized in that: The specific steps of using the simulation model display module to load the corresponding VCD simulation waveform slice file into the DDR memory to restore the simulation waveform in step S5 include: S51, using the simulation model display module to search in the local cache whether there is a corresponding VCD simulation waveform slice file, if it exists, it is directly loaded into the DDR memory to restore the simulation waveform, if not, go to step S52; S52. Download the corresponding VCD simulation waveform slice file to the local computer through the file sharing module, and then load the downloaded VCD simulation waveform slice file into the DDR memory to restore the simulation waveform.

8. The method for slicing massive simulation waveform data for FPGA parallel simulation according to claim 7, characterized in that: The simulation model display module downloads and / or loads the VCD simulation waveform slice file through an asynchronous thread.

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