Method and memory for reducing program disturb by adjusting voltage of dummy word line

Abstract

A memory includes an upper stack and a lower stack. The upper stack includes a first upper dummy word line. The lower stack includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and / or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and / or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Description

[0001] This application is a divisional application of the patent filed on December 9, 2019, with application number 201980003629.2, entitled "Method and Memory for Reducing Programming Interference by Adjusting the Voltage of Dummy Word Lines". Technical Field

[0002] This disclosure relates to methods and memories for reducing programming interference, and more specifically, to methods and memories for reducing programming interference by adjusting the voltage of dummy word lines. Background Technology

[0003] To increase memory capacity, memory with a three-dimensional structure has been developed. For example, three-dimensional stacked NAND flash memory is currently available.

[0004] The three-dimensional structure of a memory can include multiple layers, allowing more data to be stored in the same area. This solution has proven effective in increasing memory capacity.

[0005] However, programming interference becomes more severe as the number of layers increases. This interference leads to a higher failure rate in memory programming. Therefore, there is a need in the art for a solution to reduce programming interference when operating three-dimensional memory. Summary of the Invention

[0006] An embodiment discloses a method for reducing programming interference in a memory, the memory including an upper stack and a lower stack, the upper stack being formed above the lower stack, the upper stack including a first upper dummy word line, and the lower stack including a first lower dummy word line. The method includes:

[0007] A first upper bias voltage is applied to the first upper dummy word line, such that the difference between the first upper bias voltage and the first upper threshold voltage of the memory cell connected to the first upper dummy word line is a first difference value.

[0008] A first lower bias voltage is applied to the first lower dummy word line, such that the difference between the first lower bias voltage and the first lower threshold voltage of the memory cell connected to the first lower dummy word line is a second difference.

[0009] The first difference and the second difference are adjusted to reduce interference with memory programming.

[0010] Another embodiment includes a memory comprising:

[0011] Upper stack body, the upper stack body including a first upper dummy word line;

[0012] a lower stack comprising a first lower dummy word line; wherein the upper stack is formed above the lower stack;

[0013] and a control circuit coupled to the first upper dummy word line and the first lower dummy word line; wherein,

[0014] the control circuit is configured to apply a first upper bias voltage to the first upper dummy word line such that a difference between the first upper bias voltage and a first upper threshold voltage of a memory cell connected to the first upper dummy word line is a first difference, and apply a first lower bias voltage to the first lower dummy word line such that a difference between the first lower bias voltage and a first lower threshold voltage of a memory cell connected to the first lower dummy word line is a second difference;

[0015] adjusting the first difference and the second difference to reduce interference to programming of the memory.

[0016] These and other objects of the present application will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various drawing figures. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 a memory according to an embodiment is shown.

[0018] Figure 2 a flowchart of a method for reducing programming interference of a memory according to an embodiment is shown. Figure 1

[0019] Figure 3 a memory according to another embodiment is shown.

[0020] Figure 4 a flowchart of a method for reducing programming interference of a memory according to another embodiment is shown. Figure 3

[0021] a memory according to another embodiment is shown. Figure 5

[0022] Figure 6 a flowchart of a method for reducing programming interference of a memory according to another embodiment is shown. Figure 5

[0023] a memory according to another embodiment is shown. Figure 7

[0024] a flowchart of a method for reducing programming interference of a memory according to another embodiment is shown. Figure 8 Figure 7 a flowchart of a method for reducing programming interference of a memory according to another embodiment is shown.

[0025] Figure 9 Figure 7 a flowchart of a method for reducing programming interference of a memory according to another embodiment is shown.​​​The waveform of the memory.

[0026] Figure 10 Control according to another embodiment Figure 7 The waveform of the memory.

[0027] Figure 11 to 14 A memory according to different embodiments is shown. Detailed Implementation

[0028] In this text, when the conjunction “and / or” is used to connect item A and item B into “A and / or B”, it means either A and B or both A and B.

[0029] Figure 1 A memory 100 according to an embodiment is shown. The memory 100 may include an upper stack 110 and a lower stack 120. The upper stack 110 may be formed over the lower stack 120. The memory 100 may further include a junction oxide layer 155 formed between the upper stack 110 and the lower stack 120.

[0030] like Figure 1 As shown, the upper stack 110 may include a first upper dummy word line IDMY_u0, and the lower stack 120 may include a first lower dummy word line IDMY_l0.

[0031] Figure 2 It is used to reduce Figure 1 A flowchart of a method 200 for interfering with the programming of memory 100. Method 200 includes at least the following steps.

[0032] Step 210: Adjust the first upper bias voltage V_u0 applied to the first upper dummy word line IDMY_u0 and / or the first upper threshold voltage Vt_u0 of the first upper dummy word line IDMY_u0 to adjust the first difference ΔV_u0 between the first upper bias voltage V_u0 and the first upper threshold voltage Vt_u0; and

[0033] Step 220: Adjust the first lower bias voltage V_l0 applied to the first lower dummy word line IDMY_l0 and / or the first lower threshold voltage Vt_l0 of the first lower dummy word line IDMY_l0 to adjust the second difference ΔV_l0 between the first lower bias voltage V_l0 and the first lower threshold voltage Vt_l0.

[0034] Figure 2 This is just an example; it can be executed in any order. Figure 2 The steps in the process. For example, step 220 can be performed first. These steps can be performed simultaneously.

[0035] In steps 210 and 220, ΔV_u0 and ΔV_l0 can be expressed as the following equations:

[0036] AV_u0 = V_u0 - Vt_u0... (Equation 1); and

[0037] AV_l0 = V_l0 - Vt_l0... (Equation 2).

[0038] As described in steps 210 and 220, V_u0 and / or Vt_u0 can be adjusted to adjust AV_u0. V_l0 and / or Vt_l0 can be adjusted to adjust AV_l0. By adjusting the first difference AV_u0 and the second difference AV_l0 to be as low as possible, program disturb can be reduced.

[0039] As shown in FIG. 2, word line WL(n-1) can be at a first layer below first lower dummy word line IDMY_l0. Word line WL(n-2) can be at a second layer below first lower dummy word line IDMY_l0. Word line WL(n-3) can be at a third layer below first lower dummy word line IDMY_l0. Word line WL0 can be at a fourth layer below first lower dummy word line IDMY_l0. Figure 1

[0040] Word line WL(n+1) can be at a first layer above first upper dummy word line IDMY_u0. Word line WL(n+2) can be at a second layer above first upper dummy word line IDMY_u0. Word line WL(n+3) can be at a third layer above first upper dummy word line IDMY_u0. Word line WLm can be at a fourth layer above first upper dummy word line IDMY_u0.

[0041] With respect to the adjustment of the first difference AV_u0 and the second difference AV_l0, the first difference AV_u0 can be adjusted to be higher than a threshold TH1 when programming word lines among word lines WL(n-1) to WL(n+2). The second difference AV_l0 can be adjusted to be higher than the threshold TH1. In other words, after the adjustment, AV_u0 = V_u0 - Vt_u0 > TH1 and AV_l0 = V_l0 - Vt_l0 > TH1. For example, the threshold TH1 can be 7 volts.

[0042] The first difference AV_u0 can be adjusted to be lower than a threshold TH2 when programming word lines among word lines WL(n+3) to WLm. The second difference AV_l0 can be adjusted to be lower than the threshold TH2. In other words, after the adjustment, AV_u0 = V_u0 - Vt_u0 < TH2 and AV_l0 = V_l0 - Vt_l0 < TH2. For example, the threshold TH2 can be 7 volts.

[0043] The first difference AV_u0 and the second difference AV_l0 can not be limited when programming word lines among word lines WL0 to WL(n-2); however, according to experiments, the first difference AV_u0 and the second difference AV_l0 can be higher than a threshold TH3. For example, the threshold TH3 can be 3 volts. ​

[0044] Figure 3 A memory 100 according to another embodiment is shown. Figure 3 The structure shown can be compared with Figure 1 The structures shown are similar. For example... Figure 3 As shown, the lower stack body 120 may further include a second lower dummy word line IDMY_l1.

[0045] Figure 4 It is used to reduce Figure 3 A flowchart of a method 400 for interfering with the programming of memory 100. Method 400 may include the following steps.

[0046] Step 210: Adjust the first upper bias voltage V_u0 applied to the first upper dummy word line IDMY_u0 and / or the first upper threshold voltage Vt_u0 of the first upper dummy word line IDMY_u0 to adjust the first difference ΔV_u0 between the first upper bias voltage V_u0 and the first upper threshold voltage Vt_u0;

[0047] Step 220: Adjust the first lower bias voltage V_l0 applied to the first lower dummy word line IDMY_l0 and / or the first lower threshold voltage Vt_l0 of the first lower dummy word line IDMY_l0 to adjust the second difference ΔV_l0 between the first lower bias voltage V_l0 and the first lower threshold voltage Vt_l0; and

[0048] Step 230: Adjust the second lower bias voltage V_l1 applied to the second lower dummy word line IDMY_l1 and / or the second lower threshold voltage Vt_l1 of the second lower dummy word line IDMY_l1 to adjust the third difference ΔV_l1 between the second lower bias voltage V_l1 and the second lower threshold voltage Vt_l1.

[0049] Figure 4 This is just an example; it can be executed in any order. Figure 4 The steps in the process. For example, steps 220 or 230 can be performed before step 210. These steps can also be performed simultaneously.

[0050] ΔV_u0 and ΔV_l0 in steps 210 and 220 can be expressed as the above equations (Equations 1 and 2). ΔV_l1 in step 230 can be expressed as the following equation:

[0051] ΔV_l1=V_l1–Vt_l1…(Equation 3).

[0052] As described in steps 210 to 230, the first difference ΔV_u0, the second difference ΔV_l0, and the third difference ΔV_l1 can be adjusted as follows to reduce programming interference.

[0053] When programming the word lines in the upper stack 110, the first difference AV_u0 can be adjusted to be higher than the threshold TH4, the second difference AV_l0 can be adjusted to be lower than the threshold TH4, and the third difference AV_l1 can be adjusted to be lower than the threshold TH4. In other words, after the adjustment, AV_u0 = V_u0 - Vt_u0 > TH4, AV_l0 = V_l0 - Vt_l0 < TH4, and AV_l1 = V_l1 - Vt_l1 < TH4. For example, the threshold TH4 can be 7 volts.

[0054] Further, according to an embodiment, it can also be necessary to satisfy condition (c-1) in order to reduce the program disturbance of the memory 100. Figure 3

[0055] Condition (c-1) can include that a difference between the first difference AV_u0 and the second difference AV_l0 can be within a predetermined range, and another difference between the first difference AV_u0 and the third difference AV_l1 can be within the predetermined range.

[0056] The predetermined range in relation to condition (c-1) can be within a range of a level LI and a level L2 higher than the level LI. Thus, in other words, condition (c-1) can be expressed as LI < (AV_u0 - AV_l0) < L2, and LI < (AV_u0 - AV_l1) < L2. For example, the level LI can be 3 volts, and the second level L2 can be 7 volts.

[0057] In relation to the first difference AV_u0, the second difference AV_l0, and the third difference AV_l1, the equations and inequalities mentioned above can be applied when programming the word lines of the upper stack 110. Figure 3

[0058] When programming the word lines of the lower stack 120, the first difference AV_u0, the second difference AV_l0, and the third difference AV_l1 can not be limited; however, according to experiments, the differences AV_u0, AV_l0, and AV_l1 can be higher than a threshold (e.g., 3 volts).

[0059] Figure 5 A memory 100 according to another embodiment is shown. Figure 5 The shown structure can be similar to the structure shown in Figure 1 As shown in Figure 5 the upper stack 110 can further include a second upper dummy word line IDMY_u1.

[0060] Figure 6 A flowchart of a method 600 for reducing the program disturbance of the memory 100 is shown. Figure 5 The method 600 can include the following steps.​​

[0061] Step 210: adjusting a first upper bias voltage V_u0 applied to the first upper dummy word line IDMY_u0 and / or a first upper threshold voltage Vt_u0 of the first upper dummy word line IDMY_u0 to adjust a first difference AV_u0 between the first upper bias voltage V_u0 and the first upper threshold voltage Vt_u0;

[0062] Step 220: adjusting a first lower bias voltage V_l0 applied to the first lower dummy word line IDMY_l0 and / or a first lower threshold voltage Vt_l0 of the first lower dummy word line IDMY_l0 to adjust a second difference AV_l0 between the first lower bias voltage V_l0 and the first lower threshold voltage Vt_l0; and

[0063] Step 240: adjusting a second upper bias voltage V_u1 applied to the second upper dummy word line IDMY_u1 and / or a second upper threshold voltage Vt_u1 of the second upper dummy word line IDMY_u1 to adjust a fourth difference AV_u1 between the second upper bias voltage V_u1 and the second upper threshold voltage Vt_u1.

[0064] Figure 6 Just one example, the steps in Figure 6 may be performed in any order. For example, step 220 or step 240 can be performed before step 210. The steps can be performed simultaneously.

[0065] The AV_u0 and AV_l0 in step 210 and step 220 can be expressed as the above equations (Equation 1 and Equation 2). The AV_u1 in step 240 can be expressed as the following equation:

[0066] AV_u1 = V_u1 - Vt_u1 … (Equation 4).

[0067] As described in step 210, step 220, and step 230, the first difference AV_u0, the second difference AV_l0, and the fourth difference AV_u1 can be adjusted to reduce program disturb as follows.

[0068] When programming the word lines of the upper stack 110, the first difference AV_u0 can be adjusted to be lower than a threshold TH5, the second difference AV_l0 can be adjusted to be lower than the threshold TH5, and the fourth difference AV_u1 can be adjusted to be higher than the threshold TH5. In other words, after the adjustment, AV_u0 = V_u0 - Vt_u0 < TH5, AV_l0 = V_l0 - Vt_l0 < TH5, and AV_u1 = V_u1 - Vt_u1 > TH5. For example, the threshold TH5 can be 7 volts.

[0069] Further, according to embodiments, condition (c-2) can also have to be satisfied in order to reduce Figure 5 the program disturbance of the memory 100.

[0070] Condition (c-2) can include that a difference between the fourth difference AV_u1 and the first difference AV_u0 can be within a predetermined range, and another difference between the fourth difference AV_u1 and the second difference AV_l0 can be within the predetermined range.

[0071] The predetermined range in relation to condition (c-2) can be within a range of a level L3 and a level L4 higher than the level L3. Thus, in other words, condition (c-2) can be expressed as L3 < (AV_u1 - AV_u0) < L4, and L3 < (AV_u1 - AV_l0) < L4. For example, the level L3 can be 3 volts, and the level L4 can be 7 volts.

[0072] In relation to Figure 5 , the equations and inequalities in relation to the differences AV_u0, AV_l0 and AV_u1 mentioned above can be applied when programming the word lines of the upper stack 110.

[0073] The differences AV_u0, AV_l0 and AV_u1 can not be limited when programming the word lines of the lower stack 120; however, according to experiments, the differences AV_u0, AV_l0 and AV_u1 can be higher than a threshold value (e.g. 3 volts).

[0074] Figure 7 A memory 100 according to another embodiment is shown. Figure 7 The shown structure can be similar to the structure shown in Figure 1 In contrast to Figure 1 , in Figure 7 , the upper stack 110 can further comprise a second upper dummy word line IDMY_u1, and the lower stack 120 can further comprise a second lower dummy word line IDMY_l1.

[0075] Figure 8 is a flowchart of a method 800 for reducing the program disturbance of the memory 100. Figure 7 The method 800 can comprise the following steps.

[0076] Step 210: adjusting a first upper bias voltage V_u0 applied to the first upper dummy word line IDMY_u0 and / or a first upper threshold voltage Vt_u0 of the first upper dummy word line IDMY_u0 to adjust a first difference AV_u0 between the first upper bias voltage V_u0 and the first upper threshold voltage Vt_u0;

[0077] Step 220: adjusting the first lower bias voltage V_l0 applied to the first lower dummy word line IDMY_l0 and / or the first lower threshold voltage Vt_l0 of the first lower dummy word line IDMY_l0 to adjust a second difference AV_l0 between the first lower bias voltage V_l0 and the first lower threshold voltage Vt_l0;

[0078] Step 230: adjusting the second lower bias voltage V_l1 applied to the second lower dummy word line IDMY_l1 and / or the second lower threshold voltage Vt_l1 of the second lower dummy word line IDMY_l1 to adjust a third difference AV_l1 between the second lower bias voltage V_l1 and the second lower threshold voltage Vt_l1; and

[0079] Step 240: adjusting the second upper bias voltage V_u1 applied to the second upper dummy word line IDMY_u1 and / or the second upper threshold voltage Vt_u1 of the second upper dummy word line IDMY_u1 to adjust a fourth difference AV_u1 between the second upper bias voltage V_u1 and the second upper threshold voltage Vt_u1.

[0080] Figure 8 Just one example, the steps in Figure 8 can be performed in any order. For example, step 220, step 230, or step 240 can be performed before step 210. These steps can be performed simultaneously.

[0081] The AV_u0, AV_l0, AV_l1, and AV_u1 in steps 210 to 240 can be expressed as the equations (Equation 1 to Equation 4) described above.

[0082] As described in steps 210 to 240, the first difference AV_u0, the second difference AV_l0, the third difference AV_l1, and the fourth difference AV_u1 can be adjusted to reduce program disturb as follows.

[0083] When programming the word lines of the upper stack 110, the first difference AV_u0 can be adjusted to be lower than the threshold TH11. The second difference AV_l0 can be adjusted to be lower than the second threshold TH12. The third difference AV_l1 can be adjusted to be lower than the first threshold TH11. The fourth difference AV_u1 can be adjusted to be higher than the second threshold TH12. In other words, after the adjustment, AV_u0 = V_u0 - Vt_u0 < TH11, AV_l0 = V_l0 - Vt_l0 < TH12, AV_l1 = V_l1 - Vt_l1 < TH11, and AV_u1 = V_u1 - Vt_u1 > TH12. For example, the first threshold TH11 can be 11 volts, and the second threshold TH12 can be 7 volts.

[0084] Further, according to embodiments, it can also be necessary to satisfy one of condition (c-3) and condition (c-4) in order to reduce Figure 7 the program disturb of the memory 100.

[0085] Condition (c-3) can include that a difference between the fourth difference AV_u1 and the first difference AV_u0 can be within a predetermined range, and another difference between the fourth difference AV_u1 and the second difference AV_l0 can be within the predetermined range.

[0086] The predetermined range in relation to condition (c-3) can be within a range of a level L5 and a level L6 that is higher than the level L3. Thus, in other words, condition (c-3) can be expressed as L5 < (AV_u1 - AV_u0) < L6 and L5 < (AV_u1 - AV_l0) < L6. For example, the level L5 can be 3 volts, and the level L6 can be 7 volts.

[0087] Condition (c-4) can include that a difference between the fourth difference AV_u1 and the second difference AV_l0 can be within a predetermined range, and another difference between the fourth difference AV_u1 and the third difference AV_l1 can be within the predetermined range.

[0088] The predetermined range in relation to condition (c-4) can be within a range of a level L7 and a level L8 that is higher than the level L7. Thus, in other words, condition (c-4) can be expressed as L7 < (AV_u1 - AV_l0) < L8 and L7 < (AV_u1 - AV_l1) < L8. For example, the level L7 can be 3 volts, and the level L8 can be 7 volts.

[0089] In terms of Figure 7 the equations and inequalities in relation to the differences AV_u0, AV_l0, AV_l1 and AV_u1 mentioned above can be applied when programming the word lines of the upper stack 110.

[0090] The differences AV_u0, AV_l0, AV_l1 and AV_u1 can not be limited when programming the word lines of the lower stack 120; however, according to experiments, the differences AV_u0, AV_l0, AV_l1 and AV_u1 can be higher than a threshold value (e.g., 3 volts).

[0091] Figure 9 is controlling Figure 7waveform of the memory 100. According to embodiments, the memory 100 can further include a top select gate electrode (denoted as TSG), a select word line (denoted as Sel WL), an unselect word line (denoted as Unsel WL), a dummy word line (denoted as Dummy WL), a select bit line (denoted as Sel BL), and a bottom select gate electrode (denoted as BSG) for controlling both the upper stack 110 and the lower stack 120.

[0092] As shown in Figure 9 , a pre-pulse operation can be performed before the program operation. A failure of the program operation can be avoided by performing the pre-pulse operation.

[0093] As shown in Figure 9 , before the pre-pulse operation, 0 volts can be applied to the select word line (Sel WL), the dummy word line (Dummy WL), the select bit line (Sel BL), and the bottom select gate electrode (BSG). The first upper bias voltage V_u0, the first lower bias voltage V_l0, the second lower bias voltage V_l1, and the second upper bias voltage V_u1 can be set to 0 volts.

[0094] The first upper bias voltage V_u0, the first lower bias voltage V_l0, the second lower bias voltage V_l1, and the second upper bias voltage V_u1 can be set to a pre-pulse level Vp during the pre-pulse operation. Thereafter, the first upper bias voltage V_u0, the first lower bias voltage V_l0, the second lower bias voltage V_l1, and the second upper bias voltage V_u1 can be set to a program level Vpass during the program operation.

[0095] During the program operation, a voltage having the program level Vpass can be applied to the unselect word line (Unsel WL) and the dummy word line (Dummy WL). The voltage applied to the select word line (Sel WL) can be raised to the level Vpgm.

[0096] As shown in Figure 9 , during the program operation, 0 volts can be applied to the top select gate electrode (TSG) and the bottom select gate electrode (BSG). After the program operation, the select word line (Sel WL), the unselect word line (Unsel WL), the dummy word line (Dummy WL), the select bit line (Sel BL), and the bias voltages V_u0, V_l0, V_l1, and V_u1 can be set to be floating.

[0097] In Figure 9In this process, the pre-pulse level Vp can be higher than the maximum permissible level Vt_max of the first upper threshold voltage Vt_u0, the first lower threshold voltage Vt_l0, the second lower threshold voltage Vt_l1, and the second upper threshold voltage Vt_u1.

[0098] Figure 9 The bias voltages V_u0, V_l0, V_l1, and V_u1 can be supplied by the same voltage source to reduce the number of voltage sources.

[0099] Figure 10 Controlled according to another embodiment Figure 7 The waveform of memory 100. Figure 10 Can be with Figure 9 Similar. The description will not be repeated. Figure 10 and Figure 9 Similarities.

[0100] and Figure 9 Similarly, in Figure 10 In this context, a pre-pulse operation can be performed before the programming operation.

[0101] During the pre-pulse operation, the first upper bias voltage V_u0, the first lower bias voltage V_l0, the second lower bias voltage V_l1, and the second upper bias voltage V_u1 can be set to the first pre-pulse level Vp1, the second pre-pulse level Vp2, the third pre-pulse level Vp3, and the fourth pre-pulse level Vp4, respectively.

[0102] During the programming operation, the first upper bias voltage V_u0, the first lower bias voltage V_l0, the second lower bias voltage V_l1, and the second upper bias voltage V_u1 can be set to the first programming level Vpass1, the second programming level Vpass2, the third programming level Vpass3, and the fourth programming level Vpass4, respectively.

[0103] exist Figure 10 In this process, each of the first prepulse level Vp1, the second prepulse level Vp2, the third prepulse level Vp3, and the fourth prepulse level Vp4 can be higher than the maximum permissible level Vt_max of the first upper threshold voltage Vt_u0, the first lower threshold voltage Vt_l0, the second lower threshold voltage Vt_l1, and the second upper threshold voltage Vt_u1.

[0104] exist Figure 10 In this configuration, the bias voltages V_u0, V_l0, V_l1, and V_u1 can be supplied individually, thus providing better controllability and flexibility.

[0105] When programming the word lines of the lower stack 120, the following can be applied: Figure 9 and Figure 10waveforms. When programming the word lines of the upper stack 110, the bias voltages V_u0, V_l0, V_l1, and V_u1 can be 0 volts during the pre-pulse operation.

[0106] Figure 11 to 14 A memory 1100 according to different embodiments is shown. Similar to the memory 100 described above, the memory 1100 can include an upper stack 110 and a lower stack 120. However, the memory 1100 can not include the tie oxide layer 155 shown. Compared to the memory 100, the program disturbance can be more severe when programming the memory 1100. Figure 1

[0107] Figure 11 to 14 Similar to Figure 1 , Figure 3 , Figure 5 and Figure 7 respectively.

[0108] The equations and inequalities corresponding to those described above Figure 1 , Figure 3 , Figure 5 and Figure 7 may be applied to Figure 11 to 14 respectively to reduce the program disturbance. The description of these equations and inequalities will not be repeated.

[0109] In summary, by adjusting the bias voltages and threshold voltages related to dummy word lines (e.g., IDMY_u0, IDMY_l0, IDMY_l1, and IDMY_u1 mentioned above) in three-dimensional memory, the program disturbance can be reduced. According to embodiments, the program disturbance that occurs when programming the word lines of the upper stack can be better reduced. As a result, the problems in the art can be alleviated.

[0110] Those skilled in the art will readily observe that numerous modifications and changes can be made to the devices and methods described without departing from the teachings of the present application. Accordingly, the disclosures herein should be understood to be illustrative only. The appended claims should be understood to include the items set forth in the description, which operate for the methods described herein, and which are by way of example only.​

Claims

1. A method for operating a memory, the memory including an upper stack and a lower stack, the upper stack being formed above the lower stack, the upper stack including a first upper dummy word line, the lower stack including a first lower dummy word line, the method comprising, when programming the word lines of the memory: A first upper bias voltage is applied to the first upper dummy word line, such that the difference between the first upper bias voltage and the first upper threshold voltage of the memory cell connected to the first upper dummy word line is a first difference value. A first lower bias voltage is applied to the first lower dummy word line, such that the difference between the first lower bias voltage and the first lower threshold voltage of the memory cell connected to the first lower dummy word line is a second difference. The first difference and the second difference are adjusted to reduce interference with memory programming.

2. The method according to claim 1, wherein, The adjustment of the first difference includes: Adjust the first upper bias voltage and / or adjust the first upper threshold voltage.

3. The method according to claim 1, wherein, Adjusting the second difference includes: Adjust the first lower bias voltage and / or adjust the first lower threshold voltage.

4. The method according to claim 1, wherein: The first difference is adjusted to be below the threshold; The second difference is adjusted to be below the threshold.

5. The method according to claim 1, wherein: The first difference is adjusted to be higher than the threshold; The second difference is adjusted to be higher than the threshold.

6. The method according to claim 1, wherein, The lower stack body further includes a second lower dummy character line; the method further includes: A second lower bias voltage is applied to the second lower dummy word line, such that the difference between the second lower bias voltage and the second lower threshold voltage of the memory cell connected to the second lower dummy word line is a third difference. The first difference, the second difference, and the third difference are adjusted so that the difference between the first difference and the second difference is within a predetermined range, and the difference between the first difference and the third difference is within the predetermined range.

7. The method according to claim 6, wherein, Adjusting the third difference includes: Adjust the second lower bias voltage and / or the second lower threshold voltage.

8. The method according to claim 6, wherein: The first difference is adjusted to be higher than the threshold; The second difference is adjusted to be below the threshold; The third difference is adjusted to be below the threshold.

9. The method according to claim 1, wherein, The upper stack body further includes a second upper dummy word line, and the method further includes: A second upper bias voltage is applied to the second upper dummy word line, such that the difference between the second upper bias voltage and the second upper threshold voltage of the memory cell connected to the second upper dummy word line is a fourth difference. The first difference, the second difference, and the fourth difference are adjusted so that the difference between the fourth difference and the first difference is within a predetermined range, and the difference between the fourth difference and the second difference is within the predetermined range.

10. The method according to claim 9, wherein, Adjusting the fourth difference includes: Adjust the second upper bias voltage and / or the second upper threshold voltage.

11. The method according to claim 9, wherein: The first difference is adjusted to be below the threshold; The second difference is adjusted to be below the threshold; The fourth difference is adjusted to be higher than the threshold.

12. The method according to claim 1, wherein, The upper stack further includes a second upper dummy character line, the lower stack further includes a second lower dummy character line, and the method further includes: A second lower bias voltage is applied to the second lower dummy word line, such that the difference between the first lower bias voltage and the second lower threshold voltage of the memory cell connected to the second lower dummy word line is a third difference. A second upper bias voltage is applied to the second upper dummy word line, such that the difference between the second upper bias voltage and the second upper threshold voltage of the memory cell connected to the second upper dummy word line is a fourth difference. Adjust the first difference, the second difference, the third difference, and the fourth difference so that the difference between the fourth difference and the first difference is within a predetermined range and the difference between the fourth difference and the second difference is within the predetermined range, or make the difference between the fourth difference and the first difference within a predetermined range and the difference between the fourth difference and the second difference within the predetermined range.

13. The method according to claim 12, wherein: The first difference is adjusted to be below the first threshold; The second difference is adjusted to be below the second threshold; The third difference is adjusted to be lower than the first threshold; The fourth difference is adjusted to be higher than the second threshold.

14. The method according to claim 12, further comprising: During the pre-pulse operation, the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage are set to the pre-pulse level; as well as During programming operations, the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage are set to the programming level Vpass; Wherein, the prepulse level is higher than the maximum permissible level of the first upper threshold voltage, the first lower threshold voltage, the second lower threshold voltage, and the second upper threshold voltage.

15. The method according to claim 12, further comprising: During the pre-pulse operation, the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage are respectively set to the first pre-pulse level, the second pre-pulse level, the third pre-pulse level, and the fourth pre-pulse level; as well as During programming operations, the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage are respectively set to the first programming level Vpass1, the second programming level Vpass2, the third programming level Vpass3, and the fourth programming level Vpass4. Wherein, each of the first prepulse level, the second prepulse level, the third prepulse level, and the fourth prepulse level is higher than the maximum permissible level of the first upper threshold voltage, the first lower threshold voltage, the second lower threshold voltage, and the second upper threshold voltage.

16. A memory comprising: Upper stack body, the upper stack body including a first upper dummy word line; A lower stack body, the lower stack body including a first lower dummy word line; wherein, the upper stack body is formed above the lower stack body; and control circuitry coupled to the first upper dummy word line and the first lower dummy word line; wherein, The control circuit is configured to: when programming the word line of the memory, apply a first upper bias voltage to the first upper dummy word line, such that the difference between the first upper bias voltage and a first upper threshold voltage of the memory cell connected to the first upper dummy word line is a first difference; and apply a first lower bias voltage to the first lower dummy word line, such that the difference between the first lower bias voltage and a first lower threshold voltage of the memory cell connected to the first lower dummy word line is a second difference; The first difference and the second difference are adjusted to reduce interference with memory programming.

17. The memory according to claim 16, wherein, The adjustment of the first difference and the second difference includes: Adjust the first upper bias voltage and / or adjust the first upper threshold voltage to adjust the first difference; Adjust the first lower bias voltage and / or adjust the first lower threshold voltage to adjust the second difference.

18. The memory according to claim 16, wherein, The lower stack also includes a second lower dummy word line, and the control circuit is further configured to: apply a second lower bias voltage to the second lower dummy word line, such that the difference between the second lower bias voltage and the second lower threshold voltage of the memory cell connected to the second lower dummy word line is a third difference; The first difference, the second difference, and the third difference are adjusted so that the difference between the first difference and the second difference is within a predetermined range, and the difference between the first difference and the third difference is within the predetermined range.

19. The memory according to claim 18, wherein, Adjusting the third difference includes: adjusting the second lower bias voltage and / or adjusting the second lower threshold voltage to adjust the third difference.

20. The memory according to claim 16, wherein, The upper stack also includes a second upper dummy word line, and the control circuit is further configured to: apply a second upper bias voltage to the second upper dummy word line, such that the difference between the second upper bias voltage and the second upper threshold voltage of the memory cell connected to the second upper dummy word line is a fourth difference. The first difference, the second difference, and the fourth difference are adjusted so that the difference between the fourth difference and the first difference is within a predetermined range, and the difference between the fourth difference and the second difference is within the predetermined range.

21. The memory according to claim 20, wherein, Adjusting the fourth difference includes: Adjust the second upper bias voltage and / or adjust the second upper threshold voltage to adjust the fourth difference.

22. The memory of claim 16, further comprising a connector oxide layer formed between the upper stack and the lower stack.

23. The memory of claim 16, further comprising a top select gate electrode, select word lines, unselected word lines, dummy word lines, select bit lines, and a bottom select gate electrode.

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