Fault signal holding circuit, detection device, and electronic device

Abstract

The application discloses a kind of fault signal holding circuit, detection device and electronic equipment, it is related to power electronics technical field.Fault signal holding circuit includes: detection circuit, trigger circuit and feedback circuit, detection circuit receives detection signal, and when the detection signal meets fault condition, first fault signal is generated, when receiving first fault signal, trigger signal with gradually reduced voltage is generated;Feedback circuit receives trigger signal, and when the voltage of trigger signal is greater than or equal to preset voltage, second fault signal is transmitted to main control circuit.The application is kept and eliminated to fault signal by the signal that can automatically attenuate, and additional setting elimination loop is not needed in main control circuit, and cost is lower;It can also form self-locking automatically, and detection accuracy is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a fault signal maintaining circuit, a detection device and electronic equipment. BACKGROUND

[0002] In a power system, a safety protection function is usually provided, which mainly detects the power system and feeds back a fault signal to a controller when a fault occurs. In order to ensure that the controller can effectively capture the fault signal, the fault signal needs to be maintained for a period of time. However, most signal maintaining functions need to be released by the controller, that is, an elimination loop needs to be added, thereby increasing the design cost. SUMMARY

[0003] The main purpose of the present application is to provide a fault signal maintaining circuit, a detection device and electronic equipment, which aims to solve the technical problem that the signal maintaining function needs to be released by the controller and an elimination loop needs to be added in the prior art, thereby increasing the design cost.

[0004] To achieve the above purpose, the present application provides a fault signal maintaining circuit, which comprises:

[0005] a detection circuit configured to receive a detection signal and generate a first fault signal when the detection signal meets a fault condition;

[0006] a trigger circuit connected with the detection circuit and configured to generate a trigger signal with gradually decreasing voltage when receiving the first fault signal;

[0007] a feedback circuit connected with the detection circuit, the trigger circuit and a main control circuit, and configured to receive the trigger signal and transmit a second fault signal to the main control circuit and a maintaining signal to the detection circuit when the voltage of the trigger signal is greater than or equal to a preset voltage, wherein the maintaining signal meets the fault condition.

[0008] Optionally, the first fault signal is a high-level signal, and the trigger circuit comprises:

[0009] a charge-discharge circuit connected with the feedback circuit and configured to charge by using the first fault signal when receiving the first fault signal and discharge to generate the trigger signal after the charging is completed.

[0010] Optionally, the charge-discharge circuit comprises a first capacitor and a first resistor.

[0011] A first end of the first capacitor is connected with a first end of the first resistor and the feedback circuit, a second end of the first resistor is grounded, and a second end of the first capacitor is used for connecting the fault signal.

[0012] Optionally, the fault signal maintaining circuit further comprises:

[0013] The sampling circuit is connected with the detection circuit and the detected target respectively, and is configured to generate a detection signal according to the running state of the detected target.

[0014] Optionally, the sampling circuit comprises a second capacitor, a second resistor and a third resistor.

[0015] The first end of the second resistor is connected with the detected target, the second end of the second resistor is connected with the first end of the third resistor, the first end of the second capacitor and the input end of the detection circuit respectively, and the second end of the third resistor and the second end of the second capacitor are grounded.

[0016] Optionally, the detection circuit comprises a first OR gate.

[0017] The first input end of the first OR gate is connected with the sampling circuit, the second input end of the first OR gate is connected with the feedback circuit, and the output end of the first OR gate is connected with the trigger circuit.

[0018] Optionally, the feedback circuit comprises a second OR gate.

[0019] The first input end and the second input end of the second OR gate are both connected with the trigger circuit, and the output end of the second OR gate is connected with the second input end of the first OR gate and the main control circuit respectively.

[0020] Optionally, the feedback circuit further comprises a third capacitor, a fourth capacitor, a fourth resistor and a fifth resistor.

[0021] The fourth resistor is arranged between the output end of the second OR gate and the main control circuit, the first end of the third capacitor, the first end of the fourth resistor and the first end of the fifth resistor are all connected with the output end of the second OR gate, the second end of the fourth resistor is connected with the first end of the fourth capacitor and the main control circuit respectively, and the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fifth resistor are all grounded.

[0022] To achieve the above object, the application further provides a detection device, which comprises the fault signal holding circuit.

[0023] To achieve the above object, the application further provides an electronic device, which comprises the detection device.

[0024] In the present application, the fault signal maintaining circuit is formed by setting the trigger circuit and the feedback circuit. The feedback circuit is connected with the trigger circuit and the main control circuit. The trigger circuit is configured to generate the trigger signal with gradually reduced voltage when receiving the first fault signal. The feedback circuit is configured to receive the trigger signal and transmit the second fault signal to the main control circuit when the voltage of the trigger signal is greater than or equal to the preset voltage. The present application can maintain the fault signal by the signal capable of automatic attenuation, and does not need to additionally set the elimination loop in the main control circuit, so that the cost is lower. The self-locking can be automatically formed, and the detection accuracy is higher. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.

[0026] Figure 1 The structural block diagram of the first embodiment of the fault signal maintaining circuit of the present application is shown in the figure.

[0027] Figure 2 The structural block diagram of the second embodiment of the fault signal maintaining circuit of the present application is shown in the figure.

[0028] Figure 3 The structural block diagram of the third embodiment of the fault signal maintaining circuit of the present application is shown in the figure.

[0029] Figure 4 The structural block diagram of the fourth embodiment of the fault signal maintaining circuit of the present application is shown in the figure.

[0030] Figure 5 The circuit principle diagram of an embodiment of the fault signal maintaining circuit of the present application is shown in the figure.

[0031] Explanation of the reference signs:

[0032] Reference Name Reference Name 10 Detection circuit 60 Sampling circuit 20 Trigger circuit R1~R5 First to fifth resistors 30 Feedback circuit C1~C5 First to fifth capacitors 40 Master control circuit U1~U2 First to second OR gates 50 Charge and discharge circuit

[0033] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the drawings. DETAILED DESCRIPTION

[0034] It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0035] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the scope of the present application.

[0036] It should be noted that all the direction indications (such as up, down, left, right, front, back, and the like) in the embodiments of the present application are only used to explain the relative position relationship, movement condition and the like between components in a certain posture (as shown in the drawings), and if the certain posture changes, the direction indications also change accordingly.

[0037] In addition, the descriptions of “first”, “second” and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope of the present application.

[0038] With reference to Figure 1 , Figure 1 This is a structural block diagram of a first embodiment of a fault signal holding circuit of the present application. The present application proposes a first embodiment of a fault signal holding circuit.

[0039] In the first embodiment, the fault signal holding circuit includes a detection circuit 10, a trigger circuit 20 and a feedback circuit 30, the detection circuit 10 is connected with the trigger circuit 20, and the feedback circuit 30 is connected with the detection circuit 10, the trigger circuit 20 and a master control circuit 40. The detection circuit 10 is configured to receive a detection signal, and generate a first fault signal when the detection signal meets a fault condition. The trigger circuit 20 is configured to generate a trigger signal with gradually decreasing voltage when receiving the first fault signal. The feedback circuit 30 is configured to receive the trigger signal, and transmit a second fault signal to the master control circuit 40 when the voltage of the trigger signal is greater than or equal to a preset voltage.

[0040] It should be noted that the detection signal can be a signal fed back by the detected target, which can represent the state of the detected target. The detected target can be a power loop or an integrated component, etc. The fault condition can be a set voltage value. For example, when the voltage of the detection signal is greater than the set voltage, it is considered that the detection signal satisfies the fault condition; such a way is usually used for overcurrent detection. Alternatively, when the voltage of the detection signal is less than the set voltage, it is considered that the detection signal satisfies the fault condition; such a way is usually used for power failure detection. Therefore, the specific content of the fault condition can be determined according to the detection method, which is not limited in the embodiment.

[0041] The first fault signal and the second fault signal can be electrical signals with a certain voltage. The main control circuit 40 is the control center of the power system, which is used to drive the operation of the power system. The first fault signal can be an electrical signal fed back by the power system when it is in a fault state, which is mainly used to inform the main control circuit 40 that there is a fault in the power system, which can be a high-level signal or a low-level signal. For example, in a switching power supply system, the main control circuit 40 can be used to control the start and stop of the switching power supply, as well as the output power of the switching power supply, etc. When the main loop is in an overcurrent state, the first fault signal is sent to the fault signal holding circuit, and the fault signal holding circuit feeds back the second fault signal to the main control circuit 40. When the main control circuit 40 receives the second fault signal, it determines that the main loop is in an overcurrent state. Alternatively, when the fault signal holding circuit is applied to monitor an integrated component (such as a frequency converter or an inverter, etc.), the first fault signal is sent to the fault signal holding circuit when the integrated component is in a fault state, and the fault signal holding circuit feeds back the second fault signal to the main control circuit 40. When the main control circuit 40 receives the second fault signal, it determines that the component is in a fault state.

[0042] In the embodiment, when the voltage of the trigger signal is less than the preset voltage, the feedback circuit 30 stops outputting the feedback signal. Therefore, the maintenance time of the feedback signal is the time during which the fault signal can be effectively fed back to the main control circuit 40, which is the maintenance time of the voltage of the trigger signal in the interval greater than the preset voltage. Assuming that the initial voltage of the trigger signal is V1 and the preset voltage is V2, the maintenance time T = (V1-V2) / S, starting from the beginning of the decay of the trigger signal. Wherein, S is the voltage decay rate of the trigger signal. Therefore, the fault signal holding circuit can hold the fault signal, so that the main control circuit 40 can effectively capture it, and it can be automatically eliminated without the need for control by the main control circuit.

[0043] It should be noted that, since the fault in the power system can be small, the detection signal fed back by the detected target can meet the fault condition in a short time and then return to normal. At this time, the detection circuit 10 can only generate the first fault signal in a short time, which can cause the trigger signal output by the trigger circuit 20 to decay too fast, and the capture time of the master control circuit 40 is short, so that the master control circuit 40 can not be effectively captured. To avoid this problem, the feedback circuit 30 transmits the holding signal to the detection circuit at the same time of transmitting the feedback signal to the master control circuit. Since the holding signal also meets the fault condition, the detection circuit 10 forms a self-locking, that is, even if the detection signal no longer meets the fault condition, the detection circuit 10 can still output the fault signal.

[0044] Referring to Figure 2 , Figure 2 The structure block diagram of the second embodiment of the fault signal holding circuit of the present application is shown in FIG. 4. In the specific implementation, the first fault signal can be a high-level signal, and the trigger circuit 20 can include a charge-discharge circuit 50 connected with the feedback circuit 30. The charge-discharge circuit 50 charges by using the first fault signal when receiving the first fault signal, and discharges after the charging is completed to generate the trigger signal.

[0045] In the present embodiment, the charge-discharge circuit 50 can charge by using the first fault signal and discharge after the charging is completed. Since the discharge voltage gradually decays in the discharging process, the discharge voltage can be used as the trigger signal. The feedback circuit 30 generates the feedback signal before the discharge voltage drops to the preset voltage.

[0046] Referring to Figure 3 , Figure 3 The structure block diagram of the third embodiment of the fault signal holding circuit of the present application is shown in FIG. 5. In the present embodiment, the charge-discharge circuit 50 can include a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is connected with the first end of the first resistor R1 and the feedback circuit 30 respectively, the second end of the first resistor R1 is grounded, and the second end of the first capacitor C1 is used to access the fault signal.

[0047] In the present embodiment, the RC circuit is used to realize the saving and recovery of the signal. When the fault signal is accessed to the second end of the first capacitor C1, the first capacitor C1 starts to charge. Since the fault signal is usually a direct current signal, under the action of the direct current isolation of the first capacitor C1, the first capacitor C1 will discharge through the discharge loop formed by the first end and the first resistor R1 after being fully charged. The RC circuit structure of the present embodiment is simple and has a lower cost. Therefore, in the case of cost limitation, the RC circuit is more easily realized to save and recover the signal.

[0048] In this embodiment, the fault signal holding circuit includes a trigger circuit 20 and a feedback circuit 30, with the feedback circuit 30 connected to both the trigger circuit 20 and the main control circuit 40. The trigger circuit 20 is configured to generate a trigger signal with a gradually decreasing voltage upon receiving a first fault signal. The feedback circuit 30 is configured to receive the trigger signal and, when the voltage of the trigger signal is greater than or equal to a preset voltage, transmit a second fault signal to the main control circuit 40. This embodiment holds the fault signal using an automatically attenuating signal, eliminating the need for an additional cancellation circuit in the main control circuit, resulting in lower costs; it also automatically forms a self-locking mechanism, leading to higher detection accuracy.

[0049] Reference Figure 4 , Figure 4 This is a structural block diagram of a fourth embodiment of the fault signal holding circuit of the present invention. Based on the first embodiment described above, the present invention proposes a second embodiment of the fault signal holding circuit.

[0050] In the second embodiment, the fault signal holding circuit may further include a sampling circuit 60, which is connected to both the detection circuit 10 and the target being detected. The sampling circuit 60 is configured to generate a detection signal based on the operating state of the target being detected.

[0051] In this embodiment, the fault signal holding circuit also includes a sampling section for sampling the target being detected. Since the actual voltage or current of the main circuit is often large, making direct detection difficult, a sampling circuit 60 is used to convert the voltage or current of the main circuit. The detection circuit 10 then judges the converted voltage or current.

[0052] Reference Figure 5 , Figure 5 This is a circuit diagram of an embodiment of the fault signal holding circuit of the present invention.

[0053] In this embodiment, the sampling circuit 60 may include a second capacitor C2, a second resistor R2, and a third resistor R3. The first end of the second resistor R2 is connected to the target being detected, and the second end of the second resistor R2 is connected to the first end of the third resistor R3, the first end of the second capacitor C2, and the input terminal of the detection circuit 10, respectively. The second end of the third resistor R3 and the second end of the second capacitor C2 are both grounded.

[0054] like Figure 5 As shown, terminal vin is used to receive the signal fed back from the target being detected, and terminal vin is connected to the first end of the second resistor C2. The second resistor R2 and the third resistor R3 form a voltage divider circuit to adjust the voltage of the signal fed back from the target being detected to the voltage range allowed by the detection circuit 10. The second capacitor C2 is used for voltage stabilization, making the input of the detection circuit 10 more stable.

[0055] In the embodiment, the detection circuit 10 comprises a first OR gate U1. The first input terminal 1A of the first OR gate U1 is connected with the sampling circuit 60, the second input terminal 1B of the first OR gate U1 is connected with the feedback circuit 30, and the output terminal 1Y of the first OR gate U1 is connected with the second terminal of the first capacitor C1 in the trigger circuit 20.

[0056] It should be noted that when the detected target is in a fault state, the feedback signal is high. At this time, the first input terminal 1A of the first OR gate U1 is high, and the output terminal 1Y of the first OR gate U1 outputs high, generating a fault signal. The power supply terminal VCC is used to supply power to the first OR gate U1, and the fifth capacitor C5 is used to maintain the stability of the power supply of the first OR gate U1.

[0057] In the embodiment, the feedback circuit 30 can comprise a second OR gate U2. The first input terminal 1A and the second input terminal 1B of the second OR gate U2 are both connected with the first terminal of the first capacitor C1 in the trigger circuit 20, and the output terminal 1Y of the second OR gate U2 is connected with the second input terminal 1B of the first OR gate U1 and the master control circuit 40, respectively.

[0058] It can be understood that when the output terminal 1Y of the first OR gate U1 outputs high, the voltage of the second terminal of the first capacitor C1 is pulled high, and the first capacitor C1 starts to charge. Since the second terminal of the first capacitor C1 is directly connected with the output terminal 1Y of the first OR gate U1, the first capacitor C1 can complete charging in a short time. When the first capacitor C1 is fully charged, the input of the second OR gate U2 is high, and the output terminal 1Y of the second OR gate U2 is also high. Due to the direct current blocking effect of the first capacitor C1, after charging is completed, the first capacitor C1 starts to discharge through the first resistor R1, and the first terminal of the first capacitor C1 gradually decreases. When the first terminal of the first capacitor C1 is less than the minimum input voltage required by the second OR gate U2 to maintain the output high, the output terminal 1Y of the second OR gate U2 becomes low. The discharge time of the first capacitor C1 is:

[0059]

[0060] Wherein, Vcc is the chip power supply voltage of the first OR gate U1, Vic is the minimum input voltage required by the second OR gate U2 to maintain the output high, R1 is the resistance value of the first resistor, and C1 is the capacitance value of the first capacitor.

[0061] When the output terminal 1Y of the second OR gate U2 is high, the corresponding connection port Vout of the master control circuit 40 is also high. The master control circuit 40 captures the fault signal by detecting the voltage of the connection port Vout. Meanwhile, the second input terminal 1B of the first OR gate U1 is also pulled high by the output terminal 1Y of the second OR gate U2, forming a self-locking; at this time, even if the second input terminal 1B of the first OR gate U1 becomes low, the output terminal 1Y of the first OR gate U1 also remains high. When the output terminal 1Y of the second OR gate U2 becomes low, the second input terminal 1B of the first OR gate U1 becomes low, and the self-locking is released. The output of the first OR gate U1 depends on the level of the first input terminal 1A of the first OR gate U1. In addition, since the output terminal 1Y of the first OR gate U1 is a direct current signal, the first capacitor C1 does not charge after the discharge is completed, and the first terminal of the first capacitor C1 maintains low.

[0062] In addition, in the embodiment, the feedback circuit 30 can further include a third capacitor C3, a fourth capacitor C4, a fourth resistor R4 and a fifth resistor R5. The fourth resistor R4 is arranged between the output terminal 1Y of the second OR gate U2 and the master control circuit 40, the first terminal of the third capacitor C3, the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5 are all connected with the output terminal 1Y of the second OR gate U2, the second terminal of the fourth resistor R4 is respectively connected with the first terminal of the fourth capacitor C4 and the master control circuit 40, and the second terminal of the third capacitor C3, the second terminal of the fourth capacitor C4 and the second terminal of the fifth resistor R5 are all grounded.

[0063] It can be understood that the third capacitor C3, the fourth capacitor C4, the fourth resistor R4 and the fifth resistor R5 form a filter circuit to maintain the output of the output terminal 1Y of the second OR gate U2 stable, so that the master control circuit 40 can effectively detect the output.

[0064] In the embodiment, the fault signal holding circuit is composed of two OR gate chips combined with an RC discharge circuit, which realizes the saving and self-elimination of the fault signal without the participation of the master control circuit, has lower cost and is easier to implement.

[0065] To achieve the above object, the application further provides a detection device comprising the fault signal holding circuit as described above. The specific structure of the fault signal holding circuit is referred to the above embodiments. Since the detection device can adopt all the technical solutions of the above embodiments, it has at least the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0066] To achieve the above object, the application further provides an electronic device comprising the detection device as described above. The specific structure of the detection device is referred to the above embodiments. Since the electronic device can adopt the technical solutions of all the above embodiments, it has at least the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0067] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A failure signal holding circuit characterized by comprising: The fault signal holding circuit comprises: a detection circuit configured to receive a detection signal and generate a first fault signal when the detection signal meets a fault condition; a trigger circuit connected with the detection circuit and configured to generate a trigger signal with gradually decreasing voltage when receiving the first fault signal; a feedback circuit connected with the detection circuit, the trigger circuit and a master control circuit, and configured to receive the trigger signal, transmit a second fault signal to the master control circuit when the voltage of the trigger signal is greater than or equal to a preset voltage, and feed back a holding signal to the detection circuit, wherein the holding signal meets the fault condition.

2. The fault signal holding circuit according to claim 1, wherein The first fault signal is a high-level signal, and the trigger circuit comprises: a charge-discharge circuit connected with the feedback circuit and configured to charge by using the first fault signal when receiving the first fault signal, and discharge after the charging is completed to generate a trigger signal.

3. The fault signal holding circuit according to claim 2, wherein The charge-discharge circuit comprises a first capacitor and a first resistor; a first end of the first capacitor is connected with a first end of the first resistor and the feedback circuit, a second end of the first resistor is grounded, and a second end of the first capacitor is used for connecting the fault signal.

4. The fault signal holding circuit according to any one of claims 1 to 3, wherein The fault signal holding circuit further comprises: a sampling circuit connected with a detected target and the detection circuit, and configured to generate a detection signal according to an operating state of the detected target.

5. The fault signal retention circuit of claim 4, wherein, The sampling circuit comprises a second capacitor, a second resistor and a third resistor; a first end of the second resistor is connected with the detected target, a second end of the second resistor is connected with a first end of the third resistor, a first end of the second capacitor and an input end of the detection circuit, respectively, and a second end of the third resistor and a second end of the second capacitor are both grounded.

6. The fault signal holding circuit according to any one of claims 1 to 3, wherein The detection circuit comprises a first OR gate; a first input end of the first OR gate is connected with the sampling circuit, a second input end of the first OR gate is connected with the feedback circuit, and an output end of the first OR gate is connected with the trigger circuit.

7. The fault signal retention circuit of claim 6, wherein, The feedback circuit comprises a second OR gate; a first input end and a second input end of the second OR gate are both connected with the trigger circuit, and an output end of the second OR gate is connected with a second input end of the first OR gate and the master control circuit, respectively.

8. The fault signal retention circuit of claim 7, wherein, The feedback circuit further comprises a third capacitor, a fourth capacitor, a fourth resistor and a fifth resistor; the fourth resistor is arranged between the output end of the second OR gate and the master control circuit, a first end of the third capacitor, a first end of the fourth resistor and a first end of the fifth resistor are all connected with the output end of the second OR gate, a second end of the fourth resistor is connected with a first end of the fourth capacitor and the master control circuit, respectively, and a second end of the third capacitor, a second end of the fourth capacitor and a second end of the fifth resistor are all grounded.

9. A detection device, characterized in that The detection device comprises the fault signal holding circuit according to any one of claims 1-8.

10. An electronic device, comprising: The electronic equipment comprises the detection device according to claim 9.

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