Data Output Buffer and Non-Volatile Memory Chip

Abstract

The present application relates to the technical field of data output buffers, and discloses a data output buffer, which includes a parasitic capacitance to ground. One end is connected to a buffer circuit and a comparison circuit, and the other end is grounded. The buffer circuit is used to receive data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range. The comparison circuit is used to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground, compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result. In this way, the amplitude of the capacitance voltage of the parasitic capacitance to ground can be adjusted, thereby changing the current magnitude of the data output port of the data output buffer, so that the non-volatile memory chip using the data output buffer operates stably. The present application also discloses a non-volatile memory chip.

Description

Technical Field

[0001] The present application relates to the technical field of data output buffers, for example, to a data output buffer and a non-volatile memory chip. Background Art

[0002] Currently, data output buffers are usually used for data transmission. Commonly used data output buffers are Figure 1 As shown, the data input terminal 101 is connected to the gate of the ninth PMOS transistor 102 and the gate of the ninth NMOS transistor 103; the source of the ninth PMOS transistor 102 and the source of the tenth PMOS transistor 105 receive the power supply voltage; the drain of the ninth PMOS transistor 102 is connected to the drain of the ninth NMOS transistor 103, the gate of the tenth PMOS transistor 105, the gate of the tenth NMOS transistor 106, and one end of the capacitor 104; the other end of the capacitor 104, the source of the ninth NMOS transistor 103, and the source of the tenth MOS transistor are grounded;

[0003] The drain of the tenth PMOS transistor 105, the drain of the tenth NMOS transistor 106 and the data output terminal 107 are connected. Figure 1 The data output buffer is used for data transmission. The current of the data output port of the data output buffer is affected by the data bus width, the capacitance value of the capacitor, the capacitance voltage amplitude of the capacitor and the data flip time. The data bus width, the capacitance value of the capacitor and the data flip time are all fixed values. The capacitance voltage amplitude ranges from 0 to the power supply voltage value, such as Figure 2 Therefore, the output current of the data output buffer cannot be adjusted. When the current at the data output port of the data output buffer is large, abnormal ripple may appear at the power supply port, and noise may also appear in the power supply and ground network, causing unstable operation of the non-volatile memory chip using the data output buffer. Summary of the Invention

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, the following is a brief summary. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] Embodiments of the present disclosure provide a data output buffer and a non-volatile memory chip, which are capable of adjusting the current output by the data output buffer.

[0006] In some embodiments, a data output buffer includes: a parasitic capacitance to ground, one end of which is connected to a buffer circuit and a comparison circuit, and the other end of which is grounded; the buffer circuit is configured to receive data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range; the comparison circuit is configured to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground, compare the reference voltage with the capacitance voltage, and output the data to be output according to the comparison result.

[0007] In some embodiments, the buffer circuit includes: a first PMOS transistor, the source of the first PMOS transistor receives a first voltage, the gate of the first PMOS transistor receives the data to be output, and the drain of the first PMOS transistor is connected to the drain of a first NMOS transistor; the first NMOS transistor, the gate of the first NMOS transistor receives a second voltage, and the source of the first NMOS transistor is connected to the source of a second PMOS transistor and the parasitic capacitance to ground; the second PMOS transistor, the gate of the second PMOS transistor receives a third voltage, and the drain of the second PMOS transistor is connected to the drain of a second NMOS transistor; the second NMOS transistor, the gate of the second NMOS transistor receives the data to be output, and the source of the second NMOS transistor is grounded.

[0008] In some embodiments, the comparison circuit includes: a third PMOS transistor, the source of the third PMOS transistor receives a first voltage, the gate of the third PMOS transistor is connected to the gate of a fourth PMOS transistor, and the drain of the third PMOS transistor is connected to the drain of a third NMOS transistor; the fourth PMOS transistor, the source of the fourth PMOS transistor receives a first voltage, and the drain of the fourth PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of a fourth NMOS transistor; a fifth PMOS transistor, the source of the fifth PMOS transistor receives a first voltage, the gate of the fifth PMOS transistor is connected to the gate of a sixth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the gate of the fifth PMOS transistor and the drain of a fifth NMOS transistor; the sixth PMOS transistor, the source of the sixth PMOS transistor receives a first voltage, and the drain of the sixth PMOS transistor is connected to the drain of a sixth NMOS transistor; the third NMOS transistor, the drain of the third NMOS transistor is connected to the gate of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the third NMOS transistor is grounded;

[0009] A current source, one end is connected to the source electrodes of the fourth NMOS transistor and the fifth NMOS transistor, and the other end is grounded; for the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the parasitic capacitance to ground; for the fifth NMOS transistor, the gate of the fifth NMOS transistor receives a reference voltage; for the sixth NMOS transistor, the source of the sixth NMOS transistor is grounded.

[0010] In some embodiments, the first preset range is used to represent the voltage range in which the level signal is at a high level.

[0011] In some embodiments, the second preset range is used to represent the voltage range in which the level signal is at a low level.

[0012] In some embodiments, the data output buffer further includes: a reference voltage generation circuit, connected to the comparison circuit, for generating a reference voltage and outputting the reference voltage to the comparison circuit.

[0013] In some embodiments, the non-volatile memory chip includes the above-mentioned data output buffer.

[0014] In some embodiments, the non-volatile memory chip further includes: a storage array for storing data to be output; a row decoder electrically connected to the storage array; a column selector connected to the storage array and the data output buffer for outputting the data to be output to the data output buffer.

[0015] In some embodiments, the column selector is electrically connected to the data output buffer through a sense amplifier.

[0016] In some embodiments, the non-volatile memory chip further includes: a shift register, one end is electrically connected to the data output buffer, and the other end is electrically connected to a data output pin.

[0017] The data output buffer and non-volatile memory chip provided by the embodiments of the present disclosure can achieve the following technical effects: Through the parasitic capacitance to ground, one end is connected to the buffer circuit and the comparison circuit, and the other end is grounded; the buffer circuit is used to receive the data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range, and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range; the comparison circuit is used to receive the reference voltage and the capacitance voltage of the parasitic capacitance to ground; compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result. In this way, by adjusting the maximum capacitance voltage of the parasitic capacitance to ground to be within the first preset range and adjusting the minimum capacitance voltage of the parasitic capacitance to ground to be within the second preset range through the buffer circuit, the amplitude of the capacitance voltage of the parasitic capacitance to ground can be adjusted, thereby changing the current magnitude of the data output port of the data output buffer. By flexibly adjusting the current of the data output port of the data output buffer, the non-volatile memory chip using the data output buffer operates stably.

[0018] The above general description and the following description are only exemplary and explanatory, and are not used to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by the corresponding drawings. These exemplary illustrations and the drawings do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and among them:

[0020] Figure 1 is a schematic structural diagram of a data output buffer in the prior art;

[0021] Figure 2 is a schematic diagram of the voltage amplitude of a parasitic capacitance to ground in the prior art;

[0022] Figure 3 is a schematic structural diagram of a second data output buffer provided by the embodiments of the present disclosure;

[0023] Figure 4 is a schematic structural diagram of a third data output buffer provided by the embodiments of the present disclosure;

[0024] Figure 5 is a schematic diagram of the voltage amplitude of another parasitic capacitance to ground provided by the embodiments of the present disclosure;

[0025] Figure 6 is a schematic structural diagram of a fourth data output buffer provided by the embodiments of the present disclosure;

[0026] Figure 7 is a schematic structural diagram of a non-volatile memory chip provided by the embodiments of the present disclosure.

[0027] Reference numerals:

[0028] 1: parasitic capacitance to ground; 2: buffer circuit; 3: comparison circuit; 4: data output buffer; 5: memory array; 6: row decoder; 7: column selector; 8: sense amplifier; 9: shift register; 10: data output pin; 101: data input terminal; 102: ninth PMOS transistor; 103: ninth NMOS transistor; 104: capacitor; 105: tenth PMOS transistor; 106: tenth NMOS transistor; 107: data output terminal; 201: data input port to be output; 202: first voltage supply port; 203: second voltage supply port; 204: first PMOS transistor; 205: first NMOS transistor; 206: second PMOS transistor; 207: second NMOS transistor; 301: reference voltage output port; 302: voltage comparator; 303: data output port to be output; 304: third PMOS transistor; 305: fourth PMOS transistor; 306: fifth PMOS transistor; 307: sixth PMOS transistor; 308: third NMOS transistor; 309: fourth NMOS transistor; 310: fifth NMOS transistor; 311: sixth NMOS transistor; 312: current source; 401: seventh NMOS transistor; 402: eighth NMOS transistor; 403: seventh PMOS transistor; 404: eighth PMOS transistor. Detailed implementation manners

[0029] In order to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are only for reference and explanation purposes and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, numerous details are provided to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be shown in a simplified manner.

[0030] The terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the embodiments of the present disclosure are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0031] In the embodiments of the present disclosure, the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "middle", "outer", "front", and "rear" is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and their embodiments, and are not used to limit that the indicated devices, elements, or components must have a specific orientation, or be constructed and operated in a specific orientation. Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0032] In addition, the terms "arrangement", "connection", and "fixation" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0033] Unless otherwise specified, the term "plurality" means two or more.

[0034] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0035] The term "and / or" is an associative relationship describing an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, the three relationships of A and B.

[0036] It should be noted that, without conflict, the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0037] Combined Figure 3 As shown, the embodiments of the present disclosure provide a data output buffer, including a parasitic capacitance to ground 1, a buffer circuit 2, and a comparison circuit 3; one end of the parasitic capacitance to ground 1 is connected to the buffer circuit 2 and the comparison circuit 3, and the other end is grounded; the buffer circuit 2 is configured to receive the data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range; the comparison circuit 3 is configured to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground 1, compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result.

[0038] Using the data output buffer provided by the embodiments of the present disclosure, one end is connected to a buffer circuit and a comparison circuit through a parasitic capacitance to ground, and the other end is grounded; the buffer circuit is configured to receive the data to be output and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range; the comparison circuit is configured to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground; compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result. In this way, by adjusting the maximum capacitance voltage of the parasitic capacitance to ground to be within the first preset range and adjusting the minimum capacitance voltage of the parasitic capacitance to ground to be within the second preset range through the buffer circuit, the amplitude of the capacitance voltage of the parasitic capacitance to ground can be adjusted, thereby changing the current magnitude of the data output port of the data output buffer. By flexibly adjusting the current of the data output port of the data output buffer, the non-volatile memory chip using the data output buffer can operate stably.

[0039] In some embodiments, the data to be output is a level signal, and the level signal corresponds to a level voltage.

[0040] Combined Figure 4 As shown, optionally, the buffer circuit includes: a first PMOS transistor 204, the source of the first PMOS transistor 204 receives a first voltage, the gate of the first PMOS transistor 204 receives the data to be output, and the drain of the first PMOS transistor 204 is connected to the drain of a first NMOS transistor 205; the first NMOS transistor 205, the gate of the first NMOS transistor 205 receives a second voltage, and the source of the first NMOS transistor 205 is connected to the source of a second PMOS transistor 206 and a parasitic capacitance to ground 1; the second PMOS transistor 206, the gate of the second PMOS transistor 206 receives a third voltage, and the drain of the second PMOS transistor 206 is connected to the drain of a second NMOS transistor 207; the second NMOS transistor 207, the gate of the second NMOS transistor 207 receives the data to be output, and the source of the second NMOS transistor 207 is grounded. The gate of the first NMOS transistor 205 is connected to a first voltage supply port 202, and the first voltage supply port 202 is used to provide the second voltage; the gate of the second PMOS transistor 206 is connected to a second voltage supply port 203, and the second voltage supply port 203 is used to provide the third voltage. Optionally, the first voltage is a power supply voltage, and the gate of the first PMOS transistor 204 receives the data to be output through a data to be output input port 201; the gate of the second NMOS transistor 207 receives the data to be output through the data to be output input port 201.

[0041] In some embodiments, the comparison circuit is a voltage comparator 302. The first input terminal of the voltage comparator 302 is connected to the parasitic ground capacitance 1, the source of the first NMOS transistor 205, and the source of the second PMOS transistor 206; the second input terminal of the voltage comparator 302 is connected to the reference voltage output port 301; the output terminal of the voltage comparator 302 is connected to the to-be-output data output port 303. Optionally, the first input terminal of the voltage comparator is the positive input terminal, and the second input terminal of the voltage comparator is the negative input terminal. In this way, after the level signal switches from high level to low level, the first PMOS transistor is fully turned on, the second NMOS transistor is fully turned off, and the parasitic ground capacitance starts to gradually charge. When the second voltage minus the capacitance voltage of the parasitic ground capacitance is greater than the threshold voltage of the first NMOS transistor, the capacitance voltage of the parasitic ground capacitance increases rapidly. The difference between the second voltage minus the capacitance voltage and the threshold voltage of the first NMOS transistor is determined as the first voltage value. When the first voltage value is within the third preset range, the capacitance voltage of the parasitic ground capacitance is equal to the second voltage value, and the second voltage value is equal to the difference between the second voltage and the threshold voltage of the first NMOS transistor. After the level signal switches from low level to high level, the first PMOS transistor is fully turned off, the second NMOS transistor is fully turned on, and the parasitic ground capacitance starts to gradually discharge. When the capacitance voltage minus the third voltage is greater than the threshold voltage of the second PMOS transistor, the capacitance voltage of the parasitic ground capacitance decreases rapidly. The difference between the capacitance voltage of the parasitic ground capacitance minus the third voltage and the threshold voltage of the second PMOS transistor is determined as the third voltage value. When the third voltage value is within the fourth preset range, the capacitance voltage of the parasitic ground capacitance is equal to the fourth voltage value, and the fourth voltage value is equal to the sum of the third voltage and the threshold voltage of the second PMOS transistor. As Figure 5 shown, it is the voltage waveform of the capacitance voltage of the parasitic ground capacitance, and the amplitude of the voltage waveform is from the second voltage value to the fourth voltage value. Thus, the current value of the to-be-output data output port of the data output buffer is obtained by calculating I2 = N * C * (V1 - V2) / Trf. Wherein, I2 is the current value of the to-be-output data output port of the data output buffer; N is the data bus bit width; C is the capacitance value of the parasitic ground capacitance; V1 is the second voltage value; V2 is the fourth voltage value; Trf is the rise or fall time when the to-be-output data flips.

[0042] Combined with Figure 6As shown, optionally, the comparison circuit includes: a third PMOS transistor 304, the source of the third PMOS transistor 304 receives a first voltage; the gate of the third PMOS transistor 304 is connected to the gate of the fourth PMOS transistor 305; the drain of the third PMOS transistor 304 is connected to the drain of the third NMOS transistor 308; a fourth PMOS transistor 305, the source of the fourth PMOS transistor 305 receives the first voltage; the drain of the fourth PMOS transistor 305 is connected to the gate of the fourth PMOS transistor 305 and the drain of the fourth NMOS transistor 309; a fifth PMOS transistor 306, the source of the fifth PMOS transistor 306 receives the first voltage, the gate of the fifth PMOS transistor 306 is connected to the gate of the sixth PMOS transistor 307, and the drain of the fifth PMOS transistor 306 is connected to the gate of the fifth PMOS transistor 306 and the drain of the fifth NMOS transistor 310; a sixth PMOS transistor 307, the source of the sixth PMOS transistor 307 receives the first voltage, and the drain of the sixth PMOS transistor 307 is connected to the drain of the sixth NMOS transistor 311; a third NMOS transistor 308, the drain of the third NMOS transistor 308 is connected to the gate of the third NMOS transistor 308, the gate of the third NMOS transistor 308 is connected to the gate of the sixth NMOS transistor 311, and the source of the third NMOS transistor 308 is grounded; a current source 312, one end is connected to the sources of the fourth NMOS transistor 309 and the fifth NMOS transistor 310, and the other end is grounded; a fourth NMOS transistor 309, the gate of the fourth NMOS transistor 309 is connected to the parasitic capacitance to ground 1; a fifth NMOS transistor 310, the gate of the fifth NMOS transistor 310 receives a reference voltage; a sixth NMOS transistor 311, the source of the sixth NMOS transistor 311 is grounded. Optionally, the first voltage is the power supply voltage; the second voltage is the power supply voltage; the third voltage is 0 volts. The drain of the sixth PMOS transistor 307 and the drain of the sixth NMOS transistor 311 are connected to the output data output port 303. In this way, the reference voltage and the capacitance voltage can be compared, and the data to be output can be output according to the comparison result.

[0043] Optionally, the data output buffer further includes a reference voltage generation circuit, connected to the comparison circuit, for generating a reference voltage and outputting the reference voltage to the comparison circuit.

[0044] In some embodiments, the gate of the fifth NMOS transistor 310 receives a reference voltage generated by a reference voltage generation circuit. Optionally, the reference voltage generation circuit includes: a seventh NMOS transistor 401, the drain of the seventh NMOS transistor 401 receives a first voltage, the gate of the seventh NMOS transistor 401 is connected to the drain of the seventh NMOS transistor 401, and the source of the seventh NMOS transistor 401 is connected to the drain of an eighth NMOS transistor 402; an eighth NMOS transistor 402, the gate of the eighth NMOS transistor 402 is connected to the drain of the eighth NMOS transistor 402, and the source of the eighth NMOS transistor 402 is connected to the source of a seventh PMOS transistor 403 and the gate of the fifth NMOS transistor 310; a seventh PMOS transistor 403, the gate of the seventh PMOS transistor 403 is connected to the drain of the seventh PMOS transistor 403, and the drain of the seventh PMOS transistor 403 is connected to the source of an eighth PMOS transistor 404; an eighth PMOS transistor 404, the gate of the eighth PMOS transistor 404 is connected to the drain of the eighth PMOS transistor 404, and the drain of the eighth PMOS transistor 404 is grounded. In this way, the reference voltage generated by the reference voltage generation circuit can follow the threshold voltage of the first NMOS transistor and the threshold voltage of the second PMOS transistor. When the threshold voltage of the first NMOS transistor is equal to the threshold voltage of the second PMOS transistor, the voltage value of the reference voltage is equal to the voltage value of the first voltage divided by 2, that is, the reference voltage is equal to the capacitance voltage of the parasitic capacitance to the ground, so that the duty cycle of the waveform output by the reference voltage generation circuit can ideally approach 50%. When the threshold voltage of the second PMOS transistor is greater than the threshold voltage of the first NMOS transistor, the voltage value of the reference voltage is approximately equal to the capacitance voltage of the parasitic capacitance and is greater than the voltage value of the first voltage divided by 2; when the threshold voltage of the second PMOS transistor is less than the threshold voltage of the first NMOS transistor, the voltage value of the reference voltage is approximately equal to the capacitance voltage of the parasitic capacitance and is less than the voltage value of the first voltage divided by 2.

[0045] Optionally, the first preset range is used to represent the voltage range in which the level signal is at a high level;

[0046] Optionally, the second preset range is used to represent the voltage range in which the level signal is at a low level;

[0047] An embodiment of the present disclosure provides a non-volatile memory chip, including the above-mentioned data output buffer.

[0048] Using the non-volatile memory chip provided by the embodiments of the present disclosure, the non-volatile memory chip includes a data output buffer, which is connected to a buffer circuit and a comparison circuit at one end through a parasitic capacitance to ground, and grounded at the other end; the buffer circuit is configured to receive data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range; the comparison circuit is configured to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground, compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result. In this way, by adjusting the maximum capacitance voltage of the parasitic capacitance to ground to be within the first preset range and adjusting the minimum capacitance voltage of the parasitic capacitance to ground to be within the second preset range through the buffer circuit, the amplitude of the capacitance voltage of the parasitic capacitance to ground can be adjusted, thereby changing the current magnitude of the data output port of the data output buffer. By flexibly adjusting the current of the data output port of the data output buffer, the non-volatile memory chip using the data output buffer can operate stably.

[0049] Combined with Figure 7 As shown, optionally, the non-volatile memory chip further includes: a storage array 5 for storing data to be output; a row decoder 6 electrically connected to the storage array 5; a column selector 7 connecting the storage array 5 and the data output buffer 4 for outputting the data to be output to the data output buffer 4.

[0050] Optionally, the column selector 7 is electrically connected to the data output buffer through a sense amplifier 8.

[0051] Optionally, the non-volatile memory chip further includes: a shift register 9 electrically connected to the data output buffer 4 at one end and to the data output pin 10 at the other end.

[0052] The above description and the drawings fully illustrate the embodiments of the present disclosure, enabling those skilled in the art to practice them. Other embodiments may include structural and other changes. Embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Some parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A data output buffer, characterized in that, Including: A parasitic capacitance to ground, one end of which is connected to a buffer circuit and a comparison circuit, and the other end is grounded; The buffer circuit is configured to receive data to be output, and adjust the maximum capacitance voltage of the parasitic capacitance to ground to be within a first preset range and adjust the minimum capacitance voltage of the parasitic capacitance to ground to be within a second preset range according to the data to be output; The comparison circuit is configured to receive a reference voltage and the capacitance voltage of the parasitic capacitance to ground; Compare the reference voltage and the capacitance voltage, and output the data to be output according to the comparison result; The buffer circuit includes: a first PMOS transistor, the source of the first PMOS transistor receives a first voltage, the gate of the first PMOS transistor receives the data to be output, and the drain of the first PMOS transistor is connected to the drain of a first NMOS transistor; the first NMOS transistor, the gate of the first NMOS transistor receives a second voltage, the source of the first NMOS transistor is connected to the source of a second PMOS transistor and the parasitic capacitance to ground; the second PMOS transistor, the gate of the second PMOS transistor receives a third voltage, the drain of the second PMOS transistor is connected to the drain of a second NMOS transistor; the second NMOS transistor, the gate of the second NMOS transistor receives the data to be output, and the source of the second NMOS transistor is grounded.

2. The data output buffer according to claim 1, characterized in that The comparison circuit includes: A third PMOS transistor, the source of the third PMOS transistor receives a first voltage, the gate of the third PMOS transistor is connected to the gate of a fourth PMOS transistor, and the drain of the third PMOS transistor is connected to the drain of a third NMOS transistor; The fourth PMOS transistor, the source of the fourth PMOS transistor receives a first voltage, the drain of the fourth PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of a fourth NMOS transistor; A fifth PMOS transistor, the source of the fifth PMOS transistor receives a first voltage, the gate of the fifth PMOS transistor is connected to the gate of a sixth PMOS transistor, and the drain of the fifth PMOS transistor is connected to the gate of the fifth PMOS transistor and the drain of a fifth NMOS transistor; The sixth PMOS transistor, the source of the sixth PMOS transistor receives a first voltage, and the drain of the sixth PMOS transistor is connected to the drain of a sixth NMOS transistor; The third NMOS transistor, the drain of the third NMOS transistor is connected to the gate of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the sixth NMOS transistor, and the source of the third NMOS transistor is grounded; A current source, one end of which is connected to the sources of the fourth NMOS transistor and the fifth NMOS transistor, and the other end is grounded; The fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the parasitic capacitance to ground; The fifth NMOS transistor, the gate of the fifth NMOS transistor receives the reference voltage; The sixth NMOS transistor, the source of the sixth NMOS transistor is grounded.

3. The data output buffer according to claim 1, characterized in that, The first preset range is used to represent the voltage range in which the level signal is at a high level.

4. The data output buffer according to claim 1, characterized in that, The second preset range is used to represent the voltage range in which the level signal is at a low level.

5. The data output buffer according to claim 1, characterized in that Further including: A reference voltage generation circuit, connected to the comparison circuit, for generating a reference voltage and outputting the reference voltage to the comparison circuit.

6. A non-volatile memory chip, characterized in that, Including the data output buffer according to any one of claims 1 to 5.

7. The non-volatile memory chip according to claim 6, wherein Further comprising: a storage array for storing data to be output; A row decoder electrically connected to the storage array; A column selector connected to the storage array and the data output buffer for outputting the data to be output to the data output buffer.

8. The non-volatile memory chip according to claim 7, characterized in that, The column selector is electrically connected to the data output buffer through a sense amplifier.

9. The non-volatile memory chip according to claim 6, wherein, Further comprising: A shift register, one end of which is electrically connected to the data output buffer and the other end of which is electrically connected to a data output pin.

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