Semiconductor package structure and method of manufacturing the same

Abstract

The semiconductor package structure and the manufacturing method thereof provided by the present disclosure utilize the design of the organic material cover body in combination with the metal shielding layer, which can effectively reduce the density and volume of the cover body compared with the metal cover body, and is conducive to the miniaturization of the product structure. In addition, the first electronic component is covered by the barrier layer, which can block the ultrasonic waves emitted by the first electronic component to the substrate from being reflected to the first electronic component, thereby avoiding interference with the signal received by the first electronic component.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology

[0002] Piezoelectric ceramics are functional ceramic materials capable of converting mechanical energy and electrical energy into each other—the piezoelectric effect. In addition to piezoelectricity, piezoelectric ceramics also possess dielectric and elastic properties, and have been widely used in medical imaging, acoustic sensors, acoustic transducers, and ultrasonic motors. Piezoelectric ceramics are manufactured by utilizing the piezoelectric effect, where the relative displacement of positive and negative charge centers within the material under mechanical stress causes polarization, resulting in bound charges of opposite signs on the surfaces at both ends of the material. This gives them sensitive properties.

[0003] In some cases, the piezoelectric ceramic component packaging structure mainly consists of encapsulating the piezoelectric ceramic component with a metal cover, printed circuit board, and connector. The packaging design is limited by the size and shape of the metal cover, which not only hinders product miniaturization but also fails to effectively isolate the effects of vibration or packaging structure stress, thus failing to reduce ultrasonic frequency interference. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging structure, including:

[0006] substrate;

[0007] A cover body is disposed on the substrate;

[0008] A metal shielding layer and a first electronic component are disposed on the inner surface of the cover. The first electronic component is electrically connected to the metal shielding layer through a first electrical connector, and the metal shielding layer is electrically connected to the substrate through a second electrical connector.

[0009] A barrier layer covers the first electronic component.

[0010] In some alternative embodiments, the first electronic component is a piezoelectric component having two electrodes that are electrically connected to the metal shielding layer via a first electrical connector separated by a non-conductive layer.

[0011] In some alternative embodiments, the first electrical connector is a conductive adhesive, and the non-conductive layer is a non-conductive adhesive.

[0012] In some alternative embodiments, the second electrical connector is a conductive adhesive or a combination of conductive adhesive and a wire, and the second electrical connector is used to provide a vertical conductive path between the metal shielding layer and the substrate.

[0013] In some alternative implementations, it also includes:

[0014] An adhesive layer that bonds the substrate and the cover.

[0015] In some alternative implementations, the adhesive layer is a non-conductive adhesive.

[0016] In some alternative embodiments, the conductive and non-conductive adhesives have a low modulus of elasticity to prevent vibration interference from the piezoelectric component from being transmitted to the substrate.

[0017] In some alternative embodiments, the conductive adhesive has a low modulus of elasticity to prevent vibration interference from the piezoelectric component from being transmitted to the substrate.

[0018] In some alternative embodiments, the barrier layer is an elastomeric material, which is used to prevent ultrasonic waves emitted by the piezoelectric component to the substrate from being reflected back to the piezoelectric component.

[0019] In some alternative implementations, it also includes:

[0020] A second electronic component is disposed on the substrate, and the second electronic component is electrically connected to the first electronic component through the substrate and the first electrical connector.

[0021] In some alternative embodiments, the substrate has through holes to prevent the popcorn effect.

[0022] In some alternative implementations, it also includes:

[0023] An electromagnetic shielding layer is disposed on the outer surface of the cover.

[0024] In some alternative embodiments, the cover is made of an organic material.

[0025] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging structure, including:

[0026] A metallic shielding layer is formed on the inner surface of the cover.

[0027] A first electrical connector and a first electronic component are sequentially formed on the metal shielding layer, so that the first electronic component is electrically connected to the metal shielding layer through the first electrical connector;

[0028] A second electrical connector is formed, and the cover is disposed on the substrate so that the metal shielding layer is electrically connected to the substrate through the second electrical connector.

[0029] In some optional embodiments, after the first electrical connector and the first electronic component are sequentially formed on the metal shielding layer, the method further includes:

[0030] A barrier layer is formed to cover the first electronic component.

[0031] In some alternative embodiments, the first electronic component is a piezoelectric component having two electrodes that are electrically connected to the metal shielding layer via a first electrical connector separated by a non-conductive layer.

[0032] In some alternative embodiments, the first electrical connector is a conductive adhesive, and the non-conductive layer is a non-conductive adhesive.

[0033] In some alternative embodiments, the second electrical connector is a conductive adhesive or a combination of conductive adhesive and a wire, and the second electrical connector is used to provide a vertical conductive path between the metal shielding layer and the substrate.

[0034] In some alternative embodiments, before placing the cover onto the substrate, the method further includes:

[0035] An adhesive layer is provided on the substrate or the cover; and

[0036] The step of placing the cover on the substrate includes:

[0037] The cover is bonded to the substrate using the adhesive layer.

[0038] In some alternative embodiments, the adhesive layer is a non-conductive adhesive.

[0039] In some alternative embodiments, the conductive and non-conductive adhesives have a low modulus of elasticity to prevent vibration interference from the piezoelectric component from being transmitted to the substrate.

[0040] In some alternative implementations, it also includes:

[0041] An electromagnetic shielding layer is formed on the outer surface of the cover.

[0042] The semiconductor packaging structure and manufacturing method disclosed herein utilize an organic material cover combined with a metal shielding layer. Compared to a metal cover, this effectively reduces the density and volume of the cover, which is beneficial for product miniaturization. Furthermore, by using a barrier layer to encapsulate the first electronic component, ultrasonic waves emitted by the first electronic component to the substrate can be prevented from reflecting back to the first electronic component, thereby avoiding interference with the signals received by the first electronic component. Attached Figure Description

[0043] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0044] Figure 1 This is a first structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0045] Figure 2 This is a second structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;

[0046] Figures 3 to 11 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0047] Symbol explanation:

[0048] 1-Substrate, 101-Through hole, 2-Cover, 3-Metal shielding layer, 4-First electronic component, 41-Electrode, 5-First electrical connector, 6-Second electrical connector, 61-Conductive adhesive, 62-Wire, 7-Barrier layer, 8-Non-conductive layer, 9-Second electronic component, 10-Adhesive layer, 11-Electromagnetic shielding layer, 12-First carrier, 13-Second carrier. Detailed Implementation

[0049] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0050] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0051] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0052] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0053] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Figure 1 This is a first structural schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor package structure includes a substrate 1, a cover 2, a metal shielding layer 3, a first electronic component 4, and a barrier layer 7. The cover 2 is disposed on the substrate 1. The metal shielding layer 3 and the first electronic component 4 are disposed on the inner surface of the cover 2. The first electronic component 4 is electrically connected to the metal shielding layer 3 via a first electrical connector 5. The metal shielding layer 3 is electrically connected to the substrate 1 via a second electrical connector 6.

[0055] In this embodiment, the metal shielding layer 3 can be a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof. The metal shielding layer 3 can be used not only to provide an electrical connection path between the first electronic component 4 and the substrate 1, but also for electromagnetic shielding.

[0056] In one embodiment, the cover 2 can be an organic material, such as ABF resin, BT (Bismaleimide Triazine) resin, glass cloth-based epoxy resin (FR4, FR5), PI resin, liquid crystal polymer resin (LCP), or epoxy resin. This allows the use of an organic material cover 2 in conjunction with a metal shielding layer 3, replacing the metal cover 2, effectively reducing the density and volume of the cover 2. Furthermore, it avoids the limitations imposed by the size and shape design of the metal cover 2, facilitating miniaturization.

[0057] In this embodiment, the first electronic component 4 can be an active component or a passive component. Active components can be, for example, various chips (application-specific integrated circuit chips, high-bandwidth memory chips, power management chips, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips). Passive components can be, for example, capacitors, resistors, inductors, etc.

[0058] In one embodiment, the first electronic component 4 may be a piezoelectric component. The piezoelectric component may have two electrodes 41. The piezoelectric component can be used for transmitting and receiving ultrasonic and infrasonic signals. The ultrasonic signal emitted by the piezoelectric component can penetrate the cover 2, be reflected after encountering an obstacle, and then be received by the piezoelectric component. Obstacle information can then be calculated based on the reflected signal, thus making it suitable for obstacle detection scenarios in space.

[0059] In this embodiment, the barrier layer 7 can be a damping material, which can be used for vibration and noise control. In another embodiment, the barrier layer 7 can be an elastomeric material, such as rubber or silicone. The barrier layer 7 can have vibration absorption properties to prevent ultrasound waves emitted by the piezoelectric component from being reflected back to the piezoelectric component. This reduces the impact of ultrasound waves emitted downwards by the piezoelectric component on the substrate 1, thereby avoiding interference with the signals received by the piezoelectric component.

[0060] In one embodiment, the two electrodes 41 of the piezoelectric component can be electrically connected to the metal shielding layer 3 via a first electrical connector 5. The first electrical connector 5 can be a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a microbump. In another embodiment, the first electrical connector 5 can be a conductive adhesive, which can have a metallic conductive material such as silver powder. The conductive adhesive on the two electrodes 41 can be separated by a non-conductive layer 8. The non-conductive layer 8 can be a non-conductive adhesive. Here, the conductive adhesive can not only serve as an electrical connection path between the first electronic component 4 and the metal shielding layer 3, but also allow the first electronic component 4 to be bonded and fixed to the inner surface of the cover 2. The non-conductive adhesive can not only be used to electrically isolate the first electrical connector 5, but also allow the first electronic component 4 to be bonded and fixed to the surface of the cover 2.

[0061] In one embodiment, substrate 1 may have a through hole 101. The through hole 101 can be used to avoid the popcorn effect and prevent cracks from appearing inside substrate 1.

[0062] In one embodiment, the semiconductor package structure may further include an electromagnetic shielding layer 11. The electromagnetic shielding layer 11 may be disposed on the outer surface of the cover 2.

[0063] In one embodiment, the semiconductor package structure may further include a second electronic component 9. The second electronic component 9 may be disposed on the substrate 1. The second electronic component 9 may be electrically connected to the first electronic component 4 through the substrate 1, the first electrical connector 5, the metal shielding layer 3, and the first electrical connector 5. The second electronic component 9 may be an active component or a passive component.

[0064] In this embodiment, the second electrical connector 6 can be used to provide a vertical conductive path between the metal shielding layer 3 and the substrate 1. The second electrical connector 6 can be a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a microbump. In one embodiment, such as... Figure 1 As shown, the second electrical connector 6 can be a conductive adhesive. The conductive adhesive can have a low modulus of elasticity, acting as a buffer to absorb vibration and stress, preventing vibration interference from the piezoelectric component from being transmitted to the substrate 1. This can improve the impact of vibration on the semiconductor packaging structure, reduce the impact of packaging stress, thereby avoiding ultrasonic interference and increasing ultrasonic sensing characteristics and signal quality. In yet another embodiment, as... Figure 2As shown, the second electrical connector 6 can be a combination of conductive adhesive 61 and wire 62. Specifically, the metal shielding layer 3 and the substrate 1 can be electrically connected by a vertical wire 62 and a small amount of conductive adhesive 61. Since the diameter of the vertical wire 62 can be selected and its size is small, the contact area with the substrate 1 is small, thereby minimizing the impact of vibration.

[0065] In one embodiment, the semiconductor package structure may further include an adhesive layer 10. The adhesive layer 10 can bond the substrate 1 and the cover 2 to achieve a seal for the overall structure. In yet another embodiment, the adhesive layer 10 may be made of a non-conductive adhesive. The non-conductive adhesive may have a low modulus of elasticity, acting as a buffer to absorb vibration and stress, preventing vibration interference from the piezoelectric component from being transmitted to the substrate 1. This can improve the semiconductor package structure's susceptibility to vibration, reduce the impact of packaging stress, thereby avoiding ultrasonic interference and increasing ultrasonic sensing characteristics and signal quality.

[0066] The semiconductor packaging structure disclosed herein utilizes an organic material cover 2 combined with a metal shielding layer 3. Compared to a metal cover, this effectively reduces the density and volume of the cover, which is beneficial for product miniaturization. Furthermore, by using a barrier layer 7 to cover the first electronic component 4, ultrasonic waves emitted by the first electronic component 4 to the substrate 1 can be prevented from reflecting back to the first electronic component 4, thereby avoiding interference with the signals received by the first electronic component 4.

[0067] Figures 3 to 11 This is a schematic diagram of the manufacturing process of a semiconductor packaging structure according to an embodiment of the present disclosure.

[0068] like Figure 3 As shown, the cover 2 is first placed on the first carrier 12, and then a metal shielding layer 3 is formed on the inner surface of the cover 2. In one embodiment, an electromagnetic shielding layer 11 can also be formed on the outer surface of the cover 2. For example, the metal shielding layer 3 and the electromagnetic shielding layer 11 can be formed by processes such as electroplating.

[0069] like Figure 4 As shown, a first electrical connector 5 is formed on the metal shielding layer 3.

[0070] like Figure 5As shown, the first electronic component 4 is placed on the first electrical connector 5 so that the first electronic component 4 is electrically connected to the metal shielding layer 3 through the first electrical connector 5. In one embodiment, the first electronic component 4 can be a piezoelectric component. The piezoelectric component can have two electrodes 41. The two electrodes 41 can be electrically connected to the metal shielding layer 3 through the first electrical connector 5. A non-conductive layer 8 can be formed between the first electrical connectors 5 on the two electrodes 41 to separate them. In another embodiment, the non-conductive layer 8 can be a non-conductive adhesive. In yet another embodiment, the first electrical connector 5 can be a conductive adhesive, which can not only serve as an electrical connection path between the first electronic component 4 and the metal shielding layer 3, but also fix the first electronic component 4 inside the cover 2, and can also be used for electromagnetic shielding.

[0071] like Figure 6 As shown, a barrier layer 7 is formed to cover the first electronic component 4.

[0072] like Figure 7 As shown, substrate 1 is placed on second carrier 13. Second electronic component 9 is placed on substrate 1. Adhesive layer 10 and second electrical connector 6 (conductive adhesive) are formed on substrate 1. Alternatively, adhesive layer 10 can be formed on cover 2. Second electrical connector 6 (conductive adhesive) is formed on metal shielding layer 3. In one embodiment, through hole 101 can also be formed on substrate 1.

[0073] like Figure 8 As shown, the cover 2 is disposed on the substrate 1, and the cover 2 is bonded to the substrate 1 using the adhesive layer 10. The metal shielding layer 3 can be electrically connected to the substrate 1 through the second electrical connector 6 (conductive adhesive). A semiconductor packaging structure is obtained.

[0074] like Figure 9 As shown, an adhesive layer 10 is formed on the cover 2. A conductive adhesive 61 is formed on the metal shielding layer 3. In one embodiment, the adhesive layer 10 may be a non-conductive adhesive. In yet another embodiment, the conductive adhesive 61 and the non-conductive adhesive have low moduli of elasticity to prevent vibration interference from the piezoelectric component from being transmitted to the substrate 1.

[0075] like Figure 10 As shown, substrate 1 is placed on second carrier 13. Second electronic component 9 is placed on substrate 1. Wire 62 is attached to substrate 1. In one embodiment, through-hole 101 may also be formed on substrate 1.

[0076] like Figure 11 As shown, a cover 2 is disposed on a substrate 1, and the cover 2 is bonded to the substrate 1 using an adhesive layer 10. A wire 62 is connected to a conductive adhesive 61 to form a second electrical connector 6. The metal shielding layer 3 can be electrically connected to the substrate 1 through the second electrical connector 6, thus obtaining a semiconductor packaging structure.

[0077] The method for manufacturing the semiconductor packaging structure in this embodiment can achieve similar technical effects to the aforementioned semiconductor structure, and will not be described in detail here. Furthermore, utilizing basic packaging processes (such as dispensing, wire bonding, and die bonding) to standardize and automate the packaging process of piezoelectric components helps reduce production costs.

[0078] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor package structure, comprising: substrate; A cover body is disposed on the substrate, wherein the cover body is made of organic material to reduce the density and volume of the cover body; A metal shielding layer and a first electronic component are disposed on the inner surface of the cover. The first electronic component is electrically connected to the metal shielding layer through a first electrical connector, and the metal shielding layer is electrically connected to the substrate through a second electrical connector. The first electronic component is a piezoelectric component used for transmitting and receiving ultrasonic and infrasonic signals. A barrier layer covers the first electronic component, wherein the barrier layer is an elastomeric material, and the barrier layer is used to prevent the ultrasonic waves emitted by the piezoelectric component to the substrate from being reflected back to the piezoelectric component.

2. The semiconductor packaging structure according to claim 1, wherein, The piezoelectric component has two electrodes, which are electrically connected to the metal shielding layer via a first electrical connector, which is separated by a non-conductive layer.

3. The semiconductor packaging structure according to claim 2, wherein, The first electrical connector is a conductive adhesive, and the non-conductive layer is a non-conductive adhesive.

4. The semiconductor packaging structure according to claim 2, wherein, The second electrical connector is a conductive adhesive or a combination of conductive adhesive and a wire, and the second electrical connector is used to provide a vertical conductive path between the metal shielding layer and the substrate.

5. The semiconductor packaging structure according to claim 4, further comprising: An adhesive layer that bonds the substrate and the cover.

6. The semiconductor packaging structure according to claim 5, wherein, The adhesive layer is a non-conductive adhesive. Both the conductive and non-conductive adhesives have low elastic moduli to prevent vibration interference from the piezoelectric component from being transmitted to the substrate.

7. The semiconductor packaging structure according to claim 1, further comprising: A second electronic component is disposed on the substrate, and the second electronic component is electrically connected to the first electronic component through the substrate and the first electrical connector.

8. The semiconductor packaging structure according to claim 1, wherein, The substrate has through holes to prevent the popcorn effect.

9. The semiconductor packaging structure according to claim 1, further comprising: An electromagnetic shielding layer is disposed on the outer surface of the cover.

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