Display panel and manufacturing method thereof

Abstract

The application discloses a display panel and a manufacturing method thereof, and relates to the technical field of display. The display panel provided by the application mainly improves the position of a driving power supply wire in the display panel. In the technical scheme provided by the application, the display panel comprises a substrate, a thin film transistor layer and a first metal layer. The first metal layer is arranged on the thin film transistor layer, and the first metal layer at least comprises a driving power supply wire layer arranged in a non-display area of the display panel. The technical scheme provided by the application mainly arranges the wire layer on the side of the thin film transistor layer away from the substrate, avoids forming a deep hole through the thin film transistor layer on the thin film transistor layer, and reduces the risk of overlap abnormality of the driving power supply wire layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a manufacturing method thereof. BACKGROUND

[0002] Organic light emitting diode (OLED) has been widely applied in the fields of display, lighting and smart wear due to its advantages of self-luminous, high contrast and fast response.

[0003] The organic light emitting display panel generally comprises a substrate, a thin film transistor layer and an organic light emitting layer disposed on the thin film transistor. In the related technical solution, the power driving wire in the display panel is disposed on the substrate. In some cases, a deep hole penetrating through the thin film transistor layer is needed to be disposed on the thin film transistor layer to realize the connection between the driving power wire and other lines. The driving power wire is prone to have abnormal lap joint due to the deep hole, thereby affecting the display effect. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a display panel and a manufacturing method thereof, which can reduce the risk of abnormality of the driving power wire layer.

[0005] To solve the above technical problem, the technical means adopted by the present application is as follows:

[0006] In a first aspect, the present application provides a display panel, comprising:

[0007] a substrate;

[0008] a thin film transistor layer disposed on the substrate;

[0009] a first metal layer disposed on a side of the thin film transistor layer away from the substrate, and the first metal layer at least comprises a driving power wire layer disposed in a corresponding wire area of the display panel.

[0010] Optionally, in some embodiments of the present application, the driving power wire layer comprises a positive driving wire for connecting a positive voltage and a negative driving wire for connecting a negative voltage.

[0011] Optionally, in some embodiments of the present application, the first metal layer further comprises a source-drain layer constituting a source-drain electrode of a thin film transistor in the thin film transistor layer, and the display panel further comprises an organic light-emitting layer disposed on the thin film transistor layer, the organic light-emitting layer comprising an anode layer, a cathode layer and an organic layer disposed between the anode layer and the cathode layer, the positive driving wire being directly electrically connected to the anode layer through a first bonding wire, and / or the negative driving wire being directly electrically connected to the cathode layer through a second bonding wire.

[0012] Optionally, in some embodiments of the present application, the organic light-emitting layer comprises an insulating layer disposed on the thin film transistor layer and a pixel definition layer disposed on the insulating layer, the pixel definition layer defining a pixel opening, and the anode layer being disposed in the pixel opening.

[0013] Optionally, in some embodiments of the present application, the insulating layer is provided with a first via hole, the first bonding wire comprises a first bonding portion disposed on the insulating layer and in the same layer as the anode layer, and a second bonding portion disposed in the first via hole, the first bonding portion being directly electrically connected to the anode layer, and the first bonding portion being directly electrically connected to the positive driving wire through the second bonding portion.

[0014] Optionally, in some embodiments of the present application, the insulating layer is provided with a second via hole, the second bonding wire comprises a third bonding portion disposed on the insulating layer and in the same layer as the cathode layer, and a fourth bonding portion disposed in the second via hole, the third bonding portion being directly electrically connected to the cathode layer, and the third bonding portion being directly electrically connected to the negative driving wire through the fourth bonding portion.

[0015] Optionally, in some embodiments of the present application, the first metal layer further comprises a binding metal layer located in a binding area of the display panel, and at least one protective metal layer is sequentially disposed on the binding metal layer.

[0016] In a second aspect, the present application provides a display panel manufacturing method, comprising:

[0017] providing a substrate, the substrate being provided with a thin film transistor layer;

[0018] disposing a first metal layer on the thin film transistor layer, the first metal layer comprising at least a driving power wire layer disposed in a wire area of the display panel.

[0019] Optionally, in some embodiments of the present application, the driving power supply wire layer includes a forward driving wire for connecting a forward voltage and a negative driving wire for connecting a negative voltage, and the first metal layer further includes a source-drain layer for constituting a source-drain electrode of a thin film transistor in the thin film transistor layer, wherein after the first metal layer is arranged on the thin film transistor layer, the following steps are further included:

[0020] arranging an insulating layer on the thin film transistor layer, and forming a via hole in the insulating layer to expose the source-drain layer, the forward driving wire and the negative driving wire;

[0021] arranging a second metal layer on the thin film transistor layer, the second metal layer including a lapping electrode lapping on the source-drain layer through the via hole, a first lapping part lapping with the forward driving wire through the via hole, and a third lapping part lapping with the negative driving wire through the via hole;

[0022] arranging a third metal layer on the thin film transistor layer, the third metal layer including an anode layer covering the lapping electrode, a second lapping part covering the first lapping part, and a fourth lapping part covering the third lapping part.

[0023] Optionally, in some embodiments of the present application, the first metal layer further includes a binding metal layer located in a binding area of the display panel, and the second metal layer includes a first protective metal layer covering the binding metal layer.

[0024] In summary, by adopting the technical solutions described above, the technical solutions provided by the present application have at least the following beneficial effects:

[0025] The display panel provided by the present application mainly improves the position of the driving power supply wire in the display panel. In the technical solutions provided by the present application, the display panel includes a substrate, a thin film transistor layer and a first metal layer, the first metal layer is arranged on the thin film transistor layer and at least includes a driving power supply wire layer arranged in a wire area of the display panel. The technical solutions provided by the present application mainly arrange the wire layer on the side of the thin film transistor layer away from the substrate, avoid forming a deep hole through the thin film transistor layer on the thin film transistor layer, and reduce the risk of abnormal lapping of the driving power supply wire layer. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following briefly introduces the drawings needed in the embodiments. The drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.

[0027] Figure 1 A schematic diagram of setting a first metal layer on a thin film transistor layer in the embodiment 1 provided by the present application;

[0028] Figure 2 A schematic diagram of setting an insulating layer on a thin film transistor layer in the embodiment 1 provided by the present application;

[0029] Figure 3 A schematic diagram of setting a second metal layer after setting a via hole on the insulating layer in the embodiment 1 provided by the present application;

[0030] Figure 4 A schematic diagram of the overlap of a positive driving wire and a first overlap line in the embodiment 1 provided by the present application;

[0031] Figure 5 A schematic diagram of the overlap of a negative driving wire and a second overlap line in the embodiment 1 provided by the present application;

[0032] Figure 6 A schematic diagram of the position of a first overlap line and a pixel definition layer in the embodiment 1 provided by the present application;

[0033] Figure 7 A schematic diagram of the position of a second overlap line and a pixel definition layer in the embodiment 1 provided by the present application.

[0034] Explanation of reference signs:

[0035] 1-substrate, 2-thin film transistor layer, 21-buffer layer, 22-dielectric layer, 31-source-drain layer, 32-driving power wire layer, 32a-positive driving wire, 32b-negative driving wire, 4-anode layer, 41-overlap electrode, 51-first overlap line, 51a-first overlap part, 51b-second overlap part, 52-second overlap line, 52a-third overlap part, 52b-fourth overlap part, 6-insulating layer, 61-first via hole, 62-second via hole, 63-third via hole, 6a-passivation layer, 6b-planarization layer, 7-pixel definition layer, 81-bonding metal layer, 82-first protection metal layer. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0037] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a unique orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the words "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or indicating the number of the technical features referred to. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0038] In the application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation described as exemplary in this application is not necessarily to be construed as preferred or advantageous over other implementations. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, for purposes of explanation, specific details are set forth. It will be apparent to those skilled in the art that the present application can be practiced without using these specific details. In other instances, well-known structures and processes are not described in detail in order to avoid obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0039] Embodiment 1

[0040] The main body of the present embodiment is a display panel. Here, the display panel can be a display panel that is independent, or a display panel that is part of a display device such as a tablet, a mobile phone, a VR device, and the like.

[0041] Please refer to Figure 3 In the technical solution provided in the present embodiment, the display panel comprises:

[0042] a substrate 1;

[0043] a thin film transistor layer 2, the thin film transistor layer 2 being disposed on the substrate 1;

[0044] a first metal layer, the first metal layer being disposed on a side of the thin film transistor layer 2 opposite to the substrate 1, and the first metal layer at least comprising a driving power supply wire layer 32 disposed in a wire area part of the display panel.

[0045] The technical scheme provided by the embodiment is mainly to arrange the driving power supply wiring layer 32 on the side of the thin film transistor layer 2 away from the substrate 1, compared with the technical scheme in the prior art in which the driving power supply wiring layer 32 is directly arranged on the substrate 1, the display panel provided by the embodiment can avoid forming a deep hole through the thin film transistor layer 2 on the thin film transistor layer 2, thereby reducing the risk of overlap abnormality of the driving power supply wiring layer 32 due to the deep hole.

[0046] Here, the substrate 1 mainly constitutes a substrate in the display panel, which can be a rigid substrate such as a glass substrate, a quartz substrate, etc., or a flexible substrate such as a plastic substrate, and the thin film transistor layer 2 refers to a film layer structure including a thin film transistor, which can include a buffer layer 21 and a dielectric layer 22 arranged in sequence on the substrate 1 as shown in the embodiment. In addition, please refer to Figure 6 and Figure 7 In the embodiment, the display panel is an organic light-emitting display panel, which further includes an organic light-emitting layer in addition to the substrate 1 and the thin film transistor layer 2 as described above, and the organic light-emitting layer includes an anode layer 4, an organic layer (not shown), a cathode layer (not shown), a passivation layer 6a, a planarization layer 6b, a pixel definition layer 7, etc. The organic layer emits light by carrier injection and recombination under the driving of the electric field formed by the anode layer 4 and the cathode layer. Some contents related to the structure of the organic light-emitting layer have been disclosed in the prior art, so the present application will not be repeated here.

[0047] In addition, the driving power supply wiring layer 32 generally includes a positive driving wiring 32a for providing a positive voltage and a negative driving wiring 32b for providing a negative voltage, the positive driving wiring 32a is electrically connected to the signal lines corresponding to the array display area and arranged in an interlaced mesh on the display panel, thereby providing a voltage for the pixels, and the negative driving wiring 32b is electrically connected to the cathode layer in the display panel to provide a potential difference required by the cathode layer and lead current into the cathode.

[0048] It should be noted that, Figure 3 The driving power supply wiring layer 32 shown in the above embodiment can include both the positive driving wiring 32a and the negative driving wiring 32b, or only one of them, but for the above scheme, as long as the driving power supply wiring layer 32 is arranged on the side of the thin film transistor layer 2 away from the substrate 1, a deep hole through the thin film transistor can be avoided on the thin film transistor layer 2, thereby improving the overlap effect of the driving power supply wiring layer 32.

[0049] Please refer to Figure 3 and in combination with Figure 4 and Figure 5 For the convenience of understanding and display,Figure 4 The negative drive trace 32b was omitted in the middle. Figure 5 The positive drive trace 32a is omitted in this embodiment. In this embodiment, the aforementioned drive power trace layer 32 includes both a positive drive trace 32a for connecting to a positive voltage and a negative drive trace 32b for connecting to a negative voltage. The film thickness of the positive drive trace 32a and the negative drive trace 32b affects subsequent processes. Ideally, the film thickness of the positive drive trace 32a and the negative drive trace 32b should be set to a relatively small value, for example... The following is an explanation. However, it is understandable that for the above-mentioned power supply trace layer 32, while its own film thickness is reduced, its own impedance will also increase, which will affect the display effect of the display panel.

[0050] Therefore, please see Figure 4 In this embodiment, the forward drive trace 32a is directly electrically connected to the anode layer 4 via the first bonding wire 51. (For ease of demonstration...) Figure 4 Only a portion of the first connection line 51 is schematically shown, while the negative drive line 32b is omitted.

[0051] Please also see Figure 5 The negative drive trace 32b is directly electrically connected to the cathode layer via the second bonding wire 52. (For ease of demonstration) Figure 5 Only a portion of the second connection wire 52 is schematically shown, while the forward drive wiring 32a is omitted.

[0052] In this embodiment, the forward driving line 32a provides a positive voltage to the thin-film transistors in the thin-film transistor layer 2 and is also directly connected to the anode layer 4 via the first bonding wire 51, thus forming a parallel structure. This reduces the impedance of the forward driving line 32a and improves the display effect of the display panel. Similarly, the negative driving line 32b provides a potential difference to the cathode layer and guides the current in the cathode layer to the cathode. It is also directly connected to the cathode layer via the second bonding wire 52, forming a parallel structure between the cathode layer and the negative driving line 32b, thereby reducing the impedance of the negative driving line 32b and improving the display effect of the display panel. With the above configuration, the forward driving line 32a and the negative driving line 32b can have a relatively thin film thickness.

[0053] For more specific details, please refer to... Figure 6 and Figure 7In this embodiment, the organic light-emitting layer includes an insulating layer 6 disposed on the thin-film transistor layer 2 and a pixel definition layer 7 disposed on the insulating layer 6. The pixel definition layer 7 defines a pixel opening, and the anode layer 4 is disposed in the pixel opening. It should be noted that the insulating layer 6 may include a passivation layer 6a and a planarization layer 6b as shown in this embodiment, or it may include multiple planarization layers 6b. Implementers can choose the appropriate layer according to their own needs.

[0054] Please see Figure 4 A schematic diagram of the structure of the first bonding wire 51 is shown below. In this embodiment, a first via 61 is provided on the insulating layer 6. The first bonding wire 51 includes a first bonding portion 51a disposed on the insulating layer 6 and disposed in the same layer as the anode layer 4, and a second bonding portion 51b disposed within the first via 61. The first bonding portion 51a is directly electrically connected to the anode layer 4, and the first bonding portion 51a is directly electrically connected to the forward driving trace 32a through the second bonding portion 51b. To reduce charging and discharging delay time for high-resolution OLED driving displays, the materials used for the forward driving trace 32a, the negative driving trace 32b, and the source / drain layer 31 are generally selected from one or a combination of Al and its alloys, Cu and its alloys, Ti and its alloys, and MoTi and its alloys. The material of the anode layer 4 is generally selected from Al, Ag, ITO, IZO, IGZO, or a combination thereof. If the first lap wire 51 consists only of the first lap portion 51a disposed on the same layer as the anode layer 4, corrosion is likely to occur between the anode layer 4 and the forward drive trace 32a. Therefore, in this embodiment, the first lap wire 51 is configured to have a first lap portion 51a disposed on the same layer as the anode layer 4, and a second lap portion 51b disposed within the first via 61. This allows implementers to flexibly choose the material of the second lap portion 51b to achieve an indirect connection and avoid corrosion between the anode layer 4 and the forward drive trace 32a. The second lap portion 51b can be made of a high-temperature and high-humidity resistant oxide material, such as MoTi or MoTi alloy, transparent oxide, Cu, or a combination thereof.

[0055] It should also be noted here that, Figure 4 , Figure 6 Only a portion of the first bonding wire 51 is shown in the figure. Those skilled in the art will understand that the first bonding wire 51 may have a portion extending through the pixel definition layer 7 toward the anode layer 4, so that the anode layer 4 and the first bonding wire 51 are directly electrically connected.

[0056] Similarly, please see Figure 5The schematic diagram of the second bonding wire 52 shows that, in this embodiment, a second via 62 is provided on the insulating layer 6. The second bonding wire 52 includes a third bonding portion 52a disposed on the insulating layer 6 and at the same layer as the anode layer 4, and a fourth bonding portion 52b disposed within the second via 62. The third bonding portion 52a is directly electrically connected to the cathode layer, and the third bonding portion 52a is directly electrically connected to the negative drive trace 32b through the fourth bonding portion 52b. The principle is similar to that described above; by setting the second bonding wire 52 into different parts, the material of each part can be flexibly set, thereby avoiding corrosion between the electrode layer and the negative drive trace 32b. It should also be noted that... Figure 5 and Figure 7 Only a portion of the second bonding wire 52 is shown in the image. The second bonding wire 52 can be directly electrically connected to the cathode layer through a via in the pixel definition layer 7.

[0057] It should be noted that, since they are formed on the insulating layer 6, the depths of the first via 61 and the second via 62 can be configured to be relatively shallow, for example... In addition, in this embodiment, the portions of the first bonding wire 51 and the second bonding wire 52 that extend out of the insulating layer 6 are separated from each other and are covered by the pixel definition layer 7.

[0058] Please see Figure 3 In this embodiment, the first metal layer further includes a bonding metal layer 81 located in the corresponding bonding area of ​​the display panel. As described above, after patterning, the first metal layer forms a source / drain layer 31 and a driving power trace layer 32. The source / drain layer 31 and the driving power trace layer 32 are generally made of materials that are not resistant to high temperature and high humidity, which can cause the bonding pads formed by the bonding metal layer 81 to corrode in subsequent processes. Correspondingly, in this embodiment, at least one protective metal layer is sequentially covered on the bonding metal layer 81. Specifically, the protective metal layer includes a first protective metal layer 82 sequentially covered on the bonding metal layer 81 to protect the bonding metal layer 81, and they are electrically connected to each other to form bonding pads.

[0059] It should be noted that the number of protective metal layers is not limited to the single layer shown in this embodiment, and can be multiple layers. For example, in another embodiment, the protective metal layers include a first protective metal layer 82 and a second protective metal layer sequentially covering the bonding metal layer 81. The first protective metal layer 82 is formed by patterning the second metal layer. After patterning, the second metal layer also forms a second overlap portion 51b of the first overlap line 51 and a fourth overlap portion 52b of the second overlap line 52. The second protective metal layer is formed by patterning the third metal layer. After patterning, the third metal layer also forms a first overlap portion 51a of the first overlap line 51 and a third overlap portion 52a of the second overlap line 52.

[0060] In addition, in this embodiment, a third via 63 is formed on the insulating layer 6, which exposes the source and drain layers 31. At the same time, after patterning, the second metal layer forms a lap electrode 41 located in the third via 63, and after patterning, the third metal layer forms an anode layer 4 covering the lap electrode 41.

[0061] The following is a brief introduction to the manufacturing method of the display panel provided in this embodiment.

[0062] A method for manufacturing a display panel includes:

[0063] S1. A substrate 1 is provided, on which a thin film transistor layer is disposed;

[0064] S2. A first metal layer is disposed on the thin-film transistor layer, the first metal layer including at least a driving power trace layer 32 disposed in the corresponding trace area of ​​the display panel.

[0065] Please see Figure 1 The manufacturing method provided in this embodiment, compared with the traditional method, directly places the driving power trace layer 32 on the substrate 1 through step S2, avoiding the formation of deep holes through the thin film transistor layer 2, thereby reducing the risk of abnormal overlap of the driving power trace layer 32 due to deep holes.

[0066] For more details, please see Figures 2 to 6 In step S1, the first metal layer further includes a bonding metal layer 81 located in the corresponding bonding area of ​​the display panel. After the first metal layer is deposited on the thin-film transistor layer, the following steps are also included:

[0067] S3. An insulating layer 6 is provided on the thin film transistor layer 2, and a via is formed on the insulating layer 6 to expose the source and drain layers 31, the positive drive line 32a and the negative drive line 32b.

[0068] S4. A second metal layer is disposed on the thin film transistor layer 2. The second metal layer includes a bonding electrode 41 that is bonded to the source and drain layer 31 through a via, a first bonding portion 51a that is bonded to the positive drive line 32a, and a third bonding portion 52a that is bonded to the negative drive line 32b. The second metal layer also includes a first protective metal layer 82 that covers the bonding metal layer 81.

[0069] S5. A third metal layer is disposed on the thin film transistor layer 2. The third metal layer includes an anode layer 4 covering the lap electrode 41, a second lap portion 51b covering the first lap portion 51a, and a fourth lap portion 52b covering the third lap portion 52a.

[0070] As described above, since the via is formed on insulating layer 6, the depth of the via can be configured to be relatively shallow, for example... Simultaneously, it is understood that since they are formed by patterning the same metal layer, the source / drain layer 31, the drive power trace layer 32, and the bonding metal layer 81 formed by patterning the first metal layer are made of the same material. The first metal layer can be selected from one or a combination of Al and its alloys, Cu and its alloys, Ti and its alloys, and MoTi and its alloys. The overlapping electrode 41, the first overlapping portion 51a, the third overlapping portion 52a, and the first protective metal layer 82 formed by patterning the second metal layer are made of the same material, which can be made of a high-temperature and high-humidity resistant oxide material, such as MoTi or MoTi alloys, transparent oxides, and Cu, or a combination thereof. The anode layer 4, the second overlapping portion 51b, and the fourth overlapping portion 52b formed by patterning the third metal layer have the same material, which can be selected from Al, Ag, ITO, IZO, IGZO, or a combination thereof. In addition, the film thickness of the above-mentioned first metal layer can be selected from... to Meanwhile, the resistivity of the second metal layer can be configured to be less than that of the first metal layer.

[0071] In addition, as described above, the first overlap 51a is directly electrically connected to the anode layer 4, while the third overlap 52b is used to directly connect to the cathode layer in the subsequent process, thereby forming a parallel structure and reducing the impedance of the positive drive trace 32a and the negative drive trace 32b.

[0072] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0073] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0074] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0075] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such numerical values ​​are set as precisely as feasible.

[0076] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this application, the entire contents of that patent application are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or subsequently appended to this application). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terminology used in the supplementary materials of this application and the content of this application, the descriptions, definitions, and / or terminology used in this application shall prevail.

Claims

1. A display panel, characterized in that, include: Substrate; A thin-film transistor layer, wherein the thin-film transistor layer is disposed on the substrate; A first metal layer is disposed on the side of the thin film transistor layer facing away from the substrate, and the first metal layer includes at least a driving power trace layer disposed in the corresponding trace area of ​​the display panel, the driving power trace layer including a negative driving trace for connecting a negative voltage. An insulating layer is disposed on the side of the thin-film transistor layer away from the substrate. An anode layer is disposed on the thin-film transistor layer; A cathode layer is disposed on the anode layer, and the negative drive trace is directly electrically connected to the cathode layer through a second bonding wire; The insulating layer is provided with a second via. The second lap wire includes a third lap portion disposed on the insulating layer and disposed in the same layer as the anode layer, and a fourth lap portion disposed in the second via. The third lap portion and the fourth lap portion are stacked, with the third lap portion covering the fourth lap portion. One end of the third lap portion is directly electrically connected to the cathode layer, and the other end of the third lap portion is directly electrically connected to the negative drive trace through the fourth lap portion.

2. The display panel as described in claim 1, characterized in that, The drive power trace layer includes a positive drive trace for connecting to the positive voltage.

3. The display panel as described in claim 2, characterized in that, The first metal layer further includes a source-drain layer constituting the source and drain of the thin-film transistor in the thin-film transistor layer. The display panel further includes an organic light-emitting layer disposed on the thin-film transistor layer. The organic light-emitting layer includes the anode layer, the cathode layer and an organic layer disposed between the two. The forward drive trace is directly electrically connected to the anode layer through a first bonding wire.

4. The display panel as described in claim 3, characterized in that, The organic light-emitting layer includes a pixel definition layer disposed on the insulating layer, the pixel definition layer defining a pixel opening, and the anode layer disposed in the pixel opening.

5. The display panel as described in claim 4, characterized in that, The insulating layer is provided with a first via. The first lap wire includes a first lap portion disposed on the insulating layer and disposed in the same layer as the anode layer, and a second lap portion disposed in the first via. The first lap portion is directly electrically connected to the anode layer, and the first lap portion is directly electrically connected to the forward drive trace through the second lap portion.

6. The display panel as described in claim 1, characterized in that, The first metal layer also includes a bonding metal layer located in the corresponding bonding area of ​​the display panel, and at least one protective metal layer is sequentially covered on the bonding metal layer.

7. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, on which a thin-film transistor layer is disposed; A first metal layer is disposed on the thin film transistor layer. The first metal layer includes at least a driving power trace layer disposed in the corresponding trace area of ​​the display panel, and a source-drain layer constituting the source and drain of the thin film transistor in the thin film transistor layer. The driving power trace layer includes a negative driving trace for connecting a negative voltage. An insulating layer is disposed on the thin-film transistor layer, and vias are formed on the insulating layer to expose the negative drive traces; A second metal layer is disposed on the thin film transistor layer. The second metal layer includes a lap electrode that overlaps the source and drain layers through the via and a third lap portion that overlaps with the negative drive trace through the via. A third metal layer is disposed on the thin film transistor layer. The third metal layer includes an anode layer covering the lap electrode and a fourth lap portion covering the third lap portion. The third lap portion and the fourth lap portion are stacked. An organic layer and a cathode layer are disposed on the anode layer, wherein one end of the third overlap is directly electrically connected to the cathode layer, and the other end of the third overlap is directly electrically connected to the negative drive line through the fourth overlap.

8. The method for manufacturing a display panel as described in claim 7, characterized in that, The drive power trace layer includes a forward drive trace for connecting a forward voltage, and the via exposes the source / drain layer and the forward drive trace. A second metal layer is disposed on the thin-film transistor layer, the second metal layer including a first overlap portion that overlaps with the forward drive trace through the via; The third metal layer includes a second overlap that covers the first overlap.

9. The method for manufacturing a display panel as described in claim 8, characterized in that, The first metal layer further includes a bonding metal layer located in the corresponding bonding area of ​​the display panel, and the second metal layer includes a first protective metal layer covering the bonding metal layer.

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