An IGBT device with a thyristor structure using self-biased MOS clamping

Abstract

The present invention relates to an IGBT device with a thyristor structure using self-biased MOS clamping, which can also be regarded as an integrated ETO device. The body region of the IGBT device is composed of multiple layers of P-type doped layers and N-type doped layers arranged alternately, and adjacent doped regions of the same conductive type are completely isolated by another conductive type doped region. The device of the present invention uses a self-biased MOS (Q2) to clamp the electric field shielding layer, so that the external control MOS (Q1, Q2) of the traditional ETO can be monolithically integrated into the device. At the same time, compared with the IGBT with a carrier storage layer, the self-biased MOS (Q2) clamps the drain potential of the MOS (Q1) in the structure of the present invention at a lower level, thereby greatly improving the doping concentration threshold of the carrier storage layer and reducing the on-state voltage drop of the device; and the clamped MOS drain potential can reduce the saturation current of the new structure, thereby increasing the short-circuit safe working area of ​​the new device.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices in the semiconductor industry, and provides an IGBT device with a thyristor structure using self-biased MOS clamping, which can also be regarded as an integrated ETO device. Background Art

[0002] IGBT is one of the basic power semiconductor devices. It combines the low on-state voltage drop of BJT and the fast switching characteristics of MOSFET, and is therefore widely used in power electronic systems.

[0003] When the IGBT is turned on, a large number of unbalanced carriers are injected into the collector to form a conductivity modulation effect to reduce the on-state voltage drop. When it is turned off, a large number of unbalanced carriers in the drift region take some time to disappear, thereby reducing the turn-off speed of the IGBT and increasing the turn-off loss. In order to optimize the trade-off relationship between the on-state voltage drop and the turn-off loss of the IGBT, an IGBT with a carrier storage layer is constructed. [1] It was proposed that this structure improves the injection efficiency of the IGBT emitter through a high-concentration carrier storage layer, thereby reducing the injection efficiency of the collector to obtain the same on-state voltage drop, and the low collector injection efficiency reduces the turn-off time, thereby optimizing the device performance. However, at the same time, excessively high carrier storage layer doping concentration will cause the IGBT's withstand voltage to drop sharply, and high emitter injection efficiency will also increase the IGBT's saturation current density, thereby reducing the device's short-circuit safe operating area. In order to balance the positive charge generated by the carrier storage layer with an excessively high doping concentration when the device withstands voltage, a trench-gate IGBT with a floating P-region electric field shielding layer was proposed [2] The negative charge generated by the floating P region of this structure when the device is depleted can balance the positive charge generated when the carrier storage layer is depleted, which helps to optimize the device performance; but with the expansion of the depletion region between the floating P region and the N-type drift region and the N-type carrier storage layer, the potential of the carrier storage layer and the floating P region will still increase, which still limits the doping concentration of the carrier storage layer. In order to further limit the potential of the floating P region, an IGBT with a carrier storage layer with a clamping MOS is proposed. [3] . This structure limits the potential of the floating P region through self-biased MOS, and then limits the potential of the carrier storage layer, thereby breaking through the limitation of the doping concentration of the carrier storage layer and obtaining better device characteristics. However, the lateral depletion between the floating P region and the N-type drift region will still cause the potential of the carrier storage layer to rise slowly, and the doping concentration of the carrier storage layer is still limited. Therefore, there is still great potential for optimization of the characteristics of the IGBT. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the problem of limited doping concentration of the carrier storage layer in the existing trench-gate IGBT with a carrier storage layer, further optimize the compromise relationship between the on-state voltage drop and the turn-off loss in the existing IGBT device, and in view of the problems of large saturation current density and small short-circuit safe operating area existing in the existing IGBT device, an IGBT device with a thyristor structure using self-biased MOS clamping is proposed.

[0005] In order to solve the above technical problems, the present invention proposes an IGBT device with a thyristor structure using self-biased MOS clamping, wherein the body region of the IGBT device is composed of multiple layers of P-type doped layers and N-type doped layers arranged alternately, including a base region, a carrier storage region, an electric field shielding layer, a drift region and a collector region, and adjacent regions doped with the same conductive type are completely isolated by regions doped with another conductive type.

[0006] In one embodiment of the present invention, the IGBT device is controlled by two types of MOSFET, wherein the MOSFET is a metal-oxide-semiconductor field effect transistor, wherein one type of MOS (Q1) is controlled by an external drive circuit; the other type of MOS (Q2) can be turned on by self-bias or controlled to be turned on by an external signal, wherein when the clamping MOS (Q2) is turned on by self-bias, its trench polysilicon is connected to the cathode electrode, and when the clamping MOS (Q2) is turned on by external signal control, its trench polysilicon is connected to the external control signal.

[0007] In one embodiment of the present invention, the MOS (Q1) is composed of a heavily doped emitter region 1, a base region 2, a cathode electrode 12 connected to the heavily doped emitter region 1 and the base region 2, a carrier storage layer 3, and a gate polysilicon 10 wrapped by an oxide layer. The MOS (Q2) is composed of an electric field shielding layer 6 clamping the carrier storage layer as its emitter region, a base region 5, a drain region 2, a cathode electrode 12 connected to the drain region 2, and a polysilicon trench 13 wrapped by an oxide layer. The number of the two control MOSs can be adjusted according to the required device characteristics, for example, increasing the number of Q1 to reduce the on-state voltage drop of the device, or increasing the number of Q2 to reduce the saturation current density of the device. The influence of the number of MOS on the device characteristics here is only an example. In fact, by adjusting the number and ratio of the two MOSs, a certain influence can be exerted on various device characteristics.

[0008] In one embodiment of the present invention, the alternately arranged P-type doped regions and N-type doped regions, including the carrier storage regions 3 and 5 , the electric field shielding layer 6 , the drift region 7 and the collector region 9 , constitute a thyristor structure.

[0009] In one embodiment of the present invention, the buffer layer 8 and the heavily doped emitter region 4 can be selectively added or removed between the alternately arranged P-type doping regions and N-type doping regions to adjust the injection efficiency of each PN junction of the parasitic thyristor.

[0010] In one embodiment of the present invention, the base region 2 and the emitter region 1, regardless of whether they are in the same connected trenches or between different connected trenches, can be connected to the cathode to obtain current conduction capability, or they can be isolated from the cathode by insulating materials so that the adjacent trenches act as dummy gates.

[0011] In one embodiment of the present invention, the groove of the clamping MOS (Q2) can be connected to the cathode or to the external control signal, or partially connected to the cathode and partially connected to the external control signal, and the groove of the clamping MOS (Q2) may not be connected to any electrode, that is, its potential is in a floating state.

[0012] The above technical solution of the present invention has the following advantages over the prior art: the IGBT device with a thyristor structure using self-biased MOS clamping described in the present invention adds an electric field shielding layer at the bottom of the trench gate on the basis of the IGBT structure with a carrier storage layer and a dummy gate (Dummy Trench), and forms a self-biased MOS structure that clamps the electric field shielding layer potential through the dummy gate. This structure breaks through the limitation of the doping concentration of the carrier storage layer, greatly improving the compromise relationship between the on-state voltage drop and the turn-off loss of the IGBT; and, thanks to the clamping effect of the self-biased MOS, the drain potential near the channel is clamped at a lower potential under high voltage, thereby greatly reducing the saturation current density of the new IGBT and improving the short-circuit safe operating area of ​​the new device. Therefore, the new IGBT in the present invention has a better compromise relationship between the on-state voltage drop and the turn-off loss, and has a lower saturation current density and a larger short-circuit safe operating area. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0014] Figure 1 is a longitudinal cross-sectional view of the IGBT device structure of the present invention;

[0015] Figure 2 This is the second longitudinal cross-sectional structure of the IGBT device of the present invention;

[0016] Figure 3 This is the third longitudinal cross-sectional structure of the IGBT device of the present invention;

[0017] Figure 4This is the fourth longitudinal cross-sectional structure of the IGBT device of the present invention;

[0018] Figure 5 It is a top view of a device with grooved gate distribution in the present invention;

[0019] Figure 6 is a top view of another device with grooved gate distribution in the present invention;

[0020] Figure 7 It is an equivalent circuit diagram of the structure of the present invention.

[0021] exist Figures 1 to 7 In the figure, 1 is the heavily doped emitter region of the turn-on MOS (Q1); 2 is the base region of the turn-on MOS (Q1); 3 is the carrier storage layer; 4 is the heavily doped emitter region of the parasitic thyristor; 5 is the base region of the clamped MOS (Q2); 6 is the electric field shielding layer of the clamped carrier storage layer; 7 is the drift region; 8 is the buffer layer; 9 is the collector region; 10 is the gate trench polysilicon; 11 is the anode electrode; 12 is the cathode electrode; 13 is the trench gate polysilicon of the clamped MOS (Q2). DETAILED DESCRIPTION

[0022] The present embodiment provides an IGBT device with a thyristor structure using self-biased MOS clamping, wherein the body region of the IGBT device is composed of multiple layers of P-type doped layers and N-type doped layers arranged alternately, including a base region 2, carrier storage regions 3 and 5, an electric field shielding layer 6, a drift region 7 and a collector region 9, and adjacent doped regions of the same conductive type are completely isolated by doped regions of another conductive type.

[0023] The present invention will be further described below in conjunction with the accompanying drawings:

[0024] like Figure 1As shown, this is a longitudinal cross-sectional view of the device structure of the present invention. Its structure can be simply divided into three parts: the parasitic thyristor region, the open MOS (Q1) region on the upper surface of the structure, and the clamped MOS (Q2) region on the upper surface of the structure. The thyristor region includes a carrier storage layer 3 (heavily doped emitter region 4), an electric field shielding layer 6, a drift region 7, a buffer layer 8 arranged at the bottom of the drift region, a collector region 9 arranged on the lower surface of the buffer layer 8, and a collector electrode 11 (anode electrode) arranged on the lower surface of the collector region. The open MOS (Q1) region on the upper surface of the structure consists of five parts, including a heavily doped emitter region 1, a base region 2, an emitter electrode 12 (cathode electrode) connected to 1 and 2, a carrier storage layer 3, and a gate polysilicon trench 10 wrapped by an oxide layer. The clamped MOS (Q2) region on the upper surface of the structure consists of five parts, including the electric field shielding layer 6 of the clamped carrier storage layer as its emitter region, the base region 5, the drain region 2, the cathode electrode 12 connected to 2, and the polysilicon trench 13 wrapped by the oxide layer. Among them, when the trench polysilicon 13 is connected to the cathode 12, the MOS is self-biased and turned on; when the trench polysilicon 13 is connected to an external control signal, it is turned on by external signal control.

[0025] Furthermore, the injection efficiency of each PN junction of the parasitic thyristor can be adjusted by adding or removing the buffer layer 8 and the heavily doped emitter region 4 between the alternating P-type doping regions and the N-type doping regions, and the injection efficiency of each PN junction of the parasitic thyristor can be obtained. Figure 2-Figure 4 structure.

[0026] Figure 2 The second longitudinal cross-sectional structure of the device of the present invention is shown. Figure 1 The main difference is that there is no buffer layer 8, so the structure has a greater collector junction injection efficiency, which reduces the device on-state voltage drop and increases the device off-time.

[0027] Figure 3 FIG. 2 shows a third longitudinal cross-sectional structure of the device of the present invention. Figure 1 The main difference is that there is no heavily doped emitter region 4, so the emitter junction injection efficiency of the parasitic thyristor of this structure is relatively small, which will increase the on-state voltage drop of the device, but at the same time this structure can reduce one injection and one mask plate during manufacturing, and has a lower manufacturing cost.

[0028] Figure 4 The fourth longitudinal cross-sectional structure of the device of the present invention is shown. Figure 1 The main difference is that there is no heavily doped emitter region 4 and buffer layer 8, combined with Figure 2 and Figure 3 From the analysis in , we can see that this structure is Figure 1 The structure will increase the turn-off time of the device but reduce the manufacturing cost.

[0029] Figure 5 A top view of a device with a groove gate distribution constructed using the concept of the present invention is shown, in which two types of grooves are alternately arranged horizontally, respectively connected to corresponding metal layers and isolated from another metal layer.

[0030] Figure 6 A top view of another device with a groove gate distribution formed by the concept of the present invention is shown. Figure 5 The main difference is that the slot gate uses another arrangement. Figure 5 and Figure 6 The polysilicon grooves 13 of the clamped MOS are all connected to the cathode electrode 12, forming a self-biased MOS structure. However, in actual use, the grooves 13 can be connected to the cathode or to the external control signal, or partially connected to the cathode and partially connected to the external control signal; the grooves 13 can also be not connected to any electrode, that is, their potential is in a floating state. Only two groove gate distribution structures are shown in this description, but the present structure can obtain a variety of groove gate distribution structures through a simple layout, which will not be exhaustively described in this description.

[0031] also, Figures 1 to 6 The base region 2 and the emitter region 1 described in the figure can be connected to the cathode to obtain current conduction capability regardless of whether they are in the same connected trenches or between different connected trenches, or they can be isolated from the cathode by insulating materials so that the adjacent trenches act as dummy gates. Figure 7 The equivalent circuit diagram of the present invention is shown. Q1 is a turn-on MOS; Q2 is a clamping MOS; GTO is a parasitic thyristor.

[0032] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

[0033] [1] H.Takahashi, et al. "Carrier stored trench-gate bipolar transistor (CSTBT)-a novel power device for high voltage application", in Proc.ISPSD, pp.349-352, 1996.

[0034] [2]R.Y.Ma,et al.“Carrier stored trench-gate bipolar transistor withp-floating layer",Journal of Semiconductors,31.2(2010):024004

[0035] [3]P.Li,X.Lyu,J.Cheng,and X.Chen,“A low on-state voltage andsaturation current TIGBT with self-biased pMOS,”IEEE Electron Device Lett.,vol.37,no.11,pp.1470–1472, Nov.2016.

Claims

1. An IGBT device with a thyristor structure using self-biased MOS clamping, characterized in that: The body region of the IGBT device structure is composed of multiple layers of P-type doped layers and N-type doped layers arranged alternately, including a base region 2, carrier storage regions 3 and 5, an electric field shielding layer 6, a drift region 7 and a collector region 9, and adjacent doped regions of the same conductive type are completely isolated by doped regions of another conductive type; the IGBT device is controlled by two types of MOSFET, wherein the MOSFET is a metal-oxide-semiconductor field effect transistor, one type of MOS (Q1) is controlled by an external drive circuit; the other type of MOS (Q2) is self-biased and turned on and is also controlled to be turned on by an external signal; The MOS (Q1) is composed of a heavily doped emitter region 1, a base region 2, a cathode electrode 12 connected to the heavily doped emitter region 1 and the base region 2, a carrier storage layer 3, and a gate polysilicon trench 10 wrapped by an oxide layer. The MOS (Q2) is composed of an electric field shielding layer 6 clamping the carrier storage layer as its emitter region, a base region 5, a drain region 2, a cathode electrode 12 connected to the drain region 2, and a polysilicon trench 13 wrapped by an oxide layer; wherein, when the MOS (Q2) is self-biased and turned on, the trench polysilicon 13 is connected to the cathode electrode 12; when the MOS (Q2) is turned on by external signal control, the trench polysilicon 13 is connected to the external control signal.

2. The body region of an IGBT device with a thyristor structure using self-biased MOS clamping according to claim 1, characterized in that: The alternately arranged P-type doped regions and N-type doped regions, including the carrier storage region 3 , the electric field shielding layer 6 , the drift region 7 and the collector region 9 , constitute a thyristor structure.

3. The body region of an IGBT device with a thyristor structure using self-biased MOS clamping according to claim 1, characterized in that: The injection efficiency of each PN junction of the parasitic thyristor is adjusted by adding a buffer layer 8 and a heavily doped emitter region 4 between the alternately arranged P-type doping regions and N-type doping regions.

4. The control MOS in an IGBT device with a thyristor structure using self-biased MOS clamping according to claim 1, characterized in that: Regardless of whether the base region 2 and the emitter region 1 are located in the same connected trench or between different connected trenches, the base region 2 and the emitter region 1 are connected to the cathode to obtain current conduction capability and are also isolated from the cathode by insulating materials, so that the adjacent trenches act as dummy gates.

5. The control MOS in an IGBT device with a thyristor structure using self-biased MOS clamping according to claim 1, characterized in that: The groove 13 is connected to the cathode or to an external control signal, or partially connected to the cathode and partially connected to an external control signal. The groove 13 is not connected to any electrode, that is, its potential is in a floating state.

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