Semiconductor device and manufacturing method
By optimizing the electric field distribution of the gate structure in RF LDMOS devices, the serious hot carrier injection effect of the device at high current density is solved, and a better current density and reliability compromise is achieved.
Patent Information
- Application Number
- CN202411545314.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-18
AI Technical Summary
While the existing RF LDMOS devices pursue high current density, the hot carrier injection effect is severe, resulting in device threshold voltage drift, static operating current reduction and reliability reduction.
By forming a gate dielectric layer and a gate field plate dielectric layer on the substrate, and setting the distance between the gate field plate and the device drain region in the horizontal direction is smaller than the distance between the gate electrode and the drain region, thereby reducing the gate structure towards one end of the drain region. electric field intensity.
While reducing the hot carrier injection effect, high current density is achieved, achieving a better compromise between the current density and the hot carrier injection effect, and improving the reliability of the device.
Smart Images
Figure CN119486175A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor technology and relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Radio frequency laterally diffused metal oxide semiconductor (RF LDMOS) is widely used in mobile base stations, radio and television, radar and other fields due to its low cost, high reliability, high gain and high linearity. For existing RF LDMOS devices, there is a contradiction between the hot carrier injection effect and the saturation current density: in order to obtain high current density, it is often achieved by increasing the injection concentration of the LDD drift region in the RFLDMOS device, and the injection concentration of the LDD drift region is closely related to the electric field strength distribution of the device. A higher LDD drift region injection concentration means a higher electric field strength, especially at the gate edge silicon surface near the drain end. The higher the electric field strength at the gate edge silicon surface near the drain end means that the hot carrier injection effect of the device is more serious, resulting in a drift in the device threshold voltage, a decrease in the static operating current of the device, and a decrease in the device reliability.
[0003] Therefore, how to provide a semiconductor device and a manufacturing method that has a low hot carrier injection effect while obtaining a high current density and improves device reliability has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to solve the contradiction between the high current density and the low hot carrier injection effect of the device in the prior art.
[0005] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
[0006] providing a substrate;
[0007] forming a gate dielectric layer on the upper surface of the substrate, and forming a gate field plate dielectric layer at a preset position above the gate dielectric layer;
[0008] A gate structure is formed, the gate structure comprising a gate electrode and a gate field plate connected to each other, wherein the gate electrode is located above the gate dielectric layer, the gate field plate is located above the gate field plate dielectric layer, and in the horizontal direction, the distance between the gate field plate and the device drain region is smaller than the distance between the gate electrode and the device drain region.
[0009] Optionally, the step of forming the gate field plate dielectric layer includes:
[0010] forming a gate field plate dielectric material layer on the gate dielectric layer;
[0011] The gate field plate dielectric material layer at a preset position is removed by etching, and the remaining gate field plate dielectric material layer constitutes the gate field plate dielectric layer, wherein during the process of etching away the gate field plate dielectric material layer, the etching stops at the surface of the gate dielectric layer.
[0012] Optionally, an etching selectivity ratio between the gate field plate dielectric material layer and the gate dielectric layer is not less than 15:1.
[0013] Optionally, the material of the gate field plate dielectric material layer includes silicon nitride, and the material of the gate dielectric layer includes silicon oxide.
[0014] Optionally, the step of forming the gate structure includes:
[0015] forming a conductive material layer on the surface of the structure after forming the gate dielectric layer and the gate field plate dielectric layer;
[0016] The conductive material layer is etched to form the gate electrode and the gate field plate at preset positions on the gate dielectric layer and the gate field plate dielectric layer.
[0017] Optionally, the substrate is a first conductive type substrate, and before forming the gate dielectric layer, the method further includes forming a second conductive type drift region in the substrate, wherein the drift region extends from the upper surface of the substrate to the interior of the substrate.
[0018] Optionally, after forming the gate structure, the following steps are further included:
[0019] forming a first conductivity type well region in the substrate, wherein a portion of the well region is located below the gate electrode;
[0020] A second conductive type source region is formed in the well region, and a second conductive type drain region is formed in the substrate. In the horizontal direction, the source region and the drain region are separated and arranged on both sides of the gate structure, and the well region and the drain region are isolated by the drift region.
[0021] Optionally, after forming the source region and the drain region, a step of forming a first field plate structure is also included, wherein the first field plate structure includes a first field plate dielectric layer and a first field plate electrode stacked from bottom to top, and the first field plate structure covers an end of the gate field plate away from the gate electrode.
[0022] Optionally, the first field plate dielectric layer includes a silicon oxide layer and a silicon nitride layer stacked from bottom to top.
[0023] Optionally, the method further includes forming a source electrode and a drain electrode on the substrate, wherein the source electrode is electrically connected to the source region, and the drain electrode is electrically connected to the drain region.
[0024] Optionally, the base includes a substrate and an epitaxial layer stacked from bottom to top, the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer, the drift region, the well region, the source region and the drain region are all located in the epitaxial layer, wherein:
[0025] Before forming the drift region, the method further includes forming a first conductive type lead-out region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the epitaxial layer, and the lead-out region penetrates the epitaxial layer and extends at least into the substrate;
[0026] The process of forming the source region further includes forming a first conductive type well contact region in the well region, wherein the doping concentration of the well contact region is greater than the doping concentration of the well region;
[0027] The source electrode is electrically connected to the source region, the well contact region and the lead-out region.
[0028] The present invention also provides a semiconductor device, comprising:
[0029] substrate;
[0030] A gate dielectric layer, located on the upper surface of the substrate;
[0031] A gate field plate dielectric layer, located at a preset position above the gate dielectric layer;
[0032] A gate structure comprises a gate electrode and a gate field plate connected to each other, wherein the gate electrode is located above the gate dielectric layer, the gate field plate is located above the gate field plate dielectric layer, and in the horizontal direction, the distance between the gate field plate and the device drain region is smaller than the distance between the gate electrode and the device drain region.
[0033] Optionally, an etching selectivity ratio between the gate field plate dielectric layer and the gate dielectric layer is not less than 15:1.
[0034] Optionally, the material of the gate field plate dielectric layer includes silicon nitride, and the material of the gate dielectric layer includes silicon oxide.
[0035] Optionally, the substrate is a first conductive type substrate, and further includes a second conductive type drift region, wherein the drift region is located in the substrate, and the drift region extends from the upper surface of the substrate to the interior of the substrate.
[0036] Optionally, it also includes:
[0037] A first conductive type well region, located in the substrate, a portion of the well region being located below the gate electrode;
[0038] A second conductive type source region located in the well region;
[0039] A second conductive type drain region is located in the substrate, wherein in a horizontal direction, the source region and the drain region are separately arranged on both sides of the gate structure, and the well region and the drain region are isolated by the drift region.
[0040] Optionally, a first field plate structure is further included, wherein the first field plate structure includes a first field plate dielectric layer and a first field plate electrode stacked from bottom to top, and the first field plate structure covers an end of the gate field plate away from the gate electrode.
[0041] Optionally, it also includes a second field plate structure, which includes a second field plate dielectric layer and a second field plate electrode stacked from bottom to top. In the vertical direction, the second field plate structure is located above the substrate, and in the horizontal direction, the second field plate structure is located between the gate structure and the drain region.
[0042] Optionally, it further includes a source and a drain, wherein the source and the drain are both located above the substrate, the source is electrically connected to the source region, and the drain is electrically connected to the drain region.
[0043] Optionally, the base includes a substrate and an epitaxial layer stacked from bottom to top, the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer, the drift region, the well region, the source region and the drain region are all located in the epitaxial layer, and further includes:
[0044] A first conductive type lead-out region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the epitaxial layer, and the lead-out region penetrates the epitaxial layer and extends at least into the substrate;
[0045] a first conductive type well contact region, the well contact region being located in the well region, and the doping concentration of the well contact region being greater than the doping concentration of the well region;
[0046] Wherein, the source electrode is electrically connected to the source region, the well contact region and the lead-out region.
[0047] As described above, in the semiconductor device and manufacturing method of the present invention, the end of the gate structure facing the device drain region is a gate field plate, and the thickness of the dielectric layer below the gate field plate is the sum of the thicknesses of the gate dielectric layer and the gate field plate dielectric layer, so that the electric field strength at the end of the gate structure facing the device drain region is reduced, and a high current density can be obtained while reducing the hot carrier injection effect, thereby achieving a better compromise between the current density and the hot carrier injection effect of the device; and, the drift region is formed by a non-photolithography mode before the gate structure is prepared, which simplifies the process flow and reduces the gate field plate process alignment accuracy requirements; in addition, the material of the gate field plate dielectric layer has a high etching selectivity ratio with the gate dielectric layer, and the gate field plate dielectric layer is prepared by a self-stop etching method, and the process is simple and controllable. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 Shown is a process flow chart of a method for manufacturing a semiconductor device in an embodiment of the present invention.
[0049] Figure 2 Shown is a schematic diagram of providing a substrate in an embodiment of the present invention.
[0050] Figure 3 It is a schematic diagram showing the formation of a lead-out region in an embodiment of the present invention.
[0051] Figure 4 It is a schematic diagram showing the formation of an isolation layer in an embodiment of the present invention.
[0052] Figure 5 It is a schematic diagram showing the formation of a drift region according to an embodiment of the present invention.
[0053] Figure 6 It is a schematic diagram showing the formation of a gate dielectric layer in an embodiment of the present invention.
[0054] Figure 7 It is a schematic diagram showing the formation of a gate field plate dielectric material layer in an embodiment of the present invention.
[0055] Figure 8 It is a schematic diagram showing the formation of a gate field plate dielectric layer in an embodiment of the present invention.
[0056] Fig. 9 It is a schematic diagram showing the formation of a gate structure according to an embodiment of the present invention.
[0057] Fig.10 It is a schematic diagram showing the formation of a well region in an embodiment of the present invention.
[0058] Fig.11 It is a schematic diagram showing the formation of source region, drain region and well contact region in an embodiment of the present invention.
[0059] Fig.12 It is a schematic diagram showing the formation of a source metal silicide layer and a drain metal silicide layer in an embodiment of the present invention.
[0060] Fig.13 It is a schematic diagram showing the formation of a first field plate structure in an embodiment of the present invention.
[0061] Fig.14 It is a schematic diagram showing the formation of a second field plate structure according to an embodiment of the present invention.
[0062] Fig.15 It is a schematic diagram showing the formation of an interlayer dielectric layer in an embodiment of the present invention.
[0063] Fig.16 It is a schematic diagram showing the formation of a first contact hole in an embodiment of the present invention.
[0064] Fig.17 It is a schematic diagram showing the formation of a first metal layer according to an embodiment of the present invention.
[0065] Fig.18 It is a schematic diagram showing the formation of an intermetallic dielectric layer according to an embodiment of the present invention.
[0066] Fig.19 It is a schematic diagram showing the formation of a second contact hole in an embodiment of the present invention.
[0067] Fig. 20 It is a schematic diagram showing the formation of a second metal layer according to an embodiment of the present invention.
[0068] Fig.21 It is a schematic diagram showing the formation of a passivation layer in an embodiment of the present invention.
[0069] Fig. 22 It is a schematic diagram showing the thinning of the back side of the substrate and forming a back side metal layer on the back side of the substrate in an embodiment of the present invention.
[0070] Fig.23 Shown is a schematic diagram of a semiconductor device in a comparative example.
[0071] Component number description
[0072] 1 Base
[0073] 100 Substrate
[0074] 101 Epitaxial layer
[0075] 2 Lead-out area
[0076] 3 Isolation layer
[0077] 4 Drift Zone
[0078] 5. Gate dielectric layer
[0079] 6. Gate field plate dielectric material layer
[0080] 7. Gate Field Plate Dielectric Layer
[0081] 8 Gate structure
[0082] 800 Gate electrode
[0083] 801 Gate Field Plate
[0084] 802 Polysilicon layer
[0085] 803 WSi alloy layer
[0086] 9 Well region
[0087] 10 Source area
[0088] 11 Drain area
[0089] 12 Well contact area
[0090] 13 Source metal silicide layer
[0091] 14 Drain metal silicide layer
[0092] 15. First Field Board Structure
[0093] 1500 First field plate dielectric layer
[0094] 1501 First Field Plate Electrode
[0095] 16 Second field board structure
[0096] 1600 Second field plate dielectric layer
[0097] 1601 Second field plate electrode
[0098] 17 Interlayer dielectric layer
[0099] 18 First contact hole
[0100] 19 First metal layer
[0101] 20 Intermetallic dielectric layer
[0102] 21 Second contact hole
[0103] 22 Second Metal Layer
[0104] 23 Passivation layer
[0105] 24 Back metal layer
[0106] Steps S1 to S3 DETAILED DESCRIPTION
[0107] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0108] See also Figures 1 to 23 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0109] This embodiment provides a method for manufacturing a semiconductor device. Figure 1 , including the following steps:
[0110] S1: Provide substrate;
[0111] S2: forming a gate dielectric layer on the upper surface of the substrate, and forming a gate field plate dielectric layer at a preset position above the gate dielectric layer;
[0112] S3: forming a gate structure, wherein the gate structure comprises a gate electrode and a gate field plate connected to each other, wherein the gate electrode is located above the gate dielectric layer, the gate field plate is located above the gate field plate dielectric layer, and in the horizontal direction, the distance between the gate field plate and the device drain region is smaller than the distance between the gate electrode and the device drain region.
[0113] The method for manufacturing the semiconductor device of this embodiment is described in detail below with reference to the specific drawings.
[0114] First, see Figure 2 , perform step S1: provide a substrate 1.
[0115] As an example, in this embodiment, the first conductivity type is P type and the second conductivity type is N type. In other examples, the first conductivity type can also be set to N type and the second conductivity type can be set to P type. In this embodiment, the semiconductor device is an RFLDMOS device.
[0116] As an example, the substrate 1 is a first conductive type substrate, and the substrate 1 includes a substrate 100 and an epitaxial layer 101 stacked from bottom to top, the substrate 100 is a Si substrate, the epitaxial layer 101 is a Si epitaxial layer, and the doping concentration of the epitaxial layer 101 is less than the doping concentration of the substrate 100, that is, the substrate 100 is a low-resistance P-type Si substrate, and the epitaxial layer 101 is a high-resistance P-type Si epitaxial layer; in other examples, the substrate 1 can also adopt any other suitable semiconductor substrate, such as a Ge substrate, a SiC substrate, a GaN substrate, etc., which can be selected according to actual needs.
[0117] As an example, the thickness of the substrate 100 is 1 mm, and the thickness of the epitaxial layer 101 is 5 μm; in other examples, the thickness of the substrate 100 and the epitaxial layer 101 can be changed as required, and is not limited to this embodiment.
[0118] As an example, see Figure 3After providing the substrate 1, the method further includes forming a first conductive type lead-out region 2, wherein the lead-out region 2 is a P-type heavily doped region (P+), and the lead-out region 2 extends through the epitaxial layer 101 into the substrate 100. The lead-out region 2 is used to subsequently introduce the device source into the substrate 100, thereby reducing the source end parasitic inductance. Specifically, the lead-out region 2 is formed by an ion implantation process, and the implanted ions are B ions, and then high-temperature junction activation is performed to achieve good interconnection with the substrate 100.
[0119] As an example, see Figure 4 , the epitaxial layer 101 in a preset area is oxidized by a local oxidation of silicon (LOCOS) process to form an isolation layer 3 to define an active area, wherein the lead-out area 2 is located in the active area; specifically, in this embodiment, a wet oxygen process is used to form the isolation layer 3, and in other examples, a dry process or other suitable methods can also be used to form the isolation layer 3.
[0120] As an example, see Figure 5 , and also includes forming a drift region 4, which is a second conductivity type drift region, wherein the drift region 4 is located in the epitaxial layer 101, and the drift region 4 is N-type lightly doped (NLDD). The drift region 4 can ensure that the device has sufficient breakdown voltage to meet its application requirements; specifically, the drift region 4 is formed by an ion implantation process, the implanted ions are P ions, and then the junction is activated by high temperature.
[0121] As an example, in the prior art, NLDD implantation is performed after the gate is formed, which usually requires high-precision photolithography technology to achieve alignment accuracy. In this embodiment, the drift region 4 is located between the gate structure 8 (see the following). Fig. 9 ) is prepared before, and no mask is required during the ion implantation process of the drift region 4, and it is formed by a non-photolithography mode, which not only simplifies the process flow but also reduces the process alignment accuracy requirements of the gate field plate, thereby greatly improving the process repeatability.
[0122] Next, see Figures 6 to 8 , executing step S2: forming a gate dielectric layer 5 on the upper surface of the substrate 1 , and forming a gate field plate dielectric layer 7 at a preset position above the gate dielectric layer 5 .
[0123] As an example, see Figure 6, forming the gate dielectric layer 5. The quality of the gate dielectric layer 5 is crucial to the characteristics of the RF LDMOS device. In this embodiment, the epitaxial layer 101 is oxidized by a dry oxygen process to form a uniform and dense gate dielectric layer 5. The material of the gate dielectric layer 5 is silicon oxide, and the thickness of the gate dielectric layer 5 is 30nm. In other examples, the gate dielectric layer 5 can also be formed by a wet oxygen process, a deposition process or other suitable methods, and the thickness of the gate dielectric layer 5 can also be changed according to requirements.
[0124] As an example, see Figure 7 , a gate field plate dielectric material layer 6 is formed on the gate dielectric layer 5 .
[0125] As an example, see Figure 8 , etching the gate field plate dielectric material layer at a preset position, and the retained gate field plate dielectric material layer constitutes the gate field plate dielectric layer 7. Since the gate field plate dielectric material layer 6 and the gate dielectric layer 5 have a high etching selectivity, the etching selectivity is not less than 15:1, and the material of the gate field plate dielectric material layer 6 is preferably silicon nitride material, the process of etching the gate field plate dielectric material layer to form the gate field plate dielectric layer 7 can stop on the surface of the gate dielectric layer 5, which reduces the process difficulty and improves the process controllability.
[0126] Next, see Fig. 9 , perform step S3: form a gate structure 8, the gate structure 8 includes a gate electrode 800 and a gate field plate 801 connected to each other, wherein the gate electrode 800 is located above the gate dielectric layer 5, and the gate field plate 801 is located above the gate field plate dielectric layer 7, and in the horizontal direction, the distance between the gate field plate 801 and the device drain region is smaller than the distance between the gate electrode 800 and the device drain region.
[0127] As an example, the gate structure 8 includes a high-concentration n-type polysilicon layer 802 and a WSi alloy layer 803 stacked from bottom to top, which reduces the gate resistance and improves the device's radio frequency performance; specifically, a high-concentration n-type polysilicon material layer and a W metal layer stacked from bottom to top are deposited on the surface of the structure before forming the gate dielectric layer 5 and the gate field plate dielectric layer 7, and then annealed to form a WSi alloy material layer, and then the WSi alloy material layer and the polysilicon material layer thereunder are etched in sequence to form the gate structure 8, wherein the thickness of the polysilicon layer 802 is 300nm, and the thickness of the WSi alloy layer 803 is 100nm. In other examples, the thickness of the polysilicon layer 802 and the WSi alloy layer 803 are changed according to demand.
[0128] As an example, in the horizontal direction, the distance between the gate field plate 801 and the device drain region is smaller than the distance between the gate electrode 800 and the device drain region, that is, the end of the gate structure 8 facing the device drain region is mounted on the gate field plate dielectric layer 7, and the length of the gate structure 8 mounted on the gate field plate dielectric layer 7 is 0.1 μm, that is, the length of the gate field plate 801 is 0.1 μm. In other examples, the length of the gate field plate 801 is changed according to demand.
[0129] As an example, in the present embodiment, the end of the gate structure 8 facing the device drain region is the gate field plate 801, and the thickness of the dielectric layer below the gate field plate 801 is the sum of the thicknesses of the gate dielectric layer 5 and the gate field plate dielectric layer 7, so that the electric field strength at the end of the gate structure 8 facing the device drain region is reduced, and while reducing the hot carrier injection effect, the injection concentration of the drift region 4 can be appropriately increased to obtain a high current density, thereby achieving a better compromise between the current density and the device hot carrier injection effect.
[0130] As an example, under the on condition, the gate field plate dielectric layer 7 (silicon nitride is a high-k dielectric) has a certain capacitive coupling effect on the drift region 4, thereby improving the JFET effect of the RF LDMOS device and increasing the on-current density.
[0131] Next, see Figure 10 to Figure 11 After forming the gate structure 8, the step of forming a well region 9, a source region 10 and a drain region 11 is also included.
[0132] As an example, see Fig.10 , forming the well region 9 of the first conductivity type in the epitaxial layer 101, a part of the well region 9 is located below the gate electrode 800; wherein the well region 9 is a P well (Pwell), the region of the well region 9 located below the gate electrode 800 constitutes a channel, the doping concentration of the well region 9 is greater than the doping concentration of the epitaxial layer 101, the well region 9 provides a threshold voltage (Vth) that meets the requirements for the RF LDMOS device, and at the same time, the well region 9 and the drift region 4 jointly limit the electric field strength of the gate structure 8 near the drain end. Specifically, the well region 9 is formed by ion implantation through a gate self-alignment process, the implanted ions are B ions, and then the junction is activated by high temperature.
[0133] As an example, see Fig.11 , a source region 10 of a second conductivity type is formed in the well region 9, and a drain region 11 of a second conductivity type is formed in the epitaxial layer 101. In the horizontal direction, the source region 10 and the drain region 11 are separated and arranged on both sides of the gate structure 8, and the well region 9 and the drain region 11 are isolated by the drift region 4.
[0134] As an example, the source region 10 is heavily doped with N type (N+), the drain region 11 is heavily doped with N type (N+), wherein the well region 9 is further formed with a heavily doped with P type (P+) well contact region 12 adjacent to the source region 10, for subsequent electrical connection between the well region 9 and the source. Specifically, As ions are injected into the source region 10, As ions are injected into the drain region 11, and B ions are injected into the well contact region 12, and then high temperature activation is performed.
[0135] As an example, see Fig.12 , further comprising the step of forming a source metal silicide layer 13 and a drain metal silicide layer 14 to further reduce the contact resistance; specifically, the step of forming the source metal silicide layer 13 and the drain metal silicide layer 14 comprises:
[0136] (i) forming a barrier layer on the structure after forming the source region 10, the drain region 11 and the well contact region 12, and etching the barrier layer to form an opening to expose the area where the metal silicide needs to be formed;
[0137] (ii) depositing a Ti metal layer, wherein a portion of the Ti metal layer falls into the opening and a portion of the Ti metal layer is located above the barrier layer;
[0138] (iii) then performing annealing to form the source metal silicide layer 13 and the drain metal silicide layer 14, wherein the source metal silicide layer 13 and the drain metal silicide layer 14 are both TiSi alloys, wherein the source metal silicide layer 13 is in contact with the lead-out region 2, the source region 10 and the well contact region 12, and the drain metal silicide layer 14 is in contact with the drain region 11;
[0139] (iv) etching and removing the Ti metal layer and the barrier layer located above the barrier layer.
[0140] As an example, see Fig.13 After forming the source metal silicide layer 13 and the drain metal silicide layer 14, the step of forming a first field plate structure 15 is also included. The first field plate structure 15 includes a first field plate dielectric layer 1500 and a first field plate electrode 1501 stacked from bottom to top. The first field plate structure 15 covers an end of the gate field plate 801 away from the gate electrode 800.
[0141] As an example, the first field plate dielectric layer 1500 is a stacked silicon oxide / silicon nitride with a thickness of 20nm / 80nm, and the silicon oxide is mainly used to relieve the stress of silicon nitride; the first field plate electrode 1501 is a W metal layer; specifically, in this embodiment, the first field plate dielectric layer 1500 covers the surface of the device structure after the source metal silicide layer 13 and the drain metal silicide layer 14 are formed, and then a W metal material layer is formed on the first field plate dielectric layer 1500 and etched to form the first field plate electrode 1501; in other examples, the first field plate dielectric layer 1500 can also be formed only in the area corresponding to the first field plate electrode 1501, and the silicon nitride in the first field plate dielectric layer 1500 can also be replaced by aluminum oxide, hafnium oxide, etc., and the thickness of the first field plate dielectric layer 1500 can also be changed according to needs.
[0142] As an example, see Fig.14 After forming the first field plate structure 15, the step of forming a second field plate structure 16 is also included. The second field plate structure 16 includes a second field plate dielectric layer 1600 and a second field plate electrode 1601 stacked from bottom to top. In the vertical direction, the second field plate structure 16 is located above the substrate 1, and in the horizontal direction, the second field plate structure 16 is located between the gate structure 8 and the drain region 11.
[0143] As an example, the second field plate dielectric layer 1600 can be a high-K dielectric layer or a low-K dielectric layer. In this embodiment, the second field plate dielectric layer 1600 is a silicon oxide layer, and the second field plate electrode 1601 is a W metal layer. Specifically, in this embodiment, the second field plate dielectric layer 1600 covers the surface of the device structure after the first field plate structure 15 is formed, and then a W metal material layer is formed on the second field plate dielectric layer 1600 and etched to form the second field plate electrode 1601. In other examples, the second field plate dielectric layer 1600 can also be formed only in the area corresponding to the second field plate electrode 1601, and the material and thickness of the second field plate dielectric layer 1600 can also be changed according to needs.
[0144] It should be noted that the first field plate structure 15 and the second field plate structure 16 are used to improve the surface electric field of the device, which helps to reduce the electric field concentration, improve the reliability of the device, and can reduce the on-resistance of the device, increase the conduction capability of the device, and improve the RF performance of the device. In other examples, more layers of field plate structures can be set, or the first field plate structure 15 and the second field plate structure 16 are not set, and the selection is made according to actual needs.
[0145] As an example, after forming the second field plate structure 16, the step of forming a source and a drain is further included, specifically, the following steps are included:
[0146] (a) If Fig.15 As shown, an interlayer dielectric layer 17 is formed on the structure after the second field plate structure 16 is formed by a deposition process, and the interlayer dielectric layer 17 is subjected to chemical mechanical polishing for planarization, wherein the material of the interlayer dielectric layer 17 is silicon oxide, and the thickness of the interlayer dielectric layer 17 after chemical mechanical polishing is 3 μm;
[0147] (ii) Fig.16 As shown, a first contact hole 18 is formed extending from the upper surface of the interlayer dielectric layer 17 to the inside of the device, wherein the first contact hole 18 includes at least three parts, wherein the first contact hole 18 is electrically connected to the source metal silicide layer 13, the first field plate structure 15 and the second field plate structure 16, wherein the second contact hole 18 is electrically connected to the drain metal silicide layer 14, and wherein the third contact hole 18 is electrically connected to the gate structure 8, so as to realize the external connection of the source, the gate, the drain, the first field plate structure 15 and the second field plate structure 16, wherein the formation of the first contact hole 18 includes the steps of dielectric layer etching and metal filling, and the metal material filled is W;
[0148] (III) Fig.17 As shown, a first metal layer 19 is formed on the interlayer dielectric layer 17, and the first metal layer 19 includes at least three parts, a first part of the first metal layer 19 is electrically connected to the first contact hole 18 of the first part, a second part of the first metal layer 19 is electrically connected to the first contact hole 18 of the second part, and a third part of the first metal layer 19 is electrically connected to the first contact hole 18 of the third part; specifically, an AlCu material layer is formed on the interlayer dielectric layer 17, and then the AlCu material layer is etched to be patterned to form the first metal layer 19;
[0149] (IV) Fig.18 As shown, an intermetallic dielectric layer 20 covering the first metal layer 19 is formed on the interlayer dielectric layer 17, and the intermetallic dielectric layer 20 is subjected to chemical mechanical polishing for planarization, wherein the material of the intermetallic dielectric layer 20 is silicon oxide, and the thickness of the intermetallic dielectric layer 20 after chemical mechanical polishing is 3 μm;
[0150] (V) Fig.19As shown, a second contact hole 21 is formed extending from the upper surface of the intermetallic dielectric layer 20 to the inside of the device, and the second contact hole 21 includes at least three parts, the first part of the second contact hole 21 is electrically connected to the first part of the first metal layer 19, the second part of the second contact hole 21 is electrically connected to the second part of the first metal layer 19, and the third part of the second contact hole 21 is electrically connected to the third part of the first metal layer 19, wherein the formation of the second contact hole 21 includes the steps of dielectric layer etching and metal filling, and the metal material filled is W;
[0151] (V) Fig. 20 As shown, a second metal layer 22 is formed on the intermetallic dielectric layer 20, the second metal layer 22 includes at least three parts, the first part of the second metal layer 22 is electrically connected to the first part of the second contact hole 21, the second part of the second metal layer 22 is electrically connected to the second part of the second contact hole 21, and the third part of the second metal layer 22 is electrically connected to the third part of the second contact hole 21, wherein the formation of the second metal layer 22 includes the steps of depositing and etching a material layer, the deposited material layer is an AlCu layer, and then the AlCu layer is etched to be patterned to form the second metal layer 22;
[0152] (VI) Fig.21 As shown, a passivation layer 23 covering the second metal layer 22 is formed on the intermetallic dielectric layer 20, and the passivation layer 23 includes stacked silicon oxide / silicon nitride; and after the passivation layer 23 is formed, it also includes forming a first opening in the passivation layer 23 to expose a first portion of the second metal layer 22 to form a source pad, forming a second opening in the passivation layer 23 to expose a second portion of the second metal layer 22 to form a drain pad, and forming a third opening in the passivation layer 23 to expose a third portion of the second metal layer 22 to form a gate pad.
[0153] It should be noted that, depending on the specific actual needs of the device, it may include or not include multiple intermetallic dielectric layers, second contact holes and second metal layers. There is no limitation here. The passivation layer covers the topmost second metal layer and intermetallic dielectric layer.
[0154] As an example, the drain pad, the drain pad and the gate pad are used to realize welding of the drain terminal, the drain terminal and the gate terminal of the device with an external device.
[0155] As an example, Fig. 22 As shown, the method also includes thinning the back side of the substrate 100 and forming a back side metal layer 24 on the back side of the thinned substrate 100, wherein the thickness of the substrate 100 after thinning is 0.1 mm, and the back side metal layer includes stacked Ti / Ni / Ag.
[0156] At this point, a semiconductor device is manufactured. Fig. 22 The semiconductor device includes a substrate 1, a gate dielectric layer 5, a gate field plate dielectric layer 7 and a gate structure 8; the gate dielectric layer 5 is located on the upper surface of the substrate 1; the gate field plate dielectric layer 7 is located at a preset position above the gate dielectric layer 5; the gate structure 8 includes a connected gate electrode 800 and a gate field plate 801, wherein the gate electrode 800 is located above the gate dielectric layer 5, the gate field plate 801 is located above the gate field plate dielectric layer 7, and in the horizontal direction, the distance between the gate field plate 801 and the device drain region is smaller than the distance between the gate electrode 800 and the device drain region.
[0157] As an example, the substrate 1 is a first conductive type substrate, and the substrate 1 includes a substrate 100 and an epitaxial layer 101 stacked from bottom to top, the substrate 100 is a Si substrate, the epitaxial layer 101 is a Si epitaxial layer, and the doping concentration of the epitaxial layer 101 is less than the doping concentration of the substrate 100, that is, the substrate 100 is a low-resistance P-type Si substrate, and the epitaxial layer 101 is a high-resistance P-type Si epitaxial layer.
[0158] As an example, a first conductive type lead-out region 2 is also included, and the lead-out region 2 is a P-type heavily doped region (P+). The lead-out region 2 extends through the epitaxial layer 101 into the substrate 100. The function of the lead-out region 2 is to subsequently introduce the device source into the substrate 100, thereby reducing the source end parasitic inductance.
[0159] As an example, an isolation layer 3 is further included, and the isolation layer 3 is located at a preset position of the epitaxial layer 101 to define an active area, wherein the lead-out area 2 is located in the active area.
[0160] As an example, a drift region 4 of the second conductivity type is further included. The drift region 4 is located in the epitaxial layer 101 , and the drift region 4 is N-type lightly doped (NLDD).
[0161] As an example, the material of the gate dielectric layer 5 is silicon oxide, the material of the gate field plate dielectric layer 7 is silicon nitride, and the etching selectivity ratio of the gate field plate dielectric layer 7 and the gate dielectric layer 5 is not less than 15:1.
[0162] As an example, the gate structure 8 includes a high-concentration n-type polysilicon layer and a WSi alloy layer stacked from bottom to top, which reduces the gate resistance and improves the radio frequency performance of the device.
[0163] As an example, in the horizontal direction, the distance between the gate field plate 801 and the device drain region is smaller than the distance between the gate electrode 800 and the device drain region, that is, the end of the gate structure 8 facing the device drain region is mounted on the gate field plate dielectric layer 7, and the length of the gate structure 8 mounted on the gate field plate dielectric layer 7 is the length of the gate field plate 801.
[0164] As an example, a well region 9 (Pwell) of the first conductivity type is also included. The well region 9 is located in the epitaxial layer 101 , and a portion of the well region 9 is located below the gate electrode 800 .
[0165] As an example, a source region 10 (N+) of the second conductivity type is further included, and the source region 10 is located in the well region 9 .
[0166] As an example, a drain region 11 (N+) of the second conductivity type is also included, and the drain region 11 is located in the epitaxial layer 101. In the horizontal direction, the source region 10 and the drain region 11 are separated and arranged on both sides of the gate structure 8, and the well region 9 and the drain region 11 are isolated by the drift region 4.
[0167] As an example, a well contact region 12 (P+) adjacent to the source region 10 is further provided in the well region 9 for subsequent electrical connection between the well region 9 and the source.
[0168] As an example, it also includes a source metal silicide layer 13 and a drain metal silicide layer 14 , the source metal silicide layer 13 is in contact with the lead-out region 2 , the source region 10 and the well contact region 12 , and the drain metal silicide layer 14 is in contact with the drain region 11 .
[0169] As an example, a first field plate structure 15 is also included. The first field plate structure 15 includes a first field plate dielectric layer 1500 and a first field plate electrode 1501 stacked from bottom to top. The first field plate structure 15 covers one end of the gate field plate 801 away from the gate electrode 800.
[0170] As an example, a second field plate structure 16 is also included, and the second field plate structure 16 includes a second field plate dielectric layer 1600 and a second field plate electrode 1601 stacked from bottom to top. In the vertical direction, the second field plate structure 16 is located above the substrate 1, and in the horizontal direction, the second field plate structure 16 is located between the gate structure 8 and the drain region 11.
[0171] It should be noted that the first field plate structure 15 and the second field plate structure 16 are used to improve the surface electric field of the device, which helps to reduce the electric field concentration, improve the reliability of the device, and can reduce the on-resistance of the device, increase the conduction capability of the device, and improve the RF performance of the device. In other examples, more layers of field plate structures can be set, or the first field plate structure 15 and the second field plate structure 16 are not set, and the selection is made according to actual needs.
[0172] As an example, an interlayer dielectric layer 17 is further included, and the interlayer dielectric layer 17 covers the first field plate structure 15 , the second field plate structure 16 , the gate structure 8 and the substrate 1 .
[0173] As an example, it also includes a first contact hole 18, which extends from the upper surface of the interlayer dielectric layer 17 to the inside of the device. The first contact hole 18 includes at least three parts. The first part of the first contact hole 18 is electrically connected to the source metal silicide layer 13, the first field plate structure 15 and the second field plate structure 16, the second part of the first contact hole 18 is electrically connected to the drain metal silicide layer 14, and the third part of the first contact hole 18 is electrically connected to the gate structure 8.
[0174] As an example, it also includes a first metal layer 19, which is located on the interlayer dielectric layer 17. The first metal layer 19 includes at least three parts. The first part, the first metal layer 19 is electrically connected to the first part, the first contact hole 18, the second part, the first metal layer 19 is electrically connected to the second part, the first contact hole 18, and the third part, the first metal layer 19 is electrically connected to the third part, the first contact hole 18.
[0175] As an example, an intermetallic dielectric layer 20 is further included. The intermetallic dielectric layer 20 is located above the interlayer dielectric layer 17 and covers the first metal layer 19 .
[0176] As an example, it also includes a second contact hole 21, which extends from the upper surface of the intermetallic dielectric layer 20 to the inside of the device. The second contact hole 21 includes at least three parts. The first part, the second contact hole 21 is electrically connected to the first part of the first metal layer 19, the second part, the second contact hole 21 is electrically connected to the second part of the first metal layer 19, and the third part, the second contact hole 21 is electrically connected to the third part of the first metal layer 19.
[0177] As an example, a second metal layer 22 is also included, and the second metal layer 22 is located above the intermetallic dielectric layer 20. The second metal layer 22 includes at least three parts. The first part, the second metal layer 22 is electrically connected to the first part, the second contact hole 21, the second part, the second metal layer 22 is electrically connected to the second part, the second contact hole 21, and the third part, the second metal layer 22 is electrically connected to the third part, the second contact hole 21.
[0178] As an example, a passivation layer 23 is also included, and the passivation layer 23 is located above the intermetallic dielectric layer 20 and covers the second metal layer 22. The passivation layer 23 is provided with a first opening to expose a first part of the second metal layer 22 to form a source pad, and the passivation layer 23 is provided with a second opening to expose a second part of the second metal layer 22 to form a drain pad. The passivation layer 23 is provided with a third opening to expose a third part of the second metal layer 22 to form a gate pad.
[0179] It should be noted that, depending on the specific actual needs of the device, it may include or not include multiple intermetallic dielectric layers, second contact holes and second metal layers. There is no limitation here. The passivation layer covers the topmost second metal layer and intermetallic dielectric layer.
[0180] As an example, a back metal layer 24 is further included, and the back metal layer 24 is located on the back side of the substrate 100 .
[0181] As an example, see Fig.23 , which is a schematic diagram of a semiconductor device in a comparative example. In the semiconductor device in the comparative example, the gate structure only includes a gate electrode 800. The electric field strength at point A at one end of the gate electrode 800 close to the drain region is mainly regulated by the first field plate electrode 1501. The regulation effect is relatively weak, resulting in a higher electric field strength at point A. Please refer to Fig. 22 In the semiconductor device of this embodiment, the gate structure includes a gate electrode 800 and a gate field plate 801. Since the gate field plate 801 controls the electric field strength at point A, the regulating effect of the field plate on point A is increased, so that the electric field peak moves from point A to point A', and the dielectric layer corresponding to point A' is much thicker than the dielectric layer corresponding to point A, so that the electric field strength of the gate structure 8 near the drain region is lower than that of the comparative example, thereby achieving a better compromise between the current density and the hot carrier injection effect of the device.
[0182] Specifically, referring to Table 1 below, the saturation current density of the semiconductor device in the comparative example and the electric field strength of the gate structure near the drain region are used as normalized conditions to compare the semiconductor device of the present embodiment with the semiconductor device of the comparative example. The saturation current density of the RF LDMOS of the present embodiment increases by 5%, and the electric field strength decreases by 10% under the corresponding breakdown voltage condition.
[0183] Table 1:
[0184] Saturation current density Electric field strength Comparative RF LDMOS 1 1(Point A) In this embodiment, RF LDMOS 1.05 0.9(Point A')
[0185] In summary, in the semiconductor device and manufacturing method of the present invention, the end of the gate structure facing the device drain region is the gate field plate, and the thickness of the dielectric layer below the gate field plate is the sum of the thickness of the gate dielectric layer and the gate field plate dielectric layer, so that the electric field strength at the end of the gate structure facing the device drain region is reduced, and a high current density can be obtained while reducing the hot carrier injection effect, achieving a better compromise between the current density and the device hot carrier injection effect; and, the drift region is formed by a non-photolithography mode before the gate structure is prepared, which simplifies the process flow and reduces the gate field plate process alignment accuracy requirements; in addition, the material of the gate field plate dielectric layer has a high etching selectivity with the gate dielectric layer, and the gate field plate dielectric layer is prepared by a self-stop etching method, and the process is simple and controllable. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0186] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: providing a substrate; forming a gate dielectric layer on the upper surface of the substrate, and forming a gate field plate dielectric layer at a preset position above the gate dielectric layer; A gate structure is formed, the gate structure comprising a gate electrode and a gate field plate connected to each other, wherein the gate electrode is located above the gate dielectric layer, the gate field plate is located above the gate field plate dielectric layer, and in the horizontal direction, the distance between the gate field plate and the device drain region is smaller than the distance between the gate electrode and the device drain region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the gate field plate dielectric layer comprises: forming a gate field plate dielectric material layer on the gate dielectric layer; The gate field plate dielectric material layer at a preset position is removed by etching, and the remaining gate field plate dielectric material layer constitutes the gate field plate dielectric layer, wherein during the process of etching away the gate field plate dielectric material layer, the etching stops at the surface of the gate dielectric layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The etching selection ratio between the gate field plate dielectric material layer and the gate dielectric layer is not less than 15:
1.
4. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the gate field plate dielectric material layer includes silicon nitride, and the material of the gate dielectric layer includes silicon oxide.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the gate structure include: forming a conductive material layer on the surface of the structure after forming the gate dielectric layer and the gate field plate dielectric layer; The conductive material layer is etched to form the gate electrode and the gate field plate at preset positions on the gate dielectric layer and the gate field plate dielectric layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate is a first conductive type substrate. Before forming the gate dielectric layer, the process further includes forming a second conductive type drift region in the substrate. The drift region extends from the upper surface of the substrate to the interior of the substrate.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: After forming the gate structure, the following steps are also included: forming a first conductive type well region in the substrate, wherein a portion of the well region is located below the gate electrode; A second conductive type source region is formed in the well region, and a second conductive type drain region is formed in the substrate. In the horizontal direction, the source region and the drain region are separated and arranged on both sides of the gate structure, and the well region and the drain region are isolated by the drift region.
8. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the source region and the drain region, the step of forming a first field plate structure is also included. The first field plate structure includes a first field plate dielectric layer and a first field plate electrode stacked from bottom to top. The first field plate structure covers one end of the gate field plate away from the gate electrode.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: The first field plate dielectric layer includes a silicon oxide layer and a silicon nitride layer stacked from bottom to top.
10. The method for manufacturing a semiconductor device according to any one of claims 7 to 9, characterized in that: The method further includes forming a source electrode and a drain electrode on the substrate, wherein the source electrode is electrically connected to the source region, and the drain electrode is electrically connected to the drain region.
11. The method for manufacturing a semiconductor device according to claim 10, wherein: The base comprises a substrate and an epitaxial layer stacked from bottom to top, the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer, the drift region, the well region, the source region and the drain region are all located in the epitaxial layer, wherein: Before forming the drift region, the method further includes forming a first conductive type lead-out region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the epitaxial layer, and the lead-out region penetrates the epitaxial layer and extends at least into the substrate; The process of forming the source region further includes forming a first conductive type well contact region in the well region, wherein the doping concentration of the well contact region is greater than the doping concentration of the well region; The source electrode is electrically connected to the source region, the well contact region and the lead-out region.
12. A semiconductor device, characterized in that: include: substrate; A gate dielectric layer, located on the upper surface of the substrate; A gate field plate dielectric layer, located at a preset position above the gate dielectric layer; A gate structure comprises a gate electrode and a gate field plate connected to each other, wherein the gate electrode is located above the gate dielectric layer, the gate field plate is located above the gate field plate dielectric layer, and in the horizontal direction, the distance between the gate field plate and the device drain region is smaller than the distance between the gate electrode and the device drain region.
13. The semiconductor device according to claim 12, wherein: The etching selection ratio between the gate field plate dielectric layer and the gate dielectric layer is not less than 15:
1.
14. The semiconductor device according to claim 12, wherein: The material of the gate field plate dielectric layer includes silicon nitride, and the material of the gate dielectric layer includes silicon oxide.
15. The semiconductor device according to claim 12, wherein: The substrate is a first conductive type substrate, and further comprises a second conductive type drift region, wherein the drift region is located in the substrate and extends from the upper surface of the substrate to the interior of the substrate.
16. The semiconductor device according to claim 15, characterized in that Also includes: A first conductive type well region, located in the substrate, a portion of the well region being located below the gate electrode; A second conductive type source region located in the well region; A second conductive type drain region is located in the substrate, wherein in a horizontal direction, the source region and the drain region are separated and arranged on both sides of the gate structure, and the well region and the drain region are isolated by the drift region.
17. The semiconductor device according to claim 16, wherein: It also includes a first field plate structure, which includes a first field plate dielectric layer and a first field plate electrode stacked from bottom to top, and covers one end of the gate field plate away from the gate electrode.
18. The semiconductor device according to claim 17, wherein: It also includes a second field plate structure, which includes a second field plate dielectric layer and a second field plate electrode stacked from bottom to top. In the vertical direction, the second field plate structure is located above the substrate, and in the horizontal direction, the second field plate structure is located between the gate structure and the drain region.
19. The semiconductor device according to any one of claims 16 to 18, characterized in that: It also includes a source electrode and a drain electrode, wherein the source electrode and the drain electrode are both located above the substrate, the source electrode is electrically connected to the source region, and the drain electrode is electrically connected to the drain region.
20. The semiconductor device according to claim 19, characterized in that The base comprises a substrate and an epitaxial layer stacked from bottom to top, the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer, the drift region, the well region, the source region and the drain region are all located in the epitaxial layer, and further comprises: A first conductive type lead-out region, wherein the doping concentration of the lead-out region is greater than the doping concentration of the epitaxial layer, and the lead-out region penetrates the epitaxial layer and extends at least into the substrate; a first conductive type well contact region, the well contact region being located in the well region, and the doping concentration of the well contact region being greater than the doping concentration of the well region; Wherein, the source electrode is electrically connected to the source region, the well contact region and the lead-out region.