A pnitride-enhanced field effect transistor based on a p-buried layer

Abstract

The application relates to a nitride-enhanced field effect transistor based on a P buried layer, comprising a substrate layer, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, an AlN barrier layer and an InN cap layer which are sequentially stacked; wherein a groove is arranged in the GaN buffer layer, a P-GaN buried layer is arranged at the bottom of the groove, the thickness of the P-GaN buried layer is less than or equal to the depth of the groove, and the P-GaN buried layer is used for locally depleting two-dimensional electron gas in the GaN channel layer; and a source metal layer, a drain metal layer and a gate metal layer are arranged on the cap layer in a spaced mode. The device is provided with the P-GaN buried layer for depleting two-dimensional electron gas in the GaN channel layer, the distance between the gate and the channel in the nitride-enhanced field effect transistor is shortened, the electric field intensity from the gate to the channel is more favorable for being enhanced, the gate control capability of the device is improved, and the device has more excellent performance.

Description

A nitride enhancement field-effect transistor based on a P-buried layer Technical Field

[0001] This invention belongs to the field of semiconductor devices, specifically relating to a nitride-enhanced field-effect transistor based on a P-buried layer. Background Technology

[0002] In the continuous evolution of semiconductor technology, the AlGaN / GaN material system has emerged as a promising and valuable research area. Modern power systems have an urgent need for efficient, high-power-density power conversion devices. Traditional silicon-based power devices are gradually approaching the limits of their material performance when facing ever-increasing power handling requirements. AlGaN / GaN heterojunctions, however, exhibit superior advantages due to their unique physical properties. At the interface of this heterojunction, a two-dimensional electron gas (2DEG) with high electron mobility and high concentration can be naturally formed. High electron mobility means that electrons can move rapidly within the material, greatly reducing resistive losses; the high concentration of 2DEG provides ample charge carriers for the conduction of large currents. This enables AlGaN / GaN-based high electron mobility transistors (HEMTs) to exhibit excellent performance in high-voltage, high-power applications. Furthermore, due to their wide bandgap and excellent electron transport properties, AlGaN / GaN HEMT devices can operate stably in the millimeter-wave frequency band, achieving high-power, high-efficiency signal amplification and transmission. Compared to traditional silicon-based or gallium arsenide-based RF devices, the application of AlGaN / GaN RF devices in base station power amplifiers can significantly improve signal coverage and communication quality, while reducing base station power consumption and construction costs.

[0003] The conventional technique is to grow a P-GaN cap layer on the AlGaN barrier layer to deplete the two-dimensional electron gas in the channel layer, thereby achieving the transition of the device from the off state to the on state. However, this structural design increases the distance between the gate and the channel, which weakens the electric field strength from the gate to the channel. This significantly reduces the gate control capability of the device and greatly diminishes its performance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a nitride-enhanced field-effect transistor based on a P-buried layer. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a nitride enhancement field-effect transistor based on a P-buried layer, comprising: a substrate layer, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, an AlN barrier layer, and an InN cap layer stacked sequentially; wherein, a groove is formed in the GaN buffer layer, and a P-GaN buried layer is formed at the bottom of the groove, the thickness of the P-GaN buried layer being equal to the depth of the groove, and the P-GaN buried layer being used to locally deplete the two-dimensional electron gas in the GaN channel layer; a source metal layer, a drain metal layer, and a gate metal layer are disposed at intervals on the InN cap layer, and the gate metal layer is located between the source metal layer and the drain metal layer.

[0006] In some embodiments, the thickness of the GaN buffer layer ranges from 1 μm to 2 μm, and the depth of the groove ranges from 60 nm to 200 nm.

[0007] In some embodiments, the doping element of the P-GaN buried layer is Mg, and the doping concentration ranges from 1×10⁻⁶. 17 cm -3 ~5×10 20 cm -3 .

[0008] In some embodiments, the thickness of the GaN channel layer ranges from 300 nm to 800 nm.

[0009] In some embodiments, the thickness of the AlN barrier layer ranges from 3 nm to 11 nm.

[0010] In some embodiments, the thickness of the InN cap layer ranges from 1 nm to 5 nm.

[0011] In some embodiments, the thickness of the AlN nucleation layer ranges from 20 nm to 100 nm.

[0012] In some embodiments, the source metal layer and the drain metal layer are made of a stacked metal of Ti, Al, Ni, and Au, and the gate metal layer is made of a stacked metal of Ni and Au.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] Existing fabrication methods increase the distance between the gate and channel of field-effect transistors (FETs), weakening the electric field strength from the gate to the channel. This significantly reduces the device's gate control capability and compromises its performance. This invention provides a nitride-enhanced field-effect transistor (FET) based on a P-buried layer. This transistor embeds a P-GaN buried layer within a GaN buffer layer to deplete the two-dimensional electron gas in the GaN channel layer. Compared to a P-GaN cap layer, this structure shortens the gate-channel distance in the FET, further enhancing the gate-channel electric field strength and improving gate control capability. Using AlN instead of AlGaN as the barrier layer to form an AlN / GaN heterojunction with the GaN channel layer allows for the generation of a higher density of two-dimensional electron gas due to AlN's stronger polarization effect. Furthermore, using an InN cap layer above the barrier layer utilizes the smaller work function difference between InN and the metal to achieve lower contact resistance, resulting in superior device performance and promising applications in power electronics, communications, and aerospace. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the structure of the nitride enhancement field-effect transistor based on the P-buried layer proposed in this invention;

[0016] Figure 2 is a schematic diagram of the fabrication process of a nitride-enhanced field-effect transistor based on a buried P layer provided in an embodiment of the present invention.

[0017] Figure label:

[0018] 1: Substrate layer; 2: AlN nucleation layer; 3: GaN buffer layer; 4: P-GaN buried layer; 5: GaN channel layer; 6: AlN barrier layer; 7: InN cap layer; 8: Source metal layer; 9: Drain metal layer; 10: Gate metal layer. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0021] The present invention will now be described in detail with reference to the accompanying drawings, a nitride-enhanced field-effect transistor based on a P-buried layer.

[0022] Figure 1 is a schematic diagram of the structure of the nitride enhancement field-effect transistor based on a P-buried layer proposed in this invention. It should be noted that this is only a schematic diagram and does not limit the thickness of each layer or the color of the materials. As shown in Figure 1, the device includes: a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 5, an AlN barrier layer 6, and an InN cap layer 7 stacked sequentially; wherein, a groove is formed in the GaN buffer layer 3, and a P-GaN buried layer 4 is filled in the groove. The thickness of the P-GaN buried layer 4 is equal to the depth of the groove. The P-GaN buried layer 4 is used to locally deplete the two-dimensional electron gas in the GaN channel layer 5; a source metal layer 8, a drain metal layer 9, and a gate metal layer 10 are disposed at intervals on the InN cap layer 7, and the gate metal layer 10 is located between the source metal layer 8 and the drain metal layer 9.

[0023] Specifically, the substrate 1 is made of sapphire, and its thickness ranges from 100 μm to 1 mm. The AlN nucleation layer 2 has a thickness ranging from 20 nm to 100 nm.

[0024] Here, the thickness of the GaN buffer layer 3 ranges from 1 μm to 2 μm, the depth of the trench ranges from 60 nm to 200 nm, and the corresponding thickness of the P-GaN buried layer 4 ranges from 60 nm to 200 nm. Furthermore, the doping element of the P-GaN buried layer 4 is Mg, and the doping concentration ranges from 1 × 10⁻⁶. 17 cm -3 ~5×10 20 cm -3 .

[0025] Here, the AlN barrier layer 6 and the GaN channel layer 5 constitute an AlN / GaN heterojunction, wherein the thickness of the AlN barrier layer 6 ranges from 3 nm to 11 nm. Compared to the AlGaN / GaN heterojunction, it can achieve higher polarization and generate a higher density of two-dimensional electron gas. Furthermore, by setting a P-GaN buried layer 4 inside the GaN buffer layer 3 to deplete the two-dimensional electron gas corresponding to the buried layer position in the GaN channel layer 5, the distance between the gate and the channel is shortened, which is more conducive to enhancing the electric field strength from the gate to the channel and improving the gate control capability of the device.

[0026] Please refer to Figure 1. The thickness of the GaN channel layer 5 ranges from 300nm to 800nm.

[0027] Here, the InN cap layer 7 is used to reduce contact resistance, and the thickness of the InN cap layer 7 ranges from 1 nm to 5 nm. Since AlN is not easy to fabricate good ohmic contacts, using the InN cap layer 7, which has a smaller difference in work function compared to metals, can achieve lower contact resistance.

[0028] Here, the source metal layer 8 and drain metal layer 9 are made of a stacked metal of Ti, Al, Ni, and Au, wherein the thickness of Ti metal is approximately 15 nm, the thickness of Al metal is approximately 85 nm, the thickness of Ni metal is approximately 30 nm, and the thickness of Au metal is approximately 40 nm. The gate metal layer 10 is made of a stacked metal of Ni and Au, wherein the thickness of Ni metal is approximately 30 nm, and the thickness of Au metal is approximately 100 nm.

[0029] Corresponding to the nitride-enhanced field-effect transistor based on a P-buried layer proposed in this embodiment of the invention, this embodiment also provides a method for fabricating a nitride-enhanced field-effect transistor based on a P-buried layer. Figure 2 is a schematic diagram of the fabrication process of the nitride-enhanced field-effect transistor based on a P-buried layer provided in this embodiment of the invention. It should be noted that Figure 2 includes 9 sub-figures, and the direction of the arrows represents the fabrication sequence of the device. Furthermore, for simplicity and to facilitate clear identification of newly added parts, components already appearing in previous sub-figures are not numbered in each sub-figure; only newly added components in the current sub-figure are numbered.

[0030] Specifically, the preparation method includes:

[0031] Step 1: First, the sapphire substrate layer 1 is cleaned to remove surface impurities and contaminants. The substrate is immersed in an acetone solution, then ultrasonically cleaned, followed by rinsing with anhydrous ethanol to remove the acetone and drying to remove organic impurities. Then, it is treated with an acidic or alkaline solution to remove inorganic impurities. The cleaned substrate is then heat-treated in a high-temperature (1000℃~1200℃) hydrogen (H₂) atmosphere. The hydrogen flow rate can be set to 1~5L / min. This step is mainly to remove the oxide layer on the substrate surface, making the surface smoother and more activated, providing a good foundation for subsequent epitaxial growth. Finally, the substrate is nitrided at a temperature of 1000~1050℃, during which a mixture of H₂ and NH₃ gases is introduced.

[0032] Step 2: Using MOCVD process, AlN nucleation layer 2 is prepared on the pretreated substrate layer 1, as shown in Figure 2 (1). Specifically, the temperature in the reaction chamber is set to 1000℃ and the pressure is 100Torr. Trimethylaluminum (TMAl) at 60sccm and ammonia (NH2) at 1500sccm are used as raw materials, and hydrogen (H2) at 2000sccm is used as carrier gas to deposit the nucleation layer. This nucleation layer provides nucleation centers with the same orientation as the substrate, which can convert the 3D growth mode of GaN in the early stage into a 2D layered growth mode.

[0033] Step 3: On the AlN nucleation layer 2, an unintentionally doped GaN buffer layer 3 is prepared using MOCVD, MBE, or HVPE processes, as shown in (2) of Figure 2. Taking the MOCVD process as an example, the temperature in the reaction chamber is set to 1050℃, and trimethylgallium (TMGa) with a flow rate of 150 sccm and NH3 with a flow rate of 5000 sccm are introduced, with hydrogen gas at 8000 sccm as the carrier gas. Under the condition of maintaining a pressure of 100 Torr, the GaN buffer layer is grown to alleviate lattice mismatch and reduce stress.

[0034] Step 4: Using plasma reactive ion etching technology, a groove of a certain depth is etched at the center of the GaN buffer layer 3. First, a layer of positive photoresist is spin-coated on the upper surface of the buffer layer, and photolithography is performed using a mask with a specific groove pattern. Ultraviolet exposure is used to transfer the mask pattern onto the photoresist. The exposed sample is placed in a developing solution for development, so that a groove pattern corresponding to the mask is formed on the photoresist. Inductively coupled plasma etching technology is used, with chlorine (Cl2) and boron trichloride (BCl2) as etching gases. The chlorine flow rate is 30 sccm to 50 sccm, the boron trichloride flow rate is 10 sccm to 20 sccm, and the etching power is 300W to 500W, so as to form a groove on the buffer layer, as shown in (3) of Figure 2.

[0035] Step 5: Prepare a P-GaN buried layer 4 at the bottom of the groove, wherein the thickness of the P-GaN buried layer 4 is less than or equal to the depth of the groove, as shown in (4) of Figure 2. Taking the MOCVD process as an example, maintain the reaction chamber temperature at 1050℃ and the pressure at 120 Torr, and introduce trimethylgallium (TMG) with a flow rate of 30 sccm and ammonia (NH2) with a flow rate of 1500 sccm as growth sources, while introducing magnesia pyrocene (Cp2Mg) as a doping source with a flow rate of approximately 3 sccm. During the growth process, by precisely controlling the parameters such as the flow rate, temperature and pressure of each gas, ensure that P-GaN grows uniformly in the groove and has good crystal quality and electrical properties;

[0036] Step 6: Using MOCVD, MBE, or HVPE processes, prepare a GaN channel layer 5 on the GaN buffer layer 3, as shown in (5) of Figure 2. Taking MOCVD as an example, maintain the temperature of the reaction chamber at 1050℃ and the pressure at 100 Torr, and introduce a nitrogen source with a flow rate of 2500 sccm, a gallium source with a flow rate of 70 sccm, and 5000 sccm of hydrogen as the carrier gas to grow a 400 nm GaN channel layer on the buffer layer;

[0037] Step 7: Using MOCVD, MBE, or HVPE processes, an AlN barrier layer 6 is prepared on the GaN channel layer 5, as shown in (6) of Figure 2. Taking MOCVD as an example, the temperature of the reaction chamber is kept at 1100℃, and the pressure is kept at 150 Torr. TMAl with a flow rate of 30 sccm and NH3 with a flow rate of 750 sccm are introduced, and hydrogen with a flow rate of 1500 sccm is used as the carrier gas to grow the AlN barrier layer, which forms a heterojunction with the GaN channel layer. A high-concentration, high-mobility two-dimensional electron gas (2DEG) is formed on the surface of the heterojunction.

[0038] Step 8: Using MOCVD, MBE, or HVPE processes, prepare an InN cap layer 7 on the AlN barrier layer 6, as shown in (7) of Figure 2. Taking MOCVD as an example, maintain the temperature of the reaction chamber at 550℃, and under the condition of maintaining a pressure of 80 Torr, introduce TMIn at a flow rate of 20 sccm and NH3 at a flow rate of 500 sccm, with hydrogen at a flow rate of 1000 sccm as the carrier gas to grow the InN cap layer;

[0039] Step 9: Using electron beam evaporation, source metal layer 8 and drain metal layer 9 are prepared on both sides of the upper surface of InN cap layer 7, respectively. Then, the source and drain contact electrodes of the device are formed by rapid thermal annealing in a nitrogen-filled environment. The annealing temperature is 900℃, as shown in (8) of Figure 2.

[0040] Step 10: Using electron beam evaporation, a gate metal layer 10 is prepared at the center of the upper surface of the InN cap layer 7. Then, the gate contact electrode is formed by rapid thermal annealing in an oxygen-filled environment. The annealing temperature is 600℃, and a nitride enhancement field-effect transistor based on the P buried layer is obtained, as shown in (9) of Figure 2.

[0041] Existing fabrication methods increase the distance between the gate and channel of field-effect transistors (FETs), weakening the electric field strength from the gate to the channel. This significantly reduces the device's gate control capability and compromises its performance. This invention provides a nitride-enhanced field-effect transistor (FET) based on a P-buried layer. This transistor has a P-GaN buried layer partially buried in the GaN buffer layer at the gate location to deplete a portion of the two-dimensional electron gas in the GaN channel layer. Compared to enhancement methods using a P-GaN cap layer, this arrangement shortens the distance between the gate and channel, further enhancing the gate-to-channel electric field strength and improving the device's gate control capability. Using AlN instead of AlGaN as the barrier layer to form an AlN / GaN heterojunction with the GaN channel layer allows for the generation of a higher density of two-dimensional electron gas due to AlN's stronger polarization. Furthermore, using an InN cap layer above the barrier layer utilizes the smaller work function difference between InN and the metal to achieve lower contact resistance, resulting in superior device performance and promising applications in power electronics, communications, and aerospace.

[0042] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A nitride enhancement-mode field-effect transistor based on a P-buried layer, characterized in that, include: The substrate layer (1), AlN nucleation layer (2), GaN buffer layer (3), GaN channel layer (5), AlN barrier layer (6), and InN cap layer (7) are stacked sequentially. The GaN buffer layer (3) has a groove, and a P-GaN buried layer (4) is formed at the bottom of the groove. The thickness of the P-GaN buried layer (4) is equal to the depth of the groove. The P-GaN buried layer (4) is used to locally deplete the two-dimensional electron gas in the GaN channel layer (5). The AlN barrier layer (6) and the GaN channel layer (5) constitute an AlN / GaN heterojunction. The thickness of the AlN barrier layer (6) ranges from 3 nm to 11 nm, and the AlN / GaN heterojunction is generated through higher polarization. A higher density of two-dimensional electron gas, while the P-GaN buried layer (4) depletes the two-dimensional electron gas in the GaN channel layer (5) corresponding to the position of the P-GaN buried layer (4) to shorten the distance between the gate and the channel and enhance the gate control electric field; the InN cap layer (7) is provided with a source metal layer (8), a drain metal layer (9) and a gate metal layer (10) at intervals, and the gate metal layer (10) is located between the source metal layer (8) and the drain metal layer (9); wherein, the InN cap layer (7) is used to reduce the contact resistance of the source metal layer (8) and the drain metal layer (9), and the InN cap layer (7) compensates for the ohmic contact fabrication problem of the AlN barrier layer (6) by its work function difference with the metal.

2. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The thickness of the GaN buffer layer (3) ranges from 1μm to 2μm, and the depth of the groove ranges from 60nm to 200nm.

3. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The P-GaN buried layer (4) is doped with Mg, and the doping concentration ranges from 1×10⁻⁶. 17 cm -3 ~5×10 20 cm -3 .

4. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The thickness of the GaN channel layer (5) ranges from 300nm to 800nm.

5. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The thickness of the InN cap layer (7) ranges from 1 nm to 5 nm.

6. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The thickness of the AlN nucleation layer (2) ranges from 20 nm to 100 nm.

7. The nitride enhancement-mode field-effect transistor based on a P-buried layer according to claim 1, characterized in that, The source metal layer (8) and the drain metal layer (9) are made of a stacked metal of Ti, Al, Ni and Au, and the gate metal layer (10) is made of a stacked metal of Ni and Au.

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