Automated repair solution for tsvs on stacked dies

Abstract

This document discloses an apparatus comprising: a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits associated with each of the pad electrodes; a second semiconductor chip having a plurality of TSVs, each electrically connected to an associated with each of the pad electrodes and a plurality of second latch circuits associated with each of the TSVs; and a training circuit configured to perform a training operation on a signal path including a selected from the pad electrodes and a selected from the TSVs. The training circuit is configured to activate a failure signal when the signal path is determined to be defective. The failure signal is stored in the selected from the first latch circuit and the selected from the second latch circuit.

Description

Background Technology

[0001] Semiconductor chips used in memory devices such as HBM (High Bandwidth Memory) typically include TSVs (Through Silicon Vias) configured to penetrate the semiconductor substrate. TSVs on each semiconductor chip are connected to TSVs on other semiconductor chips and positioned in the same planar location via microbumps and pad electrodes, thereby forming signal paths penetrating multiple semiconductor substrates. If a TSV is in a poorly conducting state or there is a poor connection at the junction between two TSVs, the associated signal path is defective and cannot be used. In this case, a backup signal path is used to replace the defective signal path to restore functionality. Checking each signal path and replacing it with a backup signal path is performed not only during the manufacturing stage but also during the initialization cycle after power-on in actual use.

[0002] However, if the circuitry required to check the signal path during the initialization cycle is large, or if a large number of additional TSVs are needed, then the chip size will increase. Attached Figure Description

[0003] Figure 1 This is a schematic diagram illustrating the configuration of a semiconductor device according to the present disclosure.

[0004] Figure 2 This is a schematic diagram used to explain the state of the domino switch circuit in each of the chips where failure information is loaded.

[0005] Figure 3A This is a schematic diagram used to explain the connection relationship when the replacement via the domino switch circuit is not performed.

[0006] Figure 3B This is a schematic diagram used to explain the connection relationships when performing a replacement through a domino switch circuit.

[0007] Figure 4 This is a block diagram used to explain the configuration of the automatic repair circuit.

[0008] Figure 5 It is a schematic floor plan showing the layout of TSVs in the TSV area.

[0009] Figure 6 It is a circuit diagram of the selection circuit contained in the memory core chip.

[0010] Figure 7 This is a circuit diagram of the selection circuit included in the interface chip.

[0011] Figure 8 This is a diagram used to explain the grouping in the TSV area.

[0012] Figure 9 This is a flowchart used to explain the automatic repair operation.

[0013] Figure 10 It is a waveform diagram of each signal during the automatic repair operation and shows the waveform when the corresponding signal path does not contain defects.

[0014] Figure 11 It is a waveform diagram of each signal during the automatic repair operation and shows waveforms in some cases where defects are present in the signal path. Summary of the Invention

[0015] An apparatus and method for automatic repair of TSVs on stacked dies are disclosed. In one aspect of this disclosure, an apparatus includes a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to associated persons in the pad electrodes. The apparatus includes a second semiconductor chip having a plurality of TSVs each electrically connected to associated persons in the pad electrodes and a plurality of second latch circuits assigned to associated persons in the TSVs, and includes a clock generation circuit formed on the first semiconductor chip and configured to generate a clock signal. The apparatus further includes: a first selection circuit formed on the first semiconductor chip and configured to update a first selection signal based on the clock signal; and a second selection circuit formed on the second semiconductor chip and configured to update a second selection signal based on the clock signal. A training circuit included in the apparatus is configured to perform a training operation on a signal path including selected persons in the pad electrodes and selected persons in the TSVs. The first selection signal selects one of the pad electrodes and one of the first latch circuits. The second selection signal selects one of the TSVs and one of the second latch circuits. The training circuit is configured to activate a failure signal when the signal path is determined to be defective. The failure signal is stored in the selector in the first latch circuit and the selector in the second latch circuit.

[0016] In another aspect of this disclosure, an apparatus includes a first semiconductor chip comprising a plurality of pad electrodes, a plurality of first latch circuits assigned to associated persons in the pad electrodes, a non-volatile memory circuit storing primary repair data, and a repair circuit. The apparatus further includes a second semiconductor chip comprising a plurality of TSVs and a plurality of second latch circuits assigned to associated persons in the TSVs. Each of the TSVs is electrically connected to an associated person in the pad electrodes to form a plurality of signal paths. One or more of the signal paths in which the corresponding first and second latch circuits store a failure signal are invalid. The repair circuit is configured to perform a primary repair operation and a secondary repair operation in this order. The primary repair operation includes reading the primary repair data from the non-volatile memory circuit and writing the failure signal to one or more of the first and second latch circuits corresponding to a defective one or more of the signal paths indicated by the primary repair data. The secondary repair operation includes testing the signal path and writing the failure signal to one or more of the first and second latch circuits corresponding to the defective one or more of the signal path detected by the test. The test and the write are performed alternately in the secondary repair operation.

[0017] In another aspect of this disclosure, an apparatus includes a first semiconductor chip having a plurality of TSVs arranged along row and column directions and a plurality of latch circuits corresponding to the plurality of TSVs, and further including a second semiconductor chip stacked on the first semiconductor chip. The second semiconductor chip has control circuitry and a plurality of pads correspondingly coupled to the plurality of TSVs. The control circuitry is configured to generate row selection signals and column selection signals to select one of the plurality of TSVs arranged at an intersection point determined by the row selection signals and column selection signals, and to transmit control signals, in addition to the row selection signals and column selection signals, to the plurality of latch circuits such that the control signals are stored in one of the plurality of latch circuits selected by the row selection signals and column selection signals. Detailed Implementation

[0018] Various embodiments of the invention will now be explained in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate, by way of illustration, specific aspects and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0019] Figure 1 The semiconductor device shown is an HBM with a structure in which eight memory core chips 20 to 27 are stacked one on top of the other on an interface chip 10. However, the subject matter of the present invention is not limited to HBMs. The memory core chips 20 to 27 are semiconductor chips, each of which integrates a memory core containing an array of memory cells. The interface chip 10 is a semiconductor chip that controls the memory core chips 20 to 27. Each of the interface chip 10 and the memory core chips 20 to 26 includes a plurality of TSVs 30, which are arranged to penetrate the corresponding semiconductor substrate. The interface chip 10 and the memory core chips 20 to 27 are all stacked in a downward manner, that is, with the main surface on which transistors and wiring patterns (not shown) are formed facing down. Therefore, the memory core chip 27 located on the top layer does not require TSVs 30. However, the memory core chip 27 located on the top layer may include TSVs 30. Most of the TSVs 30 disposed on the memory core chips 20 to 26 are respectively connected to the front TSV pads 31A located at the same planar position. Conversely, most of the TSVs 30 and the front TSV pads 31A on the interface chip 10 are located at different planar positions. The TSVs 30 located at the same planar position on the interface chip 10 and memory chips 20 to 26 are cascaded via the front TSV pad 31A, TSV bump 31B, and rear TSV pad 31C, forming multiple signal paths 32. Commands and write data output from the interface chip 10 are supplied to memory core chips 20 to 27 via signal paths 32. Read data output from memory core chips 20 to 27 is supplied to the interface chip 10 via signal paths 32. External terminals 33 are provided on the interface chip 10, and signals are transmitted / received to / from external circuits via external terminals 33.

[0020] Some of the signal paths in signal path 32 are backup signal paths. When a signal path 32 is defective, a backup signal path is used. For example... Figure 1 As shown, latch circuits L are assigned to TSVs respectively, and failure information is stored in the latch circuit L corresponding to the TSV 30 in the defect signal path 32.

[0021] When the failure information is stored in the latch circuit L, the connection between the internal circuit of the switching interface chip 10 and the internal circuit of the memory core chips 20 to 27 and the TSV 30 is changed, so that the backup signal path is used instead of the defective signal path. Figure 2The diagram shows that a domino switch circuit 42 is provided in each of the interface chip 10 and the memory core chips 20 to 27. The domino switch circuit 42 is a circuit used to switch the connection relationship between the internal circuitry of the interface chip 10 and the internal circuitry of the memory core chips 20 to 27, and switches the TSV 30 and the connection relationship between the internal circuitry of the interface chip 10 and the internal circuitry of the memory core chips 20 to 27 and the TSV 30 based on failure information stored in the latch circuit L. The failure information is first read from the antifuse circuit 40 during the initialization cycle after power-on and then loaded into the latch circuit L of the interface chip 10 and the memory core chips 20 to 27. The transmission of the failure information is performed via the TSV 30F for failure information transmission. The failure information is written to the antifuse circuit 40 based on the results of screening tests performed during the manufacturing stage.

[0022] As in Figure 3A As shown, each of the domino switch circuits 42 is connected between multiple input / output nodes of the internal circuit 46 and multiple TSVs 30. Figure 3A In the example shown, internal circuitry 46 has eight input / output nodes N0 to N7, and correspondingly assigns nine TSVs 50 to 58 to them. Of these TSVs, eight TSVs 50 to 57 are the original TSVs, and one TSV 58 is a spare TSV. The corresponding latch circuits L0 to L7 are assigned to TSVs 50 to 57 respectively. Figure 3A In the example shown, failure information is not stored in latch circuits L0 to L7. In this case, domino switch circuit 42 connects input / output nodes N0 to N7 to TSVs 50 to 57, respectively. Therefore, spare TSV 58 is not used in this case. Conversely, when failure information is stored, for example as... Figure 3B In the latch circuit L3 shown, the domino switch circuit 42 connects the input / output nodes N0 to N7 with TSVs 50 to 52 and 54 to 58, respectively. This invalidates TSV 53 corresponding to latch circuit L3. In this way, the domino switch circuit 42 achieves fault recovery by changing the connection relationship between the input / output nodes N0 to N7 and TSVs 50 to 58, rather than simply replacing the TSV to which the fault information was assigned with a spare TSV.

[0023] According to this disclosure, the semiconductor device performs an automatic repair operation after loading failure information read from the antifuse circuit 40 during the initialization cycle following power-on activation into the latch circuit L of the interface chip 10 and memory core chips 20 to 27. The automatic repair operation is a training operation used to test the corresponding connection state of the signal path 32 and overwrite the failure information to the latch circuit L based on the test results. Defects on the signal path are discovered during screening tests performed during the manufacturing stage, and failure information is written to the antifuse circuit 40 based on the defects. Therefore, the defective signal path is replaced with a backup signal path. However, in rare cases, a new defective signal path may appear due to changes in time after shipment. The operation of finding this subsequently appearing defect and replacing the defective signal path with a backup signal path is the automatic repair operation. Therefore, the automatic repair operation needs to be completed during the initialization cycle following power-on activation, thus the time available to allocate a signal path 32 is very short. In this embodiment, the automatic repair circuit is integrated into the interface chip 10 and memory core chips 20 to 27 to automatically perform the automatic repair operation without requiring external controller control.

[0024] As in Figure 4 As shown, the automatic repair circuit is disposed in interface chip 10 and memory core chips 20 to 27. Interface chip 10 includes a clock control circuit 60, an X address control circuit 61, an X shift register 62, a Y address control circuit 63, a Y shift register 64, and a test control circuit 65. Each of memory core chips 20 to 27 includes a clock control circuit 70, an X address control circuit 71, an X shift register 72, a Y address control circuit 73, a Y shift register 74, and a test control circuit 75. The aforementioned circuits 60 to 65 in interface chip 10 and the aforementioned circuits 70 to 75 in each of memory core chips 20 to 27 have the same circuit configuration. Interface chip 10 further includes a clock generation circuit 66, a comparator 67, and an address register 68. The clock generation circuit 66 includes an oscillator and automatically generates a test clock signal CLK. The test clock signal CLK is supplied to the clock control circuit 60 included in the interface chip 10, and also to the clock control circuit 70 included in each of the memory core chips 20 to 27. The clock control circuit 60 controls the timing of the X address control circuit 61, the Y address control circuit 63, the test control circuit 65, and the address register 68. The clock control circuit 70 controls the timing of the X address control circuit 71, the Y address control circuit 73, and the test control circuit 75. Automatic repair operations can also be performed by inputting the test mode signal TM to these circuits 61, 63, 65, 71, 73, and 75.

[0025] Comparator 67 is a circuit that compares the potential of the selected signal path 32 with a reference potential Vref. Comparator 67 compares the potential of the selected signal path 32 with the reference potential Vref in the timing sequence of activating the comparison signal COMP, and generates an output signal OUT based on the comparison result. The output signal OUT is supplied to address register 68. Address register 68 generates a failure signal FAIL based on the output signal OUT. The failure signal FAIL is supplied to TSV regions 36 and 38. Address register 68 further stores the address of the defective signal path 32, thereby also performing a determination operation to determine whether the defective signal path 32 can be recovered via a backup signal path when the failure signal FAIL is subsequently activated. The address stored in address register 68 can be read externally through test mode operation.

[0026] The TSVs 30 located on interface chip 10 are arranged in an array within TSV region 36. Any one of the TSVs 30 arranged in the array within TSV region 36 can be selected using the TSV selection signal Xsel output from X shift register 62 and the TSV selection signal Ysel output from Y shift register 64. Similarly, the TSVs 30 located on each of memory core chips 20 to 27 are arranged in an array within TSV region 38. Any one of the TSVs arranged in the array within TSV region 38 can be selected using the TSV selection signal Xsel output from X shift register 72 and the TSV selection signal Ysel output from Y shift register 74.

[0027] like Figure 5 As shown, TSV 30s are arranged in a matrix in TSV regions 36 and 38. Selection circuitry 80 is assigned to each of the TSV 30s. Selection circuitry 80 is used for checking signal path 32, which is performed during the manufacturing phase and during the initialization cycle after power-on activation. (See also...) Figure 5As shown, the corresponding selection signal lines Y0, Y1, Y2, Y3, ... are assigned to multiple TSVs 30 arranged in the x-direction, and the corresponding selection signal lines X0, X1, X2, X3, ... are assigned to multiple TSVs 30 arranged in the y-direction. Selection signal lines Y0, Y1, Y2, Y3, ... supply TSV selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... to their corresponding counterparts in the selection circuit 80. Selection signal lines X0, X1, X2, X3, ... supply TSV selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... to their corresponding counterparts in the selection circuit 80. Y-shift registers 64 and 74 activate any one of the TSV selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... and deactivate all other TSV selection signals. X shift registers 62 and 72 activate any one of the TSV selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... and deactivate all other TSV selection signals. Therefore, any one of the selection circuits 80 is activated, and the corresponding TSV 30 is selected.

[0028] Each of the selection circuits 80 included in the memory core chips 20 to 27 includes a P-channel MOS transistor 81, a NAND gate circuit 82 controlling the transistor 81, and an AND gate circuit 83 controlling the corresponding latch circuit L included in the domino switch circuit 42, such as Figure 6 The NAND gate circuit 82 receives the corresponding TSV selection signals Xsel0, Xsel1, Xsel2, Xsel3, ..., the corresponding TSV selection signals Ysel0, Ysel1, Ysel2, Ysel3, ..., and the memory core selection signals Csel0, Csel1, Csel2, Csel3, ... used to select one of the memory core chips 20 to 27. When all these selection signals are at the active level (high level), the TSV selection signal XYselF is activated to a low level. In memory core chips 20 to 27, P-channel MOS transistors 84 and 81 are connected in series between the power supply VDD and TSV 30. The gate electrode of transistor 84 is supplied with a test signal TESTF. The test signal TESTF is activated during automatic repair operation. Therefore, when both the test signal TESTF and the TSV selection signal XYselF are activated to a low level, the associated signal in TSV 30 is connected to the power supply VDD. For example, when both the test signal TESTF and the TSV selection signal XYselF are activated, in this case, the power supply VDD is the power supply on the high potential side, and the associated signal path 32 is charged via TSV 30.

[0029] AND gate 83 receives the corresponding TSV selection signals Xsel0, Xsel1, Xsel2, Xsel3, ..., the corresponding TSV selection signals Ysel0, Ysel1, Ysel2, Ysel3, ..., and the failure signal FAIL, and activates flag F to a high level when all these signals are at the active level (high level). Flag F is supplied to domino switch circuit 42, and the failure information is correspondingly written to one of the latch circuits L corresponding to the associated TSV 30.

[0030] The selection circuit 80 included in the interface chip 10 has the same circuit configuration as the selection circuit 80 in the memory core chips 20 to 27, as shown in Figure 7 The only difference is that the interface chip select signal IFsel is used instead of the memory core select signals Csel0, Csel1, Csel2, Csel3, ... . In the interface chip 10, transistor 81 and N-channel MOS transistor 88 are connected in series between TSV 30 and power supply VSS. The gate electrode of transistor 88 is supplied with the test clock signal CLK. Therefore, when the test clock signal CLK is activated to a high level and the TSV select signal XYselF is activated to a low level, the associated signal in TSV 30 is connected to the power supply VSS. For example, when both the test clock signal CLK and the select signal XYselF are activated, in this case, the power supply VSS is the power supply on the low potential side, and the associated signal path 32 is discharged via TSV 30.

[0031] As shown in Figures 6 and 7, the domino switch circuit 42 is connected between the internal circuit 46 contained in the interface chip 10 or memory core chips 20 to 27 and the TSV 30. (Reference) Figure 3A and 3B Explain the function of the domino switch circuit 42. When a failure message is written to one of the latch circuits L, it invalidates one of the corresponding TSVs 30 and instead enables the backup TSV (e.g., Figure 3A and 3B The TSV 58 shown in the document is valid.

[0032] As in Figure 8As shown, the regular TSVs 30 located in TSV regions 36 and 38 are divided into multiple groups G1, G2, ..., and one or more spare TSVs 30R are assigned to each group. Therefore, the number of recoverable TSVs 30 in each group is limited to the number of spare TSVs 30R included in the relevant group. When a FAIL signal is generated, address register 68 stores the address of the corresponding signal path 32 to determine whether signal path 32 can be recovered via a spare signal path when the FAIL signal is subsequently activated. When the determination indicates that signal path 32 cannot be recovered, that is, when there is no spare TSV 30R belonging to the associated group, the FAIL signal is not activated.

[0033] The automatic repair operation will be explained next. For example, in... Figure 9 As shown in the diagram, when the device is powered on and the reset signal PowerUpRst is activated (step S1), from... Figure 2 The antifuse circuit 40 shown reads the failure information (step S2) and loads it into the domino switch circuit 42 contained in the interface chip 10 and memory core chips 20 to 27. Therefore, the failure information is written into several of the latch circuits L corresponding to the defect signal path 32 (step S3), invalidating several of the corresponding TSVs 30 and enabling the spare TSV 30R. This operation is called "hard repair". When the hard repair is complete (yes at step S4), the automatic repair operation begins (step S5). When the automatic repair operation begins, the clock control circuits 60 and 70 are activated. Therefore, the X shift registers 62 and 72 sequentially activate the TSV selection signal Xsel in sync with the test clock signal CLK, and the Y shift registers 64 and 74 sequentially activate the TSV selection signal Ysel in sync with the test clock signal CLK (step S6). At this time, the X shift register 62 included in interface chip 10 and the X shift register 72 included in memory core chips 20 to 27 respectively activate the same TSV selection signal Xsel, and the Y shift register 64 included in interface chip 10 and the Y shift register 74 included in memory core chips 20 to 27 respectively activate the same TSV selection signal Ysel. That is, interface chip 10 and memory core chips 20 to 27 respectively perform the same operation, thereby sequentially testing signal path 32 (step S8). When the test result determines that signal path 32 is defective (no at step S8), the failure signal FAIL is activated and latched into the corresponding one in latch circuit L (step S9). Figure 9In the example shown, at step S8, it is confirmed that the resistance value of signal path 32 is less than 3K ohms. However, the value to be compared is not limited to 3K ohms and can be other values. However, for signal path 32 that has already been replaced based on the failure information from the antifuse circuit 40 (yes at step S7), the failure signal FAIL is activated regardless of the test result (step S9). Then, it is determined whether the signal path 32 to be tested is the last signal path (step S10). When signal path 32 is not the last signal path (no at step S10), the TSV selection signals Xsel and Ysel are incremented (step S11). On the other hand, when the signal path 32 to be tested is the last signal path (yes at step S10), the automatic repair operation ends (step S12).

[0034] refer to Figure 10 and 11 Explain the waveforms of the signals during the automatic repair operation. Figure 10 The waveform of signal path 32 is shown when there are no defects. Figure 11 The waveforms in signal path 32 with defects are shown. First, the TSV selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... are selected from any one of the TSV selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... Figure 10 and 11 In the example shown, the selection signal Xsel0 is sequentially activated to a high level while in a state where it is already high. Therefore, as... Figure 5 As shown in the diagram, multiple TSVs 30 arranged in a matrix are sequentially selected, and the associated signal path 32 is charged via the selected TSV 30. It is sufficient to perform the charging of signal path 32 in any of the memory core chips 20 to 27, and it is not necessary to perform the charging in the other memory core chips. Preferably, the charging of signal path 32 is performed in the top-level memory core chip 27. In this case, it is sufficient to activate the memory core selection signal Csel corresponding to the top-level memory core chip 27 while keeping the memory core selection signals Csel corresponding to the other memory core chips 20 to 26 in an inactive state.

[0035] As in Figure 10 and 11As shown, one cycle of the test clock signal CLK equals the activation cycle of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... Therefore, transistor 88 is turned on during the first half of the cycle of one of the selected signal paths 32, causing the selected signal path 32 to discharge, and node A in interface chip 10 becomes VSS level. Simultaneously, transistor 88 is turned off during the second half of the cycle of one of the selected signal paths 32, stopping the discharge of the selected signal path 32. When the discharge of signal path 32 stops, signal path 32 selected via transistor 81 is charged, and thus the level of node A in interface chip 10 increases. At this time, the rate of increase of the level of node A depends on the resistance value and parasitic capacitance of signal path 32. Figure 10 The waveform shown illustrates a scenario where signal path 32 is defect-free and the level of node A immediately exceeds the reference potential Vref after the test clock signal CLK changes low. The comparator signal COMP is activated at a specific timing before the test clock signal CLK changes high again after having already changed low. When comparator COMP is activated, comparator 67 compares the level of node A with the reference potential Vref and sets the output signal OUT high when the level of node A is higher. This means that signal path 32 is defect-free, for example, with a resistance value below 3K ohms. In this case, the failure signal FAIL remains inactive. Figure 6 and 7 In the circuit example shown, node A is charged to VDD and then discharged to VSS, and its level is compared with a reference potential Vref in this state. However, node A can be discharged to VSS and then charged to VDD, and its level can be compared with a reference potential Vref in this state. In this case, the signal indicating the inversion of the comparison result is used as the output signal OUT.

[0036] at the same time, Figure 11The waveforms corresponding to defects in signal path 32, which corresponds to selection signals Xsel0 and Ysel2, are shown. When signal path 32 contains defects, the resistance increases and the charging rate of signal path 32 decreases. It can be assumed that signal path 32 is defective if the resistance of the associated TSV 30 itself increases, or if the resistance increases due to defects at the connection points via the front TSV pad 31A, TSV bump 31B, and rear TSV pad 31C. When the resistance of signal path 32 is high, the increase in the level of associated node A slows down during the activation of the comparator signal COMP, and the level of node A becomes lower than the reference potential Vref. Therefore, comparator 67 switches the output signal OUT low. This means that signal path 32 contains defects, such as a resistance equal to or greater than 3K ohms, and in this case, the failure signal FAIL is activated.

[0037] like Figure 4 As shown, the FAIL signal is supplied to the TSV regions 36 and 38 of the interface chip 10 and the memory core chips 20 to 27. That is, the FAIL signal is supplied to all selection circuits 80. However, a flag F is activated based on the FAIL signal only in some of the selected selection circuits 80 that are in a selected state, and the flag F is not activated in other selection circuits 80 even when the FAIL signal is activated. Therefore, only the flag F corresponding to the signal path 32 under test is activated, and the failure information is written to the corresponding one in the latch circuit L contained in the domino switch circuit 42. As described above, when the failure information is written to the latch circuit L, the associated signal path 32 is invalidated and replaced with an alternative signal path.

[0038] As described above, in the semiconductor device according to this disclosure, an automatic repair operation is performed during the initialization cycle after power activation. Therefore, signal paths that subsequently become defective due to time changes are invalidated, and backup signal paths are made valid to recover from the defects. Furthermore, the TSV selection signals Xsel and Ysel used in the automatic repair operation are automatically generated within the interface chip 10 and memory core chips 20 to 27. Therefore, it is not necessary to provide TSVs for transmitting the TSV selection signals Xsel and Ysel. Moreover, because the determination operation using comparator 67 and the transmission operation of the failure signal FAIL are performed alternately, by supplying a single bit of the failure signal FAIL to all selection circuits 80 in the interface chip 10 and memory core chips 20 to 27, failure information can be selectively written to a predetermined location in the latch circuit L.

[0039] The automated repair operation described above can also be performed during screening tests conducted at the manufacturing stage. For example, the effectiveness of the automated repair operation can be tested by performing the automated repair operation after specifying the defect signal path 32 based on the results of the screening test and before writing the failure information to the antifuse circuit 40.

[0040] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of the invention, as well as obvious modifications and equivalents thereof. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor apparatus comprising: a first semiconductor chip having a plurality of pad electrodes and a plurality of first latch circuits assigned to associated ones of the pad electrodes; a second semiconductor chip having a plurality of TSVs each electrically connected to an associated one of the pad electrodes and a plurality of second latch circuits assigned to associated ones of the TSVs; a clock generation circuit formed on the first semiconductor chip and configured to generate a clock signal; a first selection circuit formed on the first semiconductor chip and configured to update a first selection signal based on the clock signal, wherein the first selection signal selects one of the pad electrodes and one of the first latch circuits; a second selection circuit formed on the second semiconductor chip and configured to update a second selection signal based on the clock signal, wherein the second selection signal selects one of the TSVs and one of the second latch circuits; and a training circuit configured to perform a training operation on a signal path including a selected one of the pad electrodes and a selected one of the TSVs, wherein the training circuit is configured to activate a fail signal when the signal path is determined to be defective, and wherein the fail signal is stored in the selected one of the first latch circuits and the selected one of the second latch circuits.

2. The semiconductor apparatus of claim 1, wherein the first and second selection circuits are configured to update the first and second selection signals each time the clock signal changes from a first logic level to a second logic level so as to keep the first and second selection signals to the same value.

3. The semiconductor apparatus of claim 2, wherein the training circuit includes: a first circuit formed on the first semiconductor chip and configured to apply a first potential when the clock signal is at the second logic level; a second circuit formed on the second semiconductor chip and configured to apply a second potential different from the first potential when the clock signal is at the first logic level; and a third circuit formed on the first semiconductor chip and configured to detect a potential of the signal path at a predetermined timing during a period when the clock signal is at the first logic level.

4. The semiconductor apparatus of claim 3, wherein the third circuit is configured to activate the fail signal when the potential of the signal path does not reach a reference potential.

5. The semiconductor apparatus of claim 4, wherein the fail signal is transferred to the first and second latch circuits before the clock signal changes from the first logic level to the second logic level.

6. The semiconductor apparatus of claim 1, wherein the signal path is invalidated when the first latch circuit assigned to the selected one of the pad electrodes and the second latch circuit assigned to the selected one of the TSVs store the fail signal.

7. The semiconductor apparatus of claim 6, ​ ​ wherein the first semiconductor chip further has a spare pad electrode, wherein the second semiconductor chip further has a spare TSV, and wherein a spare signal path comprising the spare pad electrode and the spare TSV is enabled to replace the signal path determined to be defective.

8. The semiconductor apparatus of claim 3, further comprising a plurality of third semiconductor chips arranged between the first semiconductor chip and the second semiconductor chip, wherein each of the third semiconductor chips has substantially the same circuit configuration as the second semiconductor chip.

9. A semiconductor apparatus, comprising: a first semiconductor chip including a plurality of pad electrodes, a plurality of first latch circuits assigned to associated ones of the pad electrodes, a non-volatile memory circuit storing primary repair data, and a repair circuit; and a second semiconductor chip including a plurality of TSVs and a plurality of second latch circuits assigned to associated ones of the TSVs, wherein each of the TSVs is electrically connected to an associated one of the pad electrodes to form a plurality of signal paths, wherein one or several of the signal paths for which the corresponding first and second latch circuits store a fail signal are inactive, wherein the repair circuit is configured to perform a primary repair operation and a secondary repair operation in this order, wherein the primary repair operation includes reading the primary repair data from the non-volatile memory circuit and writing the fail signal to one or several of the first and second latch circuits corresponding to a defective one or several of the signal paths indicated by the primary repair data, wherein the secondary repair operation includes testing the signal paths and writing the fail signal to another one or several of the first and second latch circuits corresponding to another defective one or several of the signal paths detected by the testing, and wherein the testing and the writing in the secondary repair operation are performed alternately.

10. The semiconductor apparatus of claim 9, wherein the repair circuit is configured to perform the primary repair operation and the secondary repair operation every time a power source is activated.

11. The semiconductor apparatus of claim 9, wherein the repair circuit includes a clock generation circuit configured to generate a clock signal, and wherein the testing and the writing in the secondary repair operation corresponding to each of the signal paths are performed within one clock cycle.

12. The semiconductor apparatus of claim 11, wherein the first semiconductor chip further includes a discharge circuit configured to discharge selected ones of the signal paths by the repair circuit, wherein the second semiconductor chip further includes a charge circuit configured to charge the selected ones of the signal paths by the repair circuit, wherein the selected ones of the signal paths are discharged in a first half of the clock cycle and charged in a second half of the clock cycle, and wherein the clock generation circuit is configured to generate the clock signal in the first half of the clock cycle and in the second half of the clock cycle. wherein the test in the secondary repair operation is performed by detecting a potential of the selected one of the signal paths at a predetermined timing during the latter half of the clock cycle.

13. The semiconductor apparatus of claim 12, wherein the write in the secondary repair operation is performed by transmitting the fail signal to the first and second latch circuits during the latter half of the clock cycle.

14. The semiconductor apparatus of claim 13, wherein the fail signal is commonly supplied to the first latch circuit and the second latch circuit and stored in a selected one of the first latch circuit and a selected one of the second latch circuit.

15. The semiconductor apparatus of claim 9, further comprising a plurality of third semiconductor chips arranged between the first semiconductor chip and the second semiconductor chip, wherein each of the third semiconductor chips includes a plurality of TSVs each electrically connected to an associated one of the plurality of TSVs of the first semiconductor chip and a plurality of third latch circuits assigned to an associated one of the TSVs, and wherein each of the pad electrodes is electrically connected to an associated one of the TSVs of the second semiconductor chip and to an associated one of the TSVs of each of the third semiconductor chips to form the plurality of signal paths.

16. The semiconductor apparatus of claim 15, wherein the write in the primary repair operation is performed by writing the fail signal to one or ones of the first to third latch circuits corresponding to the defective one or ones of the signal paths indicated by the primary repair data, and wherein the write in the secondary repair operation is performed by writing the fail signal to another one or other ones of the first to third latch circuits corresponding to the defective another one or other ones of the signal paths detected by the test.

17. A semiconductor apparatus comprising: a first semiconductor chip having a plurality of TSVs arranged along row and column directions and a plurality of latch circuits disposed corresponding to the plurality of TSVs; and a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a control circuit and a plurality of pads coupled corresponding to the plurality of TSVs, wherein the control circuit is configured to: generate a row select signal and a column select signal to select one of the plurality of TSVs arranged at an intersection point determined by the row select signal and the column select signal; and commonly transmit a control signal to the plurality of latch circuits in addition to the row select signal and the column select signal such that the control signal is stored in one of the plurality of latch circuits selected by the row select signal and the column select signal.

18. The semiconductor apparatus of claim 17, wherein the control circuit is configured to activate the control signal when a selected one of the plurality of TSVs is determined to be defective.

19. The semiconductor apparatus of claim 18, wherein the first semiconductor chip further has clock generation circuitry configured to generate a clock signal, and wherein the control circuitry is configured to update the row select signal and the column select signal based on the clock signal.

20. The semiconductor apparatus of claim 19, wherein the control circuitry is configured to: update the column select signal while the row select signal is fixed to a first value each time the clock signal is activated during a first cycle; and update the column select signal while the row select signal is fixed to a second value each time the clock signal is activated during a second cycle after the first cycle.

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