Timing control circuit
By designing a timing control circuit of multiple transmission paths in the power management chip, using the combination of flip-flops and set/reset modules, the accuracy and resource waste of power-on and power-off timing control are solved, and high integration is achieved and low power consumption power management.
Patent Information
- Application Number
- CN202011169286.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-28
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2040-10-28
AI Technical Summary
When designing power management chips in the prior art, it is difficult to effectively control the power-on and power-down timing, resulting in high power consumption, waste of resources and chip damage. Especially in high-speed integrated circuits, traditional functional module ports realize power logic. It occupies a large area and lacks hysteresis function.
Design a timing control circuit, through at least three transmission paths, each transmission path includes a flip-flop, a set module and a reset module, and controls timing power-up and power-down with enable signals, and realizes setting through inverters and delay units. The delay processing of bits and reset signals ensures the accuracy and stability of the timing signal.
It effectively reduces the area of the sequencing control circuit in the chip, improves integration and functionality, ensures the accuracy of power-on and power-off timing, reduces current impact, and enhances the stability and resource utilization efficiency of the chip.
Smart Images
Figure CN114430265B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of integrated circuit design, and in particular to a timing control circuit for realizing power-on reset and power-off reset. Background Art
[0002] In the design of electronic products, high-speed integrated circuits and chips are used more and more widely. The processors of these integrated circuits, such as ARM, DSP, FPGA, etc., are running faster and faster, and the power consumed under the same process conditions is also increasing. In order to reduce power consumption, these processors will use several different power supply voltages. The core with a relatively high clock frequency uses a low voltage power supply, and the peripheral interface with a relatively low clock frequency uses a high voltage power supply. In order to ensure the safety of the internal circuits of the processor, more and more requirements are placed on the power-on timing and power-off timing of the power supply. The power-on timing is easy to achieve. By controlling the IC, after power is turned on, the power-on sequence is realized by giving enable signals to each power supply in turn. However, the power-off timing must consider multiple operations. Normally, each power supply is disconnected in the power-off sequence first, and then the main power supply is turned off. However, in actual operation, abnormal power off also occurs. For example, if the main power supply is directly disconnected without soft power off first, the system is abnormally shut down. For high-speed integrated circuits that are sensitive to power-off timing, a large current shock will be caused and the circuit will be damaged.
[0003] At present, when designing power management chips, in order to ensure the accuracy of the chip system power-on timing, most of them will design a special enable circuit for it. According to the different designs of the system circuit or the differences in the application environment, the order of power-on and enable power-on is not the same. Among them, the most widely used enable power-on is directly obtained by using the voltage division of the power supply. The advantage is that it can avoid adding an external power supply, but when the power supply voltage input range is wide, the voltage division may no longer be applicable; secondly, many enable circuits do not have hysteresis function or the hysteresis is not controlled, which may cause enable oscillation near the threshold and damage the chip.
[0004] Furthermore, as chip functions become more complex, integration becomes higher, and size becomes smaller, the implementation of special logic for powering on or off in sequence is generally done by digital programming of traditional functional module ports, which takes up a large area and causes unnecessary waste of resources. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides a timing control circuit, which can effectively reduce the occupied area of the circuit in the chip while realizing the timing control of power-on reset and power-off reset.
[0006] A timing control circuit provided by the present invention has at least two transmission paths, wherein the at least two transmission paths include:
[0007] The first transmission path includes:
[0008] A first trigger, used for providing a first timing signal;
[0009] A first setting module, whose output end is connected to the setting end of the first trigger, and has a first input end for receiving an enable signal and a second input end for receiving a flip signal of the aforementioned first timing signal;
[0010] A first reset module, whose output end is connected to the reset end of the first trigger, and has a third input end for receiving the second timing signal and a fourth input end for receiving the flip signal of the first timing signal;
[0011] The second transmission path includes:
[0012] A second trigger, used for providing the aforementioned second timing signal;
[0013] A second setting module, the output end of which is connected to the setting end of the second trigger, and has a fifth input end for receiving the first timing signal and a sixth input end for receiving a flip signal of the second timing signal;
[0014] A second reset module, the output end of which is connected to the reset end of the second trigger, and has a seventh input end for receiving the third timing signal and an eighth input end for receiving a flip signal of the aforementioned second timing signal;
[0015] The third transmission path includes:
[0016] A third trigger, used for providing the aforementioned third timing signal;
[0017] A third setting module, the output end of which is connected to the setting end of the third trigger, and has a ninth input end for receiving the second timing signal and a tenth input end for receiving a flip signal of the third timing signal;
[0018] A third reset module, the output end of which is connected to the reset end of the third trigger, and has an eleventh input end for receiving the flip signal of the aforementioned enable signal and a twelfth input end for receiving the flip signal of the aforementioned third timing signal;
[0019] The timing control circuit controls the at least two transmission paths to perform timing power-up and timing power-down according to the aforementioned enable signal.
[0020] Preferably, the first transmission path further includes:
[0021] The first inverter has an input terminal connected to the output terminal of the first trigger and is used to provide a flip signal of the first timing signal.
[0022] Preferably, the second transmission path further includes:
[0023] The second inverter has an input terminal connected to the output terminal of the second trigger and is used to provide a flip signal of the second timing signal.
[0024] Preferably, the third transmission path further includes:
[0025] The third inverter has an input terminal connected to the output terminal of the third trigger and is used to provide a flip signal of the third timing signal.
[0026] Preferably, the first setting module comprises:
[0027] A first NAND gate, the input terminals of which are respectively connected to the aforementioned enable signal and the flip signal of the aforementioned first timing signal;
[0028] A first NOR gate, whose input end is connected to the output end of the first NAND gate, and generates a first level signal according to a logic judgment result of the output signal of the first NAND gate and a power-on reset signal;
[0029] A fourth trigger, wherein the reset terminal is connected to the first clock signal, the set terminal is connected to the output terminal of the first NOR gate, and is connected to the first level signal;
[0030] The first delay unit is connected between the fourth trigger and the first trigger, and is used to provide a first set signal for the first trigger, and to perform delay processing on the first trigger according to the output result of the fourth trigger.
[0031] Preferably, the first reset module comprises:
[0032] A fifth flip-flop, wherein a set terminal is connected to the output terminal of the aforementioned second flip-flop, a first reset terminal is connected to the output terminal of the aforementioned first inverter, and a second reset terminal is connected to the aforementioned power-on reset signal;
[0033] a fourth inverter, whose input end is connected to the output end of the fifth trigger, so as to obtain a flip signal of the output result of the fifth trigger;
[0034] A second NAND gate, whose input terminals are respectively connected to the output result of the fourth inverter and the aforementioned enable signal;
[0035] A sixth flip-flop, wherein the reset terminal is connected to the second clock signal, and the set terminal is connected to the output terminal of the second NAND gate;
[0036] The second delay unit is connected between the first trigger and the sixth trigger, and is used for providing a first reset signal for the first trigger, and performing delay processing on the first trigger according to an output result of the sixth trigger.
[0037] Preferably, the first delay unit and / or the second delay unit is a delay module composed of a plurality of inverters cascaded.
[0038] Preferably, the first delay unit is a first delay module composed of a plurality of inverters cascaded.
[0039] Furthermore, the second delay unit comprises:
[0040] A second delay module composed of a plurality of cascaded inverters;
[0041] a third delay module composed of a plurality of cascaded inverters, wherein the delay times of the second delay module and the third delay module are different, and
[0042] The selection switch is connected to the output end of the second delay module and the output end of the third delay module respectively, and under the control of the flip signal of the output result of the aforementioned fifth trigger, the processing result of one of the second delay module and the third delay module is selected as the aforementioned first reset signal.
[0043] Preferably, the reset terminal of the aforementioned first trigger is also connected to the aforementioned power-on reset signal, and the aforementioned first trigger is reset according to one of the aforementioned power-on reset signal and the aforementioned first reset signal.
[0044] Preferably, any one of the first trigger, the second trigger, the third trigger and the fifth trigger is an RS trigger.
[0045] And either of the fourth trigger and the sixth trigger is a D trigger.
[0046] The beneficial effects of the present invention are as follows: a timing control circuit provided by the present invention at least comprises: a first transmission path connected to a first trigger, a second transmission path connected to a second trigger, and a third transmission path connected to three triggers, each transmission path uses a set module connected to the set end of the trigger on the respective path to provide a set signal when powered on, and uses a reset module connected to the reset end of the trigger to provide a reset signal when powered off, so as to provide a first timing signal (and a flip signal of the first timing signal), a second timing signal (and a flip signal of the second timing signal), and a third timing signal (and a flip signal of the third timing signal) correspondingly, and the timing control circuit can realize the function of controlling the first to third transmission paths to perform timing power-on and timing power-off according to an enable signal;
[0047] At the same time, the timing control circuit uses the output timing signal of the previous transmission path to provide the establishment of the output timing signal of the current transmission path, and the currently established timing signal participates in the establishment of the output timing signal of the next transmission path, thereby realizing the cumulative timing function between adjacent transmission paths;
[0048] In addition, the timing control circuit has a simple structure, and each logic element therein can be integrated using metal oxide semiconductor field effect transistors (MOS tubes for short). Through integrated design, the area occupied by the timing control circuit in the chip can be effectively reduced, thereby improving the integration and functionality of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.
[0050] Figure 1 A schematic diagram showing the structure of a timing control circuit provided by an embodiment of the present disclosure is shown;
[0051] Figure 2 Show Figure 1 A circuit diagram of a first path in the timing control circuit shown;
[0052] Figure 3 Show Figure 1 The timing diagram of each signal of the timing control circuit shown in the first embodiment;
[0053] Figure 4 Show Figure 1 The timing diagram of each signal of the timing control circuit shown in the second embodiment;
[0054] Figure 5 Show Figure 1 The timing diagram of each signal of the timing control circuit in the third embodiment is shown;
[0055] Figure 6 Show Figure 1 The timing diagram of each signal of the timing control circuit in the fourth embodiment shown;
[0056] Figure 7 Show Figure 1 The timing diagram of each signal of the timing control circuit in the fifth embodiment shown;
[0057] Figure 8 Show Figure 1 The timing diagram of each signal of the timing control circuit in the sixth embodiment is shown. DETAILED DESCRIPTION
[0058] In order to facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present disclosure more thorough and comprehensive.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used in the specification of the present disclosure below are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.
[0060] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.
[0061] Figure 1 A schematic diagram of the structure of a timing control circuit provided by an embodiment of the present disclosure is shown. Figure 2 Show Figure 1 A circuit diagram of the first path in the timing control circuit shown.
[0062] refer to Figure 1 According to an embodiment of the present disclosure, a timing control circuit 10 has at least two transmission paths. In this embodiment, the at least two transmission paths include but are not limited to: a first transmission path (not shown), a second transmission path (not shown) and a third transmission path (not shown), wherein the first transmission path includes:
[0063] A first trigger 130, for providing a first timing signal F-1;
[0064] A first setting module 110, the output end of which is connected to the setting end S of the first flip-flop 130, and has a first input end for receiving an enable signal EN and a second input end for receiving a flip signal F-1B of the first timing signal F-1;
[0065] A first reset module 120, the output end of which is connected to the reset end R2 of the first trigger 130, and has a third input end for receiving the second timing signal F-2 and a fourth input end for receiving the flip signal F-1B of the first timing signal F-1;
[0066] Furthermore, in the present embodiment, the reset terminal R1 of the first trigger 130 is also connected to a power-on reset signal POR, and the first trigger 130 is reset according to the power-on reset signal POR and one of the first reset signals provided by the first reset module 120. In the present embodiment, the power-on reset signal POR can be obtained according to the internal enable signal EN of the chip, or can be provided by an external circuit of the chip, which is not limited here.
[0067] The second transmission path includes:
[0068] The second trigger 230 is used to provide the second timing signal F-2;
[0069] A second setting module 210, the output end of which is connected to the setting end of the second flip-flop 230, and has a fifth input end for receiving the first timing signal F-1 and a sixth input end for receiving the flip signal F-2B of the second timing signal F-2;
[0070] A second reset module 220, the output end of which is connected to the reset end of the second trigger 230, and has a seventh input end for receiving the third timing signal F-3 and an eighth input end for receiving the flip signal F-2B of the second timing signal F-2;
[0071] The third transmission path includes:
[0072] A third trigger 330, for providing the third timing signal F-3;
[0073] A third setting module 310, the output end of the third setting module 310 is connected to the setting end of the third flip-flop 330, and has a ninth input end for receiving the second timing signal F-2 and a tenth input end for receiving the flip signal F-3B of the third timing signal F-3;
[0074] A third reset module 320, the output end of the third reset module 320 is connected to the reset end of the third flip-flop 330, and has an eleventh input end for receiving a flip signal of the enable signal EN and a twelfth input end for receiving a flip signal F-3B of the third timing signal F-3;
[0075] The timing control circuit 10 can control the at least two transmission paths to perform timing power-up and timing power-down according to the aforementioned enable signal EN.
[0076] Furthermore, the first transmission path also includes:
[0077] The first inverter 140 has an input terminal connected to the output terminal of the first trigger 130 for providing the inversion signal F-1B of the first timing signal F-1.
[0078] Furthermore, the second transmission path also includes:
[0079] The second inverter 240 has an input terminal connected to the output terminal of the second flip-flop 230 for providing the inversion signal F-2B of the second timing signal F-2.
[0080] Furthermore, the third transmission path also includes:
[0081] The third inverter 340 has an input terminal connected to the output terminal of the third flip-flop 330 and is used to provide the inversion signal F-3B of the third timing signal F-3.
[0082] In this embodiment, each transmission path uses a set module connected to the set end of the trigger on each path to provide a set signal when powered on, and uses a reset module connected to the reset end of the trigger to provide a reset signal when powered off, so as to provide a first timing signal F-1 (and a flip signal F-1B of the first timing signal F-1), a second timing signal F-2 (and a flip signal F-2B of the second timing signal F-2) and a third timing signal F-3 (and a flip signal F-3B of the third timing signal F-3) at the output ends of the first transmission path, the second transmission path and the third transmission path, respectively. The timing control circuit 10 can realize the function of controlling the first to third transmission paths to perform sequential power-on and sequential power-off according to the enable signal EN.
[0083] Combination Figure 2 In this embodiment, the first transmission path is used as an example for explanation. The circuit structure of the second transmission path and the third transmission path are similar to that of the first transmission path, and one part is different in the delay of the clock pulse output in the logic control. Because this part of the logic is relatively large and ordinary technicians in this field can refer to the timing diagrams corresponding to the various implementation methods below and implement it with the technical solutions disclosed in the prior art, so no examples are given here one by one.
[0084] like Figure 2 As shown, the first setting module 110 includes: a first NAND gate 111 , a first NOR gate 112 , a fourth trigger 113 and a first delay unit 114 .
[0085] Specifically, two input terminals of the first NAND gate 111 are respectively connected to the aforementioned enable signal EN and the aforementioned flip signal F-1B of the first timing signal F-1;
[0086] The input end of the first NOR gate 112 is connected to the output end of the first NAND gate 111, and generates a first level signal (not shown) according to the logic judgment result of the output signal of the first NAND gate 111 and the power-on reset signal POR;
[0087] The reset terminal of the fourth flip-flop 113 is connected to the first clock signal CLK1, which is used to logically control the fourth flip-flop 113 to be reset, and the set terminal D is connected to the output terminal of the first NOR gate 112, which is connected to the aforementioned first level signal;
[0088] The first delay unit 114 is connected between the fourth trigger 113 and the first trigger 130 , and is used to provide a first set signal to the first trigger 130 , and perform delay processing on the first trigger 130 according to an output result of the fourth trigger 113 .
[0089] Furthermore, the first reset module 120 in this embodiment includes: a fifth trigger 121 , a fourth inverter 122 , a second NAND gate 123 , a sixth trigger 124 and a second delay unit 125 .
[0090] Specifically, the set terminal S of the fifth trigger 121 is connected to the output terminal of the second trigger 230 and connected to the second timing signal F-2. The first reset terminal R1 is connected to the output terminal of the first inverter 140 to obtain the flip signal F-1B of the first timing signal F-1. The second reset terminal R2 is connected to the power-on reset signal POR.
[0091] The input terminal of the fourth inverter 122 is connected to the output terminal of the fifth flip-flop 121 to obtain the flip signal F-1A of the output result of the fifth flip-flop 121;
[0092] The two input terminals of the second NAND gate 123 are respectively connected to the output result of the fourth inverter 122 and the aforementioned enable signal EN;
[0093] The reset terminal of the sixth flip-flop 124 is connected to the second clock signal CLK2 for logic control of clearing the sixth flip-flop 124, and the set terminal D is connected to the output terminal of the second NAND gate 123;
[0094] The second delay unit 125 is connected between the first trigger 130 and the sixth trigger 124 , and is used to provide a first reset signal to the first trigger 130 , and perform delay processing on the first trigger 130 according to an output result of the sixth trigger 124 .
[0095] In one implementation of this embodiment, the first delay unit 114 and / or the second delay unit 125 is a delay module composed of a plurality of cascaded inverters.
[0096] In another preferred implementation of this embodiment, the first delay unit 114 is a first delay module 1141 composed of a plurality of inverters connected in cascade.
[0097] The second delay unit 125 comprises: a second delay module 1251 composed of a plurality of inverters connected in cascade, a third delay module 1252 composed of a plurality of inverters connected in cascade, and a selection switch 1253. Figure 2 As shown, the delay times of the second delay module 1251 and the third delay module 1252 are different, and the selection switch 1253 is respectively connected to the output end of the second delay module 1251 and the output end of the third delay module 1252. Under the control of the flip signal F-1A of the output result of the aforementioned fifth trigger 121, the processing result of one of the second delay module 1251 and the third delay module 1252 is selected as the aforementioned first reset signal.
[0098] In this embodiment, for example, the first delay module 1141 can delay the output level of the fourth trigger 113 by 5 clock pulses (clk) output, the second delay module 1251 can delay the output level of the sixth trigger 124 by 5 clk outputs, and the third delay module 1252 can delay the output level of the sixth trigger 124 by 4 clk outputs. The clock delay of each of the above delay modules is generated by clock superposition. The delay time is not unique here and can be set according to the application requirements in the actual chip. In this embodiment, only the above example data is used to illustrate and introduce the embodiment of the present disclosure.
[0099] Further, any one of the first trigger 130 , the second trigger 230 , the third trigger 330 and the fifth trigger 121 is an RS trigger, and any one of the fourth trigger 114 and the sixth trigger 124 is a D trigger.
[0100] Figure 3 to Figure 8 The test waveform results of various timing signals outputted by the timing control circuit 10 in accordance with the enable signal EN in different implementation modes in the embodiment of the present disclosure are respectively shown.
[0101] correspond Figure 3In the enable signal EN, at time t1, the chip indicates power-on, and the first timing signal F-1 provided by the first transmission path is delayed to t2 time to trigger compared with the rising edge of the enable signal EN (for example, delayed by 5 clk time, that is, t2-t1=5*clk). Combined with the above example, the second timing signal F-2 provided by the second transmission path is delayed to t3 time to trigger compared with the rising edge of the first timing signal F-1 (for example, delayed by 4 clk time, that is, t3-t2=4*clk), and the third timing signal F-3 provided by the third transmission path is delayed to t4 time to trigger compared with the rising edge of the second timing signal F-2 (for example, delayed by 4 clk time, that is, t4-t3=4*clk); at time t5, the chip indicates power-off, and the third timing signal F-3 provided by the third transmission path is delayed to t6 time to trigger compared with the falling edge of the enable signal EN. The timing control circuit 10 realizes the timing power-on (power-on sequence is the first timing signal F-1 to the second timing signal F-2 to the third timing signal F-3) and the timing power-off (power-off sequence is the third timing signal F-3 to the second timing signal F-2 to the first timing signal F-1) functions.
[0102] At the same time, the timing control circuit 10 uses the first timing signal F-1 output by the first transmission path to provide it to the input end of the second transmission path, and participates in the establishment of the second timing signal F-2. After the establishment is completed, the second timing signal F-2 participates in the establishment of the third timing signal F-3 output by the third transmission path. By utilizing the establishment of the delay time and the accumulation of the enable signal EN malfunction time, the cumulative timing function between adjacent transmission paths is realized.
[0103] by Figure 5 For example ( Figure 4The situation is similar), at time t3, after the second timing signal F-2 becomes high, the high level time starts to be counted, and after 4*clk, at time t4, the third timing signal F-3 becomes high. Then, there is a cumulative timing function during the period from t3 to t4, because the enable signal EN is high during this period. When there is a low level pulse time period tL (false operation time), as long as the low level pulse time period tL does not reach the time (5*clk) for the second timing signal F-2 to flip again (from high level to low level), the aforementioned timing power-on function can be realized while realizing the cumulative timing function, and the time from the second timing signal F-2 becoming high to the third timing signal F-3 becoming high is t4-t3=4*clk+tL.
[0104] When powering on, because the first timing signal F-1 is powered on first, and the second timing signal F-2 to the third timing signal F-3 are powered on in sequence, the cumulative timing function can be applied between the output end of the first transmission path and the output end of the second transmission path, and between the output end of the second transmission path and the output end of the third transmission path, specifically, it occurs in the time period from t2 to t3 and the time period from t3 to t4; when powering off, because the third timing signal F-3 is powered off first, and the second timing signal F-2 to the first timing signal F-1 are powered off in sequence, the cumulative timing function can be applied between the output end of the third transmission path and the output end of the second transmission path, and between the output end of the second transmission path and the output end of the first transmission path, specifically, it occurs in the time period from t6 to t7 and the time period from t7 to t8.
[0105] refer to Figure 6 , under the timing control of the enable signal EN, while realizing the above functions, it is different from Figure 5 As shown, the enable signal EN is at a low level indicating that the first timing signal F-1 has not reached the trigger time at time t5 after the second timing signal F-2 is powered off, and the enable signal EN is turned to a high level and starts to power on. After the first timing signal F-1 is powered on, it is always in a high level state. Compared with the rising edge of the enable signal EN at time t5, the second timing signal F-2 is delayed to be triggered at time t6 (for example, delayed by 4 clk times, that is, t6-t5-tL=4*clk, where tL represents the low level time of malfunction during this period. Similarly, Figure 5 The malfunction time of the enable signal EN in the time period from t3 to t4 is tL), so that the timing power-on and timing power-off functions of some timing signals are realized by using logic control, so that the timing control circuit 10 can achieve precise control of the enable power-on timing, power-off timing and delay time, and at the same time, to a certain extent, it also realizes the fault tolerance function of the enable signal malfunction, ensures the stability of the chip, and can realize the special functional requirements of the timing control circuit 10 in chip applications.
[0106] refer to Figure 7 and Figure 8 When the timing control circuit 10 is powered on, compared with the rising edge of the enable signal EN at time t1, the delayed trigger time of the first timing signal F-1 (for example, set to t2-t1=5*clk) is longer than the delayed trigger time of the second timing signal F-2 (for example, set to t3-t2=4*clk) and the delayed trigger time of the third timing signal F-3 that are powered on in sequence later; when powered off, the delayed trigger time of the enable signal EN and the third timing signal F-3 is, for example, 5*clk, and the delayed trigger time of the second timing signal F-2 and the delayed trigger time of the third timing signal F-3 that are powered off in sequence later are, for example, both 4*clk. If the third timing signal F-3 does not flip to power on and starts to power off sequentially, then compared with the falling edge of the enable signal EN at time t4, the delayed trigger time of the second timing signal F-2 is t5-t4=5*clk, and the delayed trigger time of the first timing signal F-1 that is powered on in sequence later is t6-t5=4*clk. Figure 7 As shown; if the second timing signal F-2 does not flip to power on and starts to power off, compared with the falling edge of the enable signal EN at time t3, the delayed trigger time of the first timing signal F-1 is t4-t3=5*clk, such as Figure 8 shown.
[0107] In this embodiment, the timing control circuit 10 utilizes the characteristics of the RS trigger (the first trigger 130, the second trigger 230, the third trigger 330 and the fifth trigger 121), and utilizes the set end S of the trigger when powered on, and utilizes the reset end (R1 and R2) of the RS trigger when powered off. Specifically, when powered on, the enable signal EN is in a high level state, and only the set end of the RS trigger (the set module connected to R2) works, and the next timing signal (such as the second timing signal F-2) will work only after the previous timing signal (such as the first timing signal F-1) is established. When powered off, the enable signal EN is in a low level state, and only the reset end of the RS trigger (the connected reset module) works. Because there is a situation where some transmission path outputs have not been flipped when powered off, it is not necessary to know whether the previous timing signal has been flipped when the timing is powered off. The work of each reset end can be performed independently, so that the timing control circuit 10 realizes the timing power-on and timing power-off functions while ensuring the flexibility and reliability of chip power-off.
[0108] In summary, the timing control circuit 10 provided in the embodiment of the present disclosure at least includes: a first transmission path connected to the first trigger 130, a second transmission path connected to the second trigger 230, and a third transmission path connected to the three triggers 330. When each transmission path is powered on, a set module connected to the set end S of the RS trigger on the respective path is used to provide a set signal, and when powered off, a reset module connected to the reset end R2 of the trigger is used to provide a reset signal. Through the logic circuit design, the first timing signal F-1 (and the flip signal F-1B of the first timing signal F-1), the second timing signal F-2 (and the flip signal F-2B of the second timing signal F-2) and the third timing signal F-3 (and the flip signal F-3B of the third timing signal) are provided correspondingly. The timing control circuit 10 can realize the function of controlling the first to third transmission paths to perform timing power-on and timing power-off according to the enable signal EN;
[0109] At the same time, the timing control circuit uses the timing signal output by the previous transmission path to provide the establishment of the timing signal output by the current transmission path, and the currently established timing signal participates in the establishment of the timing signal output by the next transmission path, thereby realizing the cumulative timing function between adjacent transmission paths;
[0110] In addition, the timing control circuit 10 has a simple structure, and each logic element therein can be integrated using metal oxide semiconductor field effect transistors (MOS tubes for short). It has a small shutdown current, low static power consumption, and high process flexibility and reliability. Through integrated circuit design, it can effectively reduce the occupied area of the timing control circuit 10 in the chip, thereby improving the integration and functionality of the chip.
[0111] It should be noted that in the description of the present disclosure, it needs to be understood that the terms "upper", "lower", "inner" and the like indicating orientation or positional relationship are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0112] In addition, in this article, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.
[0113] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.
Claims
1. A timing control circuit having a plurality of transmission paths, wherein: The multiple transmission paths include: The first transmission path includes: A first trigger, used for providing a first timing signal; A first setting module, whose output end is connected to the setting end of the first trigger, and has a first input end for receiving an enable signal and a second input end for receiving a flip signal of the first timing signal; A first reset module, the output end of which is connected to the reset end of the first trigger, and has a third input end for receiving a second timing signal and a fourth input end for receiving a flip signal of the first timing signal; The second transmission path includes: A second trigger, used for providing the second timing signal; A second setting module, whose output end is connected to the setting end of the second trigger, and has a fifth input end for receiving the first timing signal and a sixth input end for receiving a flip signal of the second timing signal; A second reset module, the output end of which is connected to the reset end of the second trigger, and has a seventh input end for receiving a third timing signal and an eighth input end for receiving a flip signal of the second timing signal; The third transmission path includes: A third trigger, used for providing the third timing signal; A third setting module, whose output end is connected to the setting end of the third trigger, and has a ninth input end for receiving the second timing signal and a tenth input end for receiving a flip signal of the third timing signal; A third reset module, the output end of which is connected to the reset end of the third trigger, and has an eleventh input end for receiving the flip signal of the enable signal and a twelfth input end for receiving the flip signal of the third timing signal; The timing control circuit controls the plurality of transmission paths to perform sequential power-up and sequential power-down according to the enable signal.
2. The timing control circuit according to claim 1, wherein: The first transmission path further includes: The first inverter has an input terminal connected to the output terminal of the first trigger and is used to provide a flip signal of the first timing signal.
3. The timing control circuit according to claim 1, wherein: The second transmission path further includes: The second inverter has an input terminal connected to the output terminal of the second trigger and is used to provide a flip signal of the second timing signal.
4. The timing control circuit according to claim 1, wherein: The third transmission path further includes: The third inverter has an input terminal connected to the output terminal of the third trigger and is used to provide a flip signal of the third timing signal.
5. The timing control circuit according to claim 2, wherein: The first setting module comprises: A first NAND gate, whose input terminals are respectively connected to the enable signal and the flip signal of the first timing signal; A first NOR gate, whose input end is connected to the output end of the first NAND gate, and generates a first level signal according to a logic judgment result of the output signal of the first NAND gate and a power-on reset signal; A fourth trigger, wherein a reset terminal is connected to the first clock signal, a set terminal is connected to the output terminal of the first NOR gate, and is connected to the first level signal; The first delay unit is connected between the fourth trigger and the first trigger, and is used to provide a first set signal for the first trigger, and perform delay processing on the first trigger according to an output result of the fourth trigger.
6. The timing control circuit according to claim 5, wherein: The first reset module includes: A fifth trigger, wherein a set terminal is connected to the output terminal of the second trigger, a first reset terminal is connected to the output terminal of the first inverter, and a second reset terminal is connected to the power-on reset signal; a fourth inverter, whose input end is connected to the output end of the fifth trigger, so as to obtain a flip signal of the output result of the fifth trigger; A second NAND gate, whose input terminals are respectively connected to the output result of the fourth inverter and the enable signal; A sixth flip-flop, a reset terminal connected to the second clock signal, and a set terminal connected to the output terminal of the second NAND gate; The second delay unit is connected between the first trigger and the sixth trigger, and is used for providing a first reset signal for the first trigger, and performing delay processing on the first trigger according to an output result of the sixth trigger.
7. The timing control circuit according to claim 6, wherein: The first delay unit and / or the second delay unit is a delay module composed of a plurality of inverters cascaded.
8. The timing control circuit according to claim 6, wherein: The first delay unit is a first delay module composed of a plurality of inverters cascaded. Furthermore, the second delay unit comprises: A second delay module composed of a plurality of cascaded inverters; a third delay module composed of a plurality of cascaded inverters, wherein the delay times of the second delay module and the third delay module are different, and A selection switch is connected to the output end of the second delay module and the output end of the third delay module respectively, and under the control of the flip signal of the output result of the fifth trigger, a processing result of one of the second delay module and the third delay module is selected as the first reset signal.
9. The timing control circuit according to claim 8, wherein: The reset terminal of the first trigger is also connected to the power-on reset signal, and the first trigger is reset according to one of the power-on reset signal and the first reset signal.
10. The timing control circuit according to claim 9, wherein: Any one of the first trigger, the second trigger, the third trigger and the fifth trigger is an RS trigger, And any one of the fourth flip-flop and the sixth flip-flop is a D flip-flop.