Packaging structure

Abstract

A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and multiple first power lines. The second chip is connected to a pair of second signal lines and multiple second power lines. The first chip and the second chip belong to the same wafer, and a separator is located between the first chip and the second chip. This allows for a smaller package size.

Description

Technical Field

[0001] The embodiments described in this disclosure relate to packaging technology, and more particularly to a packaging structure. Background Technology

[0002] With the development of technology, integrated circuits have been applied to many fields, and various packaging methods have emerged.

[0003] In some related technologies, one or more independent chips are packaged into the same package structure. For example, chips belonging to different wafers are attached to a flexible printed circuit board, allowing these chips to be packaged into the same package structure. Because these chips belong to different wafers, according to packaging rules, there will be a relatively long distance between two adjacent chips in this package structure (e.g., between 6 cm and 10 cm). In this case, the size of the package structure will be relatively large. Summary of the Invention

[0004] Some embodiments disclosed herein relate to a packaging structure. The packaging structure includes a first wafer and a second wafer. The first wafer is connected to a pair of first signal lines and multiple first power lines. The second wafer is connected to a pair of second signal lines and multiple second power lines. The first wafer and the second wafer belong to the same wafer, and a separator is located between the first wafer and the second wafer.

[0005] In some embodiments, the first chip and the second chip perform the same function.

[0006] In some embodiments, the first chip and the second chip perform different functions.

[0007] In some embodiments, these first power lines are disposed on both sides of the pair of first signal lines.

[0008] In some embodiments, these second power lines are disposed on both sides of the pair of second signal lines.

[0009] In some embodiments, a separation channel is located between one of the first power lines and one of the second power lines.

[0010] In some embodiments, the pair of first signal lines is adjacent to the pair of second signal lines.

[0011] In some embodiments, the pair of first signal lines and the pair of second signal lines are disposed between the first power lines and the second power lines.

[0012] In some embodiments, a separator is located between one of the first signal lines and one of the second signal lines.

[0013] In some embodiments, the partition channel is an invalid circuit area.

[0014] In some embodiments, the first wafer is independent of the second wafer.

[0015] In some embodiments, the first wafer and the second wafer are electrically separated.

[0016] In some embodiments, the width of the partition is less than 6 centimeters.

[0017] In some embodiments, the width of the partition channel is substantially in the range of 70 micrometers to 90 micrometers.

[0018] In some embodiments, the package structure further includes multiple through-wires. These through-wires are disposed on one side of the first wafer and one side of the second wafer. These through-wires are used to transmit multiple signals without passing through the first wafer and the second wafer.

[0019] In some embodiments, the pair of first signal lines or the pair of second signal lines are used to receive a plurality of differential signals. These differential signals originate from a timing controller of a display device. The first power lines or the second power lines are used to receive a plurality of power signals, and these power signals originate from a power integrated circuit of the display device.

[0020] In some embodiments, the second wafer and the first wafer are located in a flip-chip bonded package. Attached Figure Description

[0021] To make the above and other objects, features, advantages and embodiments disclosed herein more apparent and understandable, the accompanying drawings are described below:

[0022] Figure 1 This is a schematic diagram of an electronic system illustrated in accordance with some embodiments of the present disclosure;

[0023] Figure 2 This is a schematic diagram of an integrated circuit on a flexible printed circuit board illustrated according to some embodiments of the present disclosure; and

[0024] Figure 3 This is a schematic diagram of an integrated circuit on a flexible printed circuit board, illustrated in accordance with some embodiments of the present disclosure.

[0025] [Symbol Explanation]

[0026] 100: Electronic Systems

[0027] 120, 120A, 120B: Driver integrated circuits

[0028] 1201, 1202, 1203, 1204: Chips

[0029] 140: Power Supply Integrated Circuit

[0030] 160: Timing Controller

[0031] 180: Display panel

[0032] 190: Flexible Printed Circuit Board

[0033] L1, L1a, L1b, L1c, L1d: Power cords

[0034] L2, L2a, L2b, L2c, L2d: Signal lines

[0035] L3, L3a, L3b, L3c, L3d: Crossing lines

[0036] L4: Chip Line

[0037] PS: Power signal

[0038] DS: Differential signal

[0039] LS: Crossing Line Signal

[0040] CS: Chip signal

[0041] SS1, SS2: Separator Detailed Implementation

[0042] The following description will be given in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of this disclosure. The structures and operations are not intended to restrict the order of execution. Any structure with equivalent effects after reconfiguration of elements falls within the scope of this disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements in the following paragraphs will be labeled with the same symbols.

[0043] It should be understood that although the terms "first," "second," and "third," etc., are used in this disclosure to describe various elements, components, regions, layers, and / or blocks, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer, and / or block. Therefore, a first element, component, region, layer, and / or block in the following paragraphs may also be referred to as a second element, component, region, layer, and / or block without departing from the intent of this disclosure.

[0044] refer to Figure 1 . Figure 1 This is a schematic diagram of an electronic system 100 illustrated according to some embodiments of the present disclosure. In some embodiments, the electronic system 100 is a display device for displaying an image.

[0045] The above-described implementation of the electronic system 100 is merely illustrative and is not intended to limit the scope of this disclosure. Various implementations of the electronic system 100 are within the scope of this disclosure. For example, the electronic system 100 may be an electronic system with other functions.

[0046] by Figure 1 For example, electronic system 100 includes driver integrated circuit (IC) 120, power integrated circuit 140, timing controller 160, and display panel 180. Driver integrated circuit 120 is attached to flexible printed circuit board 190.

[0047] The power supply integrated circuit 140 is coupled to the driver integrated circuit 120 and is used to provide power to the driver integrated circuit 120. In some embodiments, the power supply integrated circuit 140 includes multiple power supplies to provide different power supply voltages to the driver integrated circuit 120 to start the driver integrated circuit 120.

[0048] The timing controller 160 is coupled to and used to control the driver integrated circuit 120. In some embodiments, the timing controller 160 includes multiple signal sources to provide different control signals or display data to the driver integrated circuit 120 to control the driver integrated circuit 120.

[0049] The driver integrated circuit 120 is coupled to and used to drive the display panel 180. In some embodiments, the driver integrated circuit 120 includes a plurality of driver chips to provide different driving voltages or display data to the display panel 180 to drive the display panel 180 to display images. For example, the driver integrated circuit 120 may be a source driver, a gate driver, or a combination thereof.

[0050] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0051] In some embodiments, the electronic system 100 further includes multiple power lines L1, multiple signal lines L2, multiple through lines L3, and multiple chip lines L4. These power lines L1, signal lines L2, through lines L3, and chip lines L4 can be implemented using conductive segments.

[0052] by Figure 1 For example, these power lines L1 are coupled between the power supply integrated circuit 140 and the driver integrated circuit 120. These power lines L1 are used to transmit multiple power signals PS from the power supply(s) in the power supply integrated circuit 140 to the driver integrated circuit 120. In this way, the driver integrated circuit 120 can be activated according to these received power signals PS.

[0053] These signal lines L2 are coupled between the timing controller 160 and the driver integrated circuit 120. These signal lines L2 are used to transmit multiple differential signals DS from multiple signal sources in the timing controller 160 to the driver integrated circuit 120. As described above, these differential signals DS can be control signals or display data. Thus, the driver integrated circuit 120 can be controlled to operate by these received differential signals DS.

[0054] These through-line lines L3 are disposed on the flexible printed circuit board 190 and coupled between the display panel 180 and other circuits. These through-line lines L3 are used to transmit multiple through-line signals LS between the display panel 180 and these other circuits without passing through the driver integrated circuit 120. These through-line signals LS can be other signals.

[0055] These chip lines L4 are coupled between the driver integrated circuit 120 and the display panel 180. These chip lines L4 are used to transmit multiple chip signals CS from the driver integrated circuit 120 to the display panel 180. As described above, these chip signals CS can be drive signals or display data. Thus, the display panel 180 can be driven to display images based on these received chip signals CS.

[0056] It should be noted that, Figure 1 The number of power lines L1, signal lines L2, through lines L3, and chip lines L4 is merely an example and is not limited thereto. Various numbers of power lines L1, signal lines L2, through lines L3, and chip lines L4 are all within the scope of this disclosure.

[0057] refer to Figure 2 . Figure 2 This is a schematic diagram of an integrated circuit on a flexible printed circuit board 190, illustrated according to some embodiments of this disclosure. Figure 2 For example, the integrated circuit on the flexible printed circuit board 190 is a driver integrated circuit 120A, and the driver integrated circuit 120A may be... Figure 1 An example of the driver integrated circuit 120.

[0058] In some embodiments, the driver integrated circuit 120A includes a plurality of wafers and these wafers belong to the same wafer. Figure 2 For example, the driver integrated circuit 120A includes a first chip 1201 and a second chip 1202, and the first chip 1201 and the second chip 1202 belong to the same wafer.

[0059] It should be noted that the number of chips in the driver integrated circuit 120A is merely an example and is not limited thereto. Various chip numbers are within the scope of this disclosure.

[0060] The first chip 1201 is coupled with multiple first power lines L1a and a pair of first signal lines L2a. The first power lines L1a are located on both sides of the pair of first signal lines L2a. Specifically, the pair of first signal lines L2a is located in the center of the first chip 1201, with a portion of the first power lines L1a located to the right of the pair of first signal lines L2a, and the remaining first power lines L1a located to the left of the pair of first signal lines L2a. Similarly, the second chip 1202 is coupled with multiple second power lines L1b and a pair of second signal lines L2b. The second power lines L1b are located on both sides of the pair of second signal lines L2b. Specifically, the pair of second signal lines L2b is located in the center of the second chip 1202, with a portion of the second power lines L1b located to the right of the pair of second signal lines L2b, and the remaining second power lines L1b located to the left of the pair of second signal lines L2b. Equivalently, a portion of the first power line L1a and a portion of the second power line L1b are disposed between the pair of first signal lines L2a and the pair of second signal lines L2b.

[0061] In addition, multiple through-wires L3a and L3b are disposed on both sides of the first chip 1201 and the second chip 1202. Specifically, these through-wires L3a are located on the left side of the first chip 1201, and these through-wires L3b are disposed on the right side of the second chip 1202. In other words, the first chip 1201, the second chip 1202, these first power lines L1a, these second power lines L1b, the pair of first signal lines L2a, and the pair of second signal lines L2b are disposed in the space between these through-wires L3a and L3b. These through-wires L3a and L3b are used for transmission. Figure 1 These cross-line signals LS do not pass through the first chip 1201 and the second chip 1202.

[0062] In some embodiments, the first chip 1201 and the second chip 1202 perform the same function. For example, both the first chip 1201 and the second chip 1202 are source drivers and they are used to drive a large-size display panel. In these embodiments, the number of channels of the driver integrated circuit 120A can be increased (for example, doubled).

[0063] In some other embodiments, the first chip 1201 and the second chip 1202 perform different functions. In these other embodiments, the driver integrated circuit 120A can perform multiple functions and can be applied to more fields.

[0064] As described above, the first wafer 1201 and the second wafer 1202 belong to the same wafer. In other words, the first wafer 1201 and the second wafer 1202 belong to the same wafer. Figure 2For example, a first wafer 1201 and a second wafer 1202 may be packaged in the same package structure, with a separator SS1 located between the first wafer 1201 and the second wafer 1202. In some embodiments, the separator SS1 is also referred to as a dicing line. Generally, when multiple wafers are designed on a wafer, the wafer is divided into multiple regions by multiple dicing lines, and the wafers are respectively positioned in these regions. Then, a dicer is used to cut these regions along these dicing lines to form multiple individual wafers.

[0065] by Figure 2 For example, a separator channel SS1 can be used to separate a first chip 1201 and a second chip 1202, and the separator channel SS1 is disposed between one of the first power lines L1a and one of the second power lines L1b. Specifically, the separator channel SS1 is disposed between the rightmost first power line L1a coupled to the first chip 1201 and the leftmost second power line L1b coupled to the second chip 1202.

[0066] However, in this disclosure, the separator SS1 is not cut, and the first wafer 1201 and the second wafer 1202 are packaged in the same package structure. For example, the first wafer 1201 and the second wafer 1202 may be packaged in a chip-on-film (CoF) package. Thus, the separator SS1 becomes a cut line within the package structure or a cut line within the driver integrated circuit 120A.

[0067] In some embodiments, the separator SS1 is a blank area or an invalid circuit area. In other words, by configuring the separator SS1, the first wafer 1201 is independent of the second wafer 1202, or the first wafer 1201 and the second wafer 1202 are electrically separated. In this case, the first wafer 1201 does not affect the operation of the second wafer 1202, and the second wafer 1202 does not affect the operation of the first wafer 1201.

[0068] In some related technologies, one or more independent chips are packaged into the same package structure. For example, chips belonging to different wafers are attached to a flexible printed circuit board, allowing these chips to be packaged into the same package structure. Because these chips belong to different wafers, according to packaging rules, there will be a relatively long distance between two adjacent chips in this package structure (e.g., between 6 cm and 10 cm). In this case, the size of the package structure will be relatively large.

[0069] Compared to the aforementioned related technologies, in this disclosure, the separator SS1 between the first wafer 1201 and the second wafer 1202 (which belong to the same wafer) is not cut, and the first wafer 1201 and the second wafer 1202 are packaged into the same package structure. Thus, because the distance between the first wafer 1201 and the second wafer 1202 on the same wafer is shorter, the package size can be reduced. In some embodiments, the width of the separator SS1 is less than the aforementioned 6 cm. In other words, the spacing between the first wafer 1201 and the second wafer 1202 is less than 6 cm. For example, the width of the separator SS1 can be substantially between 70 micrometers and 90 micrometers. Furthermore, with this configuration, the power supply design and circuit design can be simplified, and the driver integrated circuit 120A can share a photomask with other individual integrated circuit products.

[0070] refer to Figure 3 . Figure 3 This is a schematic diagram of an integrated circuit on a flexible printed circuit board 190, illustrated according to some embodiments of this disclosure. Figure 3 For example, the integrated circuit on the flexible printed circuit board 190 is a driver integrated circuit 120B, and the driver integrated circuit 120B can be... Figure 1 An example of a driver integrated circuit 120.

[0071] Similar to Figure 2 The driver integrated circuit 120A in the middle, Figure 3 The driver integrated circuit 120B in the middle comprises multiple chips, and these chips belong to the same wafer. Figure 3 For example, the driver integrated circuit 120B includes a first chip 1203 and a second chip 1204, and the first chip 1203 and the second chip 1204 belong to the same wafer.

[0072] It should be noted that the number of chips in the driver integrated circuit 120B is merely an example and is not limited thereto. Various chip numbers are within the scope of this disclosure.

[0073] A first chip 1203 is coupled with a plurality of first power lines L1c and a pair of first signal lines L2c. The pair of first signal lines L2c is disposed at the edge of the first chip 1203, and the first power lines L1c are disposed on one side of the pair of first signal lines L2c (for example, the left side). A second chip 1204 is coupled with a plurality of second power lines L1d and a pair of second signal lines L2d. The pair of second signal lines L2d is disposed at the edge of the second chip 1204, and the second power lines L1d are disposed on one side of the pair of second signal lines L2d (for example, the right side). The pair of first signal lines L2c is adjacent to the pair of second signal lines L2d, and the pair of first signal lines L2c and the pair of second signal lines L2d are disposed in the space between the first power lines L1c and the second power lines L1d.

[0074] In addition, multiple cross lines L3c and L3d are disposed on both sides of the first chip 1203 and the second chip 1204. Figure 3 The configuration and operation of these crossing lines L3c and L3d are similar to... Figure 2 The crossing lines L3a and L3b are not described in detail here.

[0075] Similarly, the first chip 1203 and the second chip 1204 can perform the same or different functions. In this way, the number of channels of the driver integrated circuit 120B can be increased (for example, doubled) or the driver integrated circuit 120B can perform multiple functions.

[0076] As described above, the first wafer 1203 and the second wafer 1204 belong to the same wafer. In other words, the first wafer 1203 and the second wafer 1204 belong to the same wafer. Figure 3 For example, the first chip 1203 and the second chip 1204 may be packaged in the same package structure, and the separator SS2 is located between the first chip 1203 and the second chip 1204.

[0077] by Figure 3 For example, the separator SS2 can be used to separate the first chip 1203 and the second chip 1204, and the separator SS2 is disposed between one of the pair of first signal lines L2c and one of the pair of second power lines L2d.

[0078] In this disclosure, the separator SS2 is not cut, and the first wafer 1203 and the second wafer 1204 are packaged in the same package structure. For example, the first wafer 1203 and the second wafer 1204 may be packaged in a flip-chip package. Thus, the separator SS2 becomes a cut line within the package structure or a cut line within the driver integrated circuit 120B.

[0079] Figure 3 The function of the middle dividing lane SS2 is similar to Figure 2 The function of the middle dividing channel SS1 will not be elaborated here.

[0080] In summary, in this disclosure, the separator between the first wafer and the second wafer (which are located on the same wafer) is not cut, and the first wafer and the second wafer are packaged into the same package structure. Thus, because the distance between the first wafer and the second wafer, located on the same wafer, is short, the package size can be smaller.

[0081] Various functional components and blocks are disclosed herein. For those skilled in the art, functional blocks can be implemented by circuits (whether dedicated circuits or general-purpose circuits operating under the control of one or more processors and coded instructions), which generally include transistors or other circuit elements for controlling the operation of electrical circuits corresponding to the functions and operations described herein. Further understanding is that, generally, the specific structure and interconnection of the circuit elements can be determined by a compiler, such as a Register Transfer Language (RTL) compiler. A RTL compiler operates on scripts that are quite similar to assembly language code, compiling the scripts into a form for layout or construction of the final circuit.

[0082] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A packaging structure, characterized in that, Include: A first chip, connected to a pair of first signal lines and multiple first power lines; and A second chip connects a pair of second signal lines and multiple second power lines. The first chip and the second chip belong to the same wafer, a separator is located between the first chip and the second chip, and the first chip, the second chip, and the separator are packaged into the same package structure. The pair of first signal lines and the plurality of first power lines, the pair of second signal lines and the plurality of second power lines are disposed between the plurality of first through lines and the plurality of second through lines.

2. The packaging structure according to claim 1, characterized in that, The first chip and the second chip perform the same function.

3. The packaging structure according to claim 1, characterized in that, The first chip and the second chip perform different functions.

4. The packaging structure according to claim 1, characterized in that, The plurality of first power lines are disposed on both sides of the pair of first signal lines.

5. The packaging structure according to claim 1, characterized in that, The plurality of second power lines are disposed on both sides of the pair of second signal lines.

6. The packaging structure according to claim 5, characterized in that, The dividing channel is located between one of the plurality of first power lines and one of the plurality of second power lines.

7. The packaging structure according to claim 1, characterized in that, The first signal line is adjacent to the second signal line.

8. The packaging structure according to claim 7, characterized in that, The pair of first signal lines and the pair of second signal lines are disposed between the plurality of first power lines and the plurality of second power lines.

9. The packaging structure according to claim 7, characterized in that, The separator is located between one of the first signal lines and one of the second signal lines.

10. The packaging structure according to claim 1, characterized in that, The dividing channel is an invalid circuit area.

11. The packaging structure according to claim 1, characterized in that, The first chip is independent of the second chip.

12. The packaging structure according to claim 11, characterized in that, The first wafer and the second wafer are electrically separated.

13. The packaging structure according to claim 1, characterized in that, The width of the dividing channel is less than 6 centimeters.

14. The packaging structure according to claim 13, characterized in that, The width of the dividing channel is actually between 70 and 90 micrometers.

15. The packaging structure according to claim 1, characterized in that, The plurality of first through-wires are disposed on one side of the first wafer, and the plurality of second through-wires are disposed on one side of the second wafer. The plurality of first through-wires and the plurality of second through-wires are used to transmit multiple signals without passing through the first wafer and the second wafer.

16. The packaging structure according to claim 1, characterized in that, The pair of first signal lines or the pair of second signal lines are used to receive multiple differential signals, which are from a timing controller of a display device. The multiple first power lines or the multiple second power lines are used to receive multiple power signals, which are from a power integrated circuit of the display device.

17. The packaging structure according to claim 1, characterized in that, The same packaging structure is a chip-on-film package.

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