Memory and method for manufacturing the same
By setting the control area and memory area in dynamic random memory and controlling the conduction of bit lines, the loading time of the memory cell is optimized, the problem of poor memory performance is solved, and the speed and performance of the memory is improved.
Patent Information
- Application Number
- CN202011221712.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-11-05
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2040-11-05
AI Technical Summary
The read or write cycles of dynamic random memory are long, resulting in poor memory performance.
The control area and the storage area are arranged on the substrate, and the first and second active areas in the control area are connected to the bit lines, and the conduction of the bit lines is controlled to control the number of effective bit lines during read and write operations, thereby optimizing the memory unit loading time.
By controlling the conduction of the bit lines, the time of each read and write operation is reduced, and the average memory speed and performance of the memory are improved.
Smart Images
Figure CN114446956B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory and a preparation method thereof. Background Art
[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.
[0003] A dynamic random access memory generally includes a plurality of memory cells, which are arranged in rows and columns to form a memory matrix, wherein the memory cells in each column are connected by a word line, and the memory cells in each row are connected by a bit line. During reading or writing, the memory cells in the entire column connected by a word line are usually selected by column first, and then the memory cells in the entire row connected by a bit line are selected by row. In this way, when the bit line and word line of the target memory cell are selected at the same time, the target memory cell can be selected, thereby realizing reading data from or writing data to the target memory cell.
[0004] However, when a target storage unit is selected, the read or write cycle of the dynamic random access memory is long and the speed is slow, which is not conducive to improving the performance of the dynamic random access memory. Summary of the invention
[0005] In view of the above problems, an embodiment of the present invention provides a memory and a method for manufacturing the memory, which are used to increase the speed of the memory and thereby improve the performance of the memory.
[0006] In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
[0007] A first aspect of an embodiment of the present invention provides a memory, which includes a substrate, a control area is provided on the substrate, and storage areas are respectively provided on both sides of the control area; each storage area includes a plurality of first active areas, the plurality of first active areas are arranged into a plurality of rows along a first direction, each first active area is provided with a first contact area, and each first contact area in each row of first active areas is connected to a bit line; the control area includes a plurality of second active areas arranged along the first direction and corresponding one-to-one to the plurality of rows of first active areas; each second active area is provided with a first gate and a first source and drain area and a second source and drain area located on both sides of the first gate, and each first gate in the control area is connected to each other to form a control line; in the same second active area, the first source and drain area and the second source and drain area are each connected to a corresponding bit line, and the bit line connected to the first source and drain area and the bit line connected to the second source and drain area are located on both sides of the control line.
[0008] In some embodiments, in each second active region, a first conductive portion is disposed on the first source and drain region, and the first source and drain region is connected to a corresponding bit line through the first conductive portion.
[0009] In some embodiments, in each second active region, a second conductive portion is disposed on the second source and drain region, and the second source and drain region is connected to a corresponding bit line through the second conductive portion.
[0010] In some embodiments, the first conductive portion and the second conductive portion are located on the same layer.
[0011] In some implementations, a third conductive portion is disposed on the first contact region; and in each row of the first active region of each storage region, the third conductive portion on each first contact region is connected to a bit line.
[0012] In some embodiments, the first conductive portion, the second conductive portion, and the third conductive portion are located in the same layer.
[0013] In some embodiments, in each storage area, multiple first active areas are arranged into several columns along the second direction, and in the first active areas in any two adjacent rows, the column where all the first active areas in one row are located is alternately arranged with the column where all the first active areas in the other row are located, and each first active area in the same column intersects with two word lines, and in the first active areas in any adjacent columns, the ends of the first active areas in one column and the first active areas in another column that are close to each other intersect with the same word line, wherein the second direction is arranged perpendicular to the first direction; each first active area in the same column is provided with two second gates, and the two second gates are respectively connected to two word lines alternately arranged in the first active area.
[0014] In some embodiments, the first contact region on each first active region is located between the two second gates.
[0015] In some embodiments, the first gate and the second gate are located in the same layer.
[0016] In some embodiments, each first active region further includes a second contact region disposed on a side of each second gate away from the first contact region, and each second contact region is connected to a corresponding charge storage element.
[0017] In some embodiments, a plurality of control areas and a plurality of storage areas are disposed on the substrate, and the control areas and the storage areas are alternately disposed.
[0018] A second aspect of an embodiment of the present invention provides a method for preparing a memory, which comprises the following steps:
[0019] providing a substrate;
[0020] A control area is formed on a substrate, and storage areas are formed on both sides of the control area; each storage area includes a plurality of first active areas, the plurality of first active areas are arranged in a plurality of rows along a first direction, and the control area includes a plurality of second active areas arranged in the first direction and corresponding to the plurality of rows of first active areas one by one;
[0021] A first contact region is formed in each first active region, a first gate and a first source-drain region and a second source-drain region located on both sides of the first gate are arranged in each second active region, and the first gates in the control region are connected to each other to form a control line;
[0022] A bit line connected to each first contact area is formed above each row of the first active area. In the same second active area, the first source and drain areas and the second source and drain areas are respectively connected to a corresponding bit line, and the bit line connected to the first source and drain areas and the bit line connected to the second source and drain areas are located on both sides of the control line.
[0023] In some embodiments, in each second active region, a first conductive portion is formed on the first source and drain region, and the first source and drain region is connected to a corresponding bit line through the first conductive portion.
[0024] In some embodiments, in each second active region, a second conductive portion is formed on the second source and drain region, and the second source and drain region is connected to a corresponding bit line through the second conductive portion.
[0025] In some embodiments, the first conductive portion and the second conductive portion are formed in the same process step.
[0026] In some implementations, a third conductive portion is formed on the first contact region; and in each row of the first active region of each storage region, the third conductive portion on each first contact region is connected to a bit line.
[0027] In some embodiments, the first conductive portion, the second conductive portion, and the third conductive portion are formed in the same process step.
[0028] In some embodiments, in each storage area, a plurality of first active areas are arranged into a plurality of columns along the second direction, and in the first active areas in any two adjacent rows, the column where all the first active areas in one row are located is alternately arranged with the column where all the active areas in the other row are located, and each first active area in the same column is staggered with two word lines, and in the first active areas in any adjacent columns, the ends of the first active areas in one column and the first active areas in another column that are close to each other are connected to a word line; two second gates are formed in each first active area in the same column, and the two second gates are respectively connected to the two word lines staggered with the first active areas.
[0029] In some embodiments, the first contact region on each first active region is located between two second gates.
[0030] In some embodiments, the first gate and the second gate are provided in the same process step.
[0031] In some embodiments, a second contact region is further formed in each first active region and is located on a side of each second gate away from the first contact region, so as to connect each second contact region to a corresponding charge storage element.
[0032] In some embodiments, a plurality of control regions and a plurality of storage regions are formed on a substrate, and the control regions and the storage regions are alternately arranged.
[0033] In the memory provided by the embodiment of the present invention, a control area is set on a substrate, and storage areas are respectively set on both sides of the control area, and the first contact area of the first active area of each row of each storage area is connected to a bit line, and the first source and drain area and the second source and drain area of the second active area of the control area are connected to the corresponding bit lines on both sides of the second active area, and then by controlling the voltage of the control line, it is controlled whether the bit line connected to the first source and drain area and the bit line connected to the second source and drain area are turned on, and then the effective length of the bit line is controlled during each read operation and write operation, that is, the number of storage units connected to the effective bit line can be controlled in each read operation and write operation, and then the time of each read operation and write operation is controlled, so that the average storage speed of the memory is accelerated and the performance of the memory is improved.
[0034] The memory prepared by the method for preparing the memory of the embodiment of the present invention has fast storage speed and good performance, and the preparation process is simple and the process difficulty is low.
[0035] In addition to the technical problems solved by the embodiments of the present invention described above, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions, other technical problems that can be solved by the memory and the preparation method thereof provided by the embodiments of the present invention, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0037] Figure 1 It is a schematic diagram of the principle of a memory in the related art;
[0038] Figure 2aIt is a schematic diagram of the structure in which a first active region and a second active region are arranged on a substrate in this embodiment;
[0039] Figure 2b for Figure 2a Section view at line AA;
[0040] Figure 3a A schematic diagram of a structure of word lines and control lines formed for the memory provided in this embodiment;
[0041] Figure 3b for Figure 3a A cross-sectional view at the position of line BB;
[0042] Figure 4a A schematic diagram of a structure for forming a bit line for the memory provided in this embodiment Figure 1 ;
[0043] Figure 4b for Figure 4a Cross-sectional view at the CC line;
[0044] Figure 4c A second structural diagram of a memory device provided in this embodiment forming a bit line;
[0045] Figure 4d for Figure 4c Sectional view at line DD;
[0046] Figure 5a A schematic diagram of a structure in which a capacitor is formed in the memory provided in this embodiment;
[0047] Figure 5b for Figure 5a Cross-sectional view at line EE;
[0048] Figure 5c for Figure 5a Cross-sectional view at line FF;
[0049] Figure 6 A schematic diagram of the principle of the memory provided in this embodiment;
[0050] Figure 7 A flow chart of a method for preparing a memory provided in this embodiment.
[0051] Reference numerals:
[0052] 100: storage unit; 101: cache area;
[0053] 200: base; 201: control area;
[0054] 202: storage area; 203: first active area;
[0055] 204: first contact region; 205: bit line;
[0056] 206: word line; 207: trench insulation portion;
[0057] 208: a second gate; 209: a gate oxide layer;
[0058] 210: gate barrier layer; 211: gate conductive layer;
[0059] 212: second contact region; 213: fourth conductive portion;
[0060] 214: capacitor; 215: second active region;
[0061] 216: a first gate; 217: a first source and drain region;
[0062] 218: second source and drain region; 219: control line;
[0063] 220: gate insulating layer; 221: first conductive portion;
[0064] 222: second conductive portion; 223: third conductive portion. DETAILED DESCRIPTION
[0065] In the related art, a memory generally includes a plurality of storage units 100, for example, Figure 1 As shown, the memory includes fifteen memory cells 100, and the fifteen memory cells 100 form a memory matrix of five rows and three columns, wherein each row of memory cells 100 is connected by a word line 206 (English name is Word line, abbreviated as WL), and each column of memory cells 100 is connected by a bit line 205 (English name is Bit line, abbreviated as BL). The read operation principle of the memory is as follows:
[0066] Taking the read operation on the memory cell 100 in the first row and the first column as an example, first, all the memory cells 100 in the first row are selected through the word line 206 connected to the memory cell 100 in the first row, and are temporarily stored in the cache area 101. Then, all the memory cells 100 in the first column are selected through the bit line 205 connected to the memory cell 100 in the first column. In this way, the memory cell 100 in the first row and the first column can be selected, and then the read operation can be performed.
[0067] However, the inventors of the present application discovered that, for example, when it is necessary to select the storage cell 100 in the first row and first column, the storage cell 100 in the second row and first column, the storage cell 100 in the third row and first column, the storage cell 100 in the fourth row and first column, and the storage cell 100 in the fifth row and first column will also be selected, resulting in redundant loading of the storage cell 100 in the second row and first column, the storage cell 100 in the third row and first column, the storage cell 100 in the fourth row and first column, and the storage cell 100 in the fifth row and first column, which will increase the entire loading time, slow down the storage speed of the memory, and deteriorate the performance of the memory.
[0068] To this end, the present invention proposes a memory and a preparation method, which sets a control area and storage areas located on both sides of the control area on a substrate, sets multiple rows of first active areas in each storage area, each row of first active areas is connected to a bit line, and sets multiple second active areas in the control area, each second active area forms a first gate, a first source and drain area and a second source and drain area located at the first gate, and the first source and drain area and the second source and drain area are respectively connected to the bit lines on both sides of the second active area. In this way, by controlling the voltage of the first gate, all the first active areas of a corresponding row in two adjacent storage areas can be controlled to be turned on through the bit line connected to the first source and drain area and the bit line connected to the second source and drain area, thereby controlling the effective length of the bit line in each read operation and write operation, that is, in each read operation and write operation, the number of storage units connected to the effective bit line can be controlled, thereby reducing the time of each read operation and write operation, so that the average storage speed of the memory is accelerated and the performance of the memory is improved.
[0069] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.
[0070] like Figure 2a As shown, a memory provided in this embodiment includes a substrate 200 , wherein the substrate 200 is provided with a control area 201 , and storage areas 202 are respectively provided on both sides of the control area 201 .
[0071] See also Figure 2a Each storage area 202 includes a plurality of first active areas 203, and the plurality of first active areas 203 are arranged in a plurality of rows along the first direction. For example, in this embodiment, the plurality of first active areas 203 are arranged in seven rows along the first direction, and each row includes four first active areas 203. The first direction can be as follows: Figure 2aX direction shown. See Figure 4b As shown, each first active region 203 is provided with a first contact region 204 . In this embodiment, the first contact region 204 is approximately located in the middle of the first active region 203 , and each first contact region 204 in each row of the first active regions 203 is connected to a bit line 205 .
[0072] See also Figure 2a and Figure 3a In each storage area 202, the plurality of first active areas 203 are further arranged into a plurality of columns along a second direction, the second direction being perpendicular to the first direction, and the second direction may be as follows: Figure 3a In any two adjacent rows of first active areas 203, all first active areas 203 in one row are staggered with all first active areas 203 in the other row, and each first active area 203 in the same column intersects with two word lines 206. In any two adjacent columns of first active areas 203, the ends of the first active areas 203 in one column and the first active areas 203 in the other column that are close to each other intersect with the same word line 206. Further, the first active area 203 is a strip-shaped structure, and the first active area 203 extends along a third direction, and the third direction is arranged at a predetermined angle with the second direction, and the angle range is between 15° and 30°. The third direction is as shown in FIG. Figure 3a Z direction shown.
[0073] It should be noted that if Figure 2a and Figure 2b As shown, trench insulating portions 207 are disposed between adjacent first active regions 203 . The trench insulating portions 207 are formed by filling insulating materials in trenches between adjacent first active regions 203 , and are used to electrically separate adjacent first active regions 203 .
[0074] See also Figure 3a and Figure 3bAs shown, each first active region 203 in the same column is provided with two second gates 208, and the two second gates 208 are respectively connected to two word lines 206 staggered in the first active region 203. The second gate 208, for example, includes a gate oxide layer 209, a gate barrier layer 210, and a gate conductive layer 211. Specifically, a first gate groove is provided on the first active region 203, a layer of gate oxide layer 209 is deposited on the inner surface of the first gate groove, a layer of gate barrier layer 210 is deposited on the inner surface of the gate oxide layer 209, and the groove in the gate barrier layer 210 is filled with a gate conductive layer 211. The gate anode oxide layer is made of a high dielectric constant material or oxide, and the gate barrier layer 210 can be, for example, a metal electrode material for preventing mixing between the gate oxide layer 209 and the gate conductive layer 211. The gate conductive layer 211 is, for example, made of a metal electrode material. Moreover, in the first active areas 203 of the same column, a word line groove is also provided on the trench insulating portion 207 provided between adjacent first active areas 203, and a conductive material electrically connected to the gate conductive layer 211 is deposited in the word line groove. The conductive material in the word line groove is electrically connected to the gate conductive layer 211 to form a word line 206.
[0075] See also Figure 3b As shown, in some embodiments, each first active region 203 further includes a second contact region 212 disposed on a side of each second gate 208 away from the first contact region 204, and each second contact region 212 is connected to a corresponding charge storage element. The charge storage element is, for example, Figure 5a The capacitor 214 is shown. The capacitor 214 is, for example, Figure 5b The fourth conductive portion 213 is shown to be connected to the second contact region 212. Figure 3b As shown, the first contact area 204 on each first active area 203 is located between two second gates 208. At this time, each first active area 203 is connected to a bit line 205 and to two word lines 206. In this way, the two second gates 208, the first contact area 204 and the two second contact areas 212 on each first active area 203 together form two MOS transistors (Metal Oxide Semiconductor in English and Metal Oxide Semiconductor Field Effect Transistor in Chinese), wherein one second gate 208, the second contact area 212 on one side of the second gate 208 and the first contact area 204 on the other side of the second gate 208 together form a MOS transistor. This arrangement can make the memory structure more compact and more integrated.
[0076] See also Figure 4aAs shown, in the memory of this embodiment, each control area 201 includes a plurality of second active areas 215 arranged along the first direction and corresponding one-to-one to a plurality of rows of first active areas 203. The second active area 215 is also a strip-shaped structure, and the second active area 215 also extends along the third direction, and the third direction is set at a predetermined angle with the second direction, and the angle range is between 15° and 30°. It should be noted that trench insulating portions 207 are also provided between the second active areas 215 and between the second active areas 215 and the first active areas 203, and the trench insulating portions 207 are also used to electrically separate two adjacent second active areas 215, and adjacent first active areas 203 and the second active area 215.
[0077] See also Figure 4a and Figure 4b As shown, each second active region 215 is provided with a first gate 216 and a first source / drain region 217 and a second source / drain region 218 located on both sides of the first gate 216 . Each control region 201 includes a control line 219 that runs through each second active region 215 , that is, formed by connecting each first gate 216 .
[0078] Please continue reading Figure 4b As shown, the first gate 216 includes a gate oxide layer 209, a gate barrier layer 210 and a gate conductive layer 211. Specifically, a second gate groove is formed inside the second active region 215, a gate oxide layer 209 is deposited on the inner surface of the second gate groove, a gate barrier layer 210 is deposited on the inner surface of the gate oxide layer 209, and the gate conductive layer 211 is filled in the groove formed by the gate barrier layer 210. The gate oxide layer 209 is made of a high dielectric constant material or an oxide, the gate barrier layer 210 can be, for example, a metal electrode material, used to prevent mixing between the gate oxide layer 209 and the gate conductive layer 211, the gate conductive layer 211 is, for example, made of a metal electrode material, and the selection and combination of the materials of each layer of the first gate 216 can be defined according to the work function actually required.
[0079] Exemplarily, in some embodiments, a control line groove is provided in the trench insulating portion 207 of the control region 201, the control line groove in the trench insulating portion 207 of the control region 201 is connected to the second gate groove in the second active region 215, and the control line groove in the trench insulating portion 207 of the control region 201 is filled with a conductive material, so that the conductive material in the control line groove in the trench insulating portion 207 in the control region 201 and the gate conductive layer 211 in the first gate 216 are electrically connected, and together form a control line 219.
[0080] Please continue reading Figure 4bAs shown, in the second gate groove provided on the second active region 215, the top surfaces of the gate conductive layer 211, the gate barrier layer 210 and the gate oxide layer 209 are lower than the notch of the second gate groove, and in the second gate groove provided on the second active region 215, a gate insulating layer 220 is also provided above the gate conductive layer 211, the gate barrier layer 210 and the gate oxide layer 209, for insulating the gate conductive layer 211. Exemplarily, in the control line groove provided in the trench insulating portion 207 of the control region 201, the top surface of the conductive material filled in the control line groove is also lower than the notch of the control line groove, and the gate insulating layer 220 is also provided above the conductive material in the control line groove, for insulating the conductive material in the control line groove.
[0081] See also Figure 4c As shown, the first source drain region 217 and the second source drain region 218 are each connected to a corresponding bit line 205 , and the bit line 205 connected to the first source drain region 217 and the bit line 205 connected to the second source drain region 218 are located on both sides of the control line 219 .
[0082] It should be noted that the first source and drain region 217 and the second source and drain region 218 can be prepared by ion implantation. For example, boron is first doped into the second active region 215 to form a P-type semiconductor. Secondly, phosphorus or arsenic is doped into the first source and drain region 217 and the second source and drain region 218 to form an N-type semiconductor. In this way, the first source and drain region 217 and the second source and drain region 218 are formed.
[0083] It is worth noting that the first gate 216, the first source-drain region 217 and the second source-drain region 218 disposed in the second active layer form a MOS tube.
[0084] To illustrate the working principle of the memory of this embodiment, please refer to Figure 6As shown, in this embodiment, the memory includes three columns and four rows of memory cells 100, the memory cell 100 is the aforementioned capacitor 214, and a row of three second active areas 215 is arranged between the third row and the fourth row. Obviously, all the memory cells 100 in the first row, all the memory cells 100 in the second row, and all the memory cells 100 in the third row constitute a memory area 202, and the memory cells 100 in the fourth row constitute a memory area 202, and the three second active areas 215 in a row constitute a control area 201. The memory also includes three columns of bit line groups, four rows of word lines 206 and a row of control lines 219. The four rows of word lines 206 connect the storage cells 100 where the word lines 206 of each row are located. Each column of the bit line group includes a bit line 205 connecting the first row of the column, the second row of the column and the third row of the column, and a bit line 205 connecting the fourth row of the column. The two bit lines 205 of each column of the bit line 205 group are respectively connected to the first source and drain regions 217 and the second source and drain regions 218 of the corresponding second active region 215. Exemplarily, when the memory cell 100 in the first row and the first column is read, the gate voltage of the second active area 215 in the first column can be controlled so that the two bit lines 205 in the first column are not turned on. At this time, there is no need to load the memory cell 100 in the first row and the first column, and the loading time is shortened. When the memory cell 100 in the first row and the first column is read, the gate voltage of the second active area 215 in the first column can be controlled so that the two bit lines 205 in the first column are turned on. At this time, the memory cell 100 in the first row and the first column can be loaded through all the memory cells 100 in the first column. In this way, when the number of read operations increases, the average storage speed of the memory is accelerated, and the performance of the memory is improved. In addition, the position of the second active area 215 can be controlled to reasonably divide the memory area 202, so that the frequently used memory cells 100 are located in one memory area 202, which can further accelerate the average storage speed of the memory and improve the performance of the memory.
[0085] In the memory provided by the embodiment of the present invention, a control area 201 is set on a substrate 200, and storage areas 202 are respectively set on both sides of the control area 201, and the first contact area 204 of the first active area 203 of each row of each storage area 202 is connected to a bit line 205, and the first source and drain area 217 and the second source and drain area 218 of the second active area 215 of the control area 201 are connected to the corresponding bit lines 205 on both sides of the second active area 215, and then by controlling the voltage of the control line 219, it is controlled whether the bit line 205 connected to the first source and drain area 217 and the bit line 205 connected to the second source and drain area 218 are turned on, and then the effective length of the bit line 205 is controlled during each read operation and write operation, that is, the number of storage units 100 connected to the effective bit line 205 can be controlled in each read operation and write operation, and then the time of each read operation and write operation is controlled, so that the average storage speed of the memory is accelerated and the performance of the memory is improved.
[0086] See also Figure 4d As shown, in each second active region 215, a first conductive portion 221 is provided on the first source and drain region 217, and the first source and drain region 217 is connected to a corresponding bit line 205 through the first conductive portion 221. The first conductive portion 221 can ensure reliable connection between the first source and drain region 217 and the bit line 205, thereby reducing contact resistance.
[0087] Please continue reading Figure 4d As shown, in each second active region 215, a second conductive portion 222 is provided on the second source and drain region 218, and the second source and drain region 218 is connected to a corresponding bit line 205 through the second conductive portion 222. The second conductive portion 222 can ensure reliable connection between the second source and drain region 218 and the bit line 205, thereby reducing contact resistance.
[0088] In some embodiments, the first conductive part 221 and the second conductive part 222 are located in the same layer, which can make the memory structure more compact, highly integrated, and more convenient to manufacture.
[0089] See also Figure 4d As shown, a third conductive portion 223 is disposed on the first contact region 204. In each row of the first active region 203 in each storage region 202, the third conductive portion 223 on each first contact region 204 is connected to a bit line 205. The third conductive portion 223 can ensure reliable contact between the first contact region 204 and the bit line 205, thereby reducing contact resistance.
[0090] In some embodiments, the first conductive portion 221 , the second conductive portion 222 , and the third conductive portion 223 are located in the same layer, so that the structure of the memory can be more compact, the integration degree can be higher, and the preparation can be more convenient.
[0091] In some embodiments, the first gate 216 and the second gate 208 are located in the same layer, so that the structure of the memory can be more compact, the integration degree can be higher, and the preparation can be more convenient.
[0092] In some embodiments, a plurality of control areas 201 and a plurality of storage areas 202 are disposed on the substrate 200, and each control area 201 is alternately arranged with each storage area 202. For example, in some embodiments, two control areas 201 and three storage areas 202 are disposed on the substrate 200, and the three storage areas 202 are arranged along the second direction, and a control area 201 is disposed between each two adjacent storage areas 202, so that the control areas 201 and the storage areas 202 are alternately arranged. Arranging multiple control areas 201 and storage areas 202 on the substrate 200 can make the storage speed of the memory faster and improve the storage performance.
[0093] The second aspect of this embodiment also provides a method for preparing a memory, such as Figure 7 As shown, it includes the following steps:
[0094] Step S1, providing a substrate 200;
[0095] In the above step S1 , the material of the substrate 200 may be, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator, and other materials known to those skilled in the art.
[0096] Step S2, forming a control area 201 on the substrate 200 and forming storage areas 202 on both sides of the control area 201; each storage area 202 includes a plurality of first active areas 203, the plurality of first active areas 203 are arranged in a plurality of rows along a first direction, and each control area 201 includes a plurality of second active areas 215 arranged in the first direction and corresponding to the plurality of rows of first active areas 203 one by one;
[0097] In the above step S2, see Figure 2a and Figure 2b As shown, the control area 201 and the storage area 202 include the following steps, for example:
[0098] Step S21, providing a groove on the substrate 200; for example, first, a patterned mask layer is formed on the top surface of the substrate 200 by a photolithography process, and then, an etching process is performed on the substrate 200 using the mask layer to obtain a groove.
[0099] Step S22, filling the trench with an insulating material to form a trench insulating portion 207, wherein the insulating material may be, for example, silicon oxide or silicon nitride. By filling the trench with the insulating material, the substrate 200 provided with the trench can be planarized, and the first active area 203 and the second active area 215 can be effectively electrically isolated. The method of filling the trench with the insulating material is, for example, first, depositing an insulating layer on the substrate 200 provided with the trench by a deposition process, and then removing the insulating layer on the top surface of the substrate 200, leaving only the insulating material in the trench, to form the trench insulating portion 207.
[0100] Of course, after the insulating material is filled in the trench, a high-temperature annealing process may be performed to reduce the pressure on the substrate.
[0101] Step S3, forming a first contact region 204 in each first active region 203, disposing a first gate 216 and a first source / drain region 217 and a second source / drain region 218 located on both sides of the first gate 216 in each second active region 215, and connecting the first gates 216 in the control region 201 to form a control line 219;
[0102] In step S3 above, see Figure 3a and Figure 3b As shown, the specific steps include:
[0103] Step S31: Perform ion implantation twice in the first active region 203 and the second active region 215 to form a first ion doping layer located above and a second ion doping layer located below the first active region 203 and the second active region 215, wherein the first ion doping layer and the second ion doping layer are respectively formed as different types of semiconductors, for example, the first ion doping layer is an n-type semiconductor, and the second ion doping layer is a p-type semiconductor.
[0104] Step S32: forming a second gate groove in each second active area 215, the first ion-doped layer on both sides of the second gate groove forms a first source-drain area 217 and a second source-drain area 218 respectively, and forming a control line groove connected to the gate groove on the trench insulating portion 207 between two adjacent second active areas 215 in each control area 201; the specific preparation process of this step is, for example, first, forming a patterned mask layer by a photolithography process on the top surface of the substrate 200 on which the first ion-doped layer and the second ion-doped layer are formed, and secondly, the substrate 200 on which the first ion-doped layer and the second ion-doped layer are formed is etched by using the mask layer to obtain a first gate groove and a control line groove.
[0105] Step S33: forming a first gate 216 in the first gate groove of the second active area 215, the first gate 216 for example including a gate oxide layer 209, a gate barrier layer 210 and a gate conductive layer 211, and depositing a conductive material in the control line groove, specifically for example including the following steps: first, depositing a layer of gate oxide layer 209 on the substrate 200 provided with the first gate groove and the control line groove by a deposition process, and removing the gate oxide layer 209 on the top surface of the substrate 200 and the gate oxide layer 209 in the control line groove, and only retaining the gate oxide layer 209 in the first gate groove; secondly, continuing to deposit a layer of gate barrier layer 210 by a deposition process, and removing the gate barrier layer 210 on the top surface of the substrate 200 and the gate barrier layer 210 in the control line groove, and only retaining the gate barrier layer 210 in the first gate groove; then, continuing to deposit a layer of gate conductive layer 211 by a deposition process, and removing the gate conductive layer 211 on the top surface of the substrate 200, and only retaining the gate conductive layer 211 in the gate groove and the control line groove.
[0106] Step S34: a gate insulating layer 220 is provided in the first gate groove, specifically including the following steps: first, a back etching process is adopted to make the top surface of the gate oxide layer 209, the top surface of the gate barrier layer 210 and the top surface of the gate conductive layer 211 lower than the notch of the first gate groove, wherein, due to different etching selectivities, the top surface of the gate oxide layer 209, the top surface of the gate barrier layer 210 and the top surface of the gate conductive layer 211 are located at different heights; second, a layer of gate insulating layer 220 is deposited by a deposition process, and the gate insulating layer 220 on the top surface of the substrate 200 is removed, and only the gate insulating layer 220 in the gate groove and the control line groove is retained. The gate insulating layer 220 is used to effectively insulate the gate conductive layer 211.
[0107] It should be explained that the specific steps in the above step S3 are only exemplary steps. In the actual preparation process, the steps can be optimized. If the optimization of such steps is only carried out by changing the pattern of the mask layer, and then forming a control line groove and depositing the gate conductive layer 211 and the gate insulating layer 220 in the control line groove in different steps, they are all within the protection scope of this embodiment. For example, in the specific steps of the above step S3, step S32 includes forming a first gate groove in each second active area 215, and does not include forming a control line groove connected to the first gate groove on the groove insulating portion 207 between two adjacent second active areas 215 in each control area 201; step S33 includes forming a first gate 216 in the first gate groove, and does not include depositing a conductive material in the control line groove, and the specific steps of the above step S3 also include step S35, forming a control line groove connected to the first gate groove on the groove insulating portion 207 between two adjacent second active areas 215 in each control area 201; and step S36, depositing a conductive material in the control line groove.
[0108] Step S4, forming a bit line 205 connected to each first contact area 204 on each row of the first active area 203, and in the same second active area 215, the first source and drain area 217 and the second source and drain area 218 are connected to each corresponding bit line 205, and the bit line 205 connected to the first source and drain area 217 and the bit line 205 connected to the second source and drain area 218 are located on both sides of the control line 219.
[0109] In the above step S4, please refer to Figure 4a , Figure 4b , Figure 4c and Figure 4d As shown, the specific steps include:
[0110] Step S41: forming a bit line 205 on a substrate 200 provided with a control line 219 by means of a photolithography process, an etching process and a deposition process. At this time, among the formed rows of bit lines 205, each bit line 205 is connected to all the first contact areas 204 located in a corresponding row, and all the first contact areas 204 corresponding to a row include the first contact areas 204 of all the storage areas 202 corresponding to a row, and each bit line 205 is also connected to the first source and drain area 217 or the second source and drain area 218 of the corresponding second active area 215.
[0111] Step S42 , cutting off the bit lines 205 on the substrate 200 provided with the bit lines 205 by means of photolithography and etching processes, wherein the cutting position is the position where each bit line 205 intersects with the control line 219 , that is, the bit line 205 is cut off at the bit line 205 directly above the control line 219 .
[0112] In some embodiments, a third ion doping may be performed in the second active region 215 to improve the conductivity of the semiconductor and reduce the contact resistance.
[0113] See also Figure 4b As shown, in each second active region 215 , a first conductive portion 221 is formed on the first source and drain region 217 , and the first source and drain region 217 is connected to a corresponding bit line 205 through the first conductive portion 221 .
[0114] For example, before step S41 of step S4, the following steps are further included:
[0115] First, a patterned mask layer is disposed on the substrate 200 provided with the control line 219, and an opening disposed on the mask layer leaks out the first source and drain region 217;
[0116] Secondly, the upper part of the first source and drain region 217 is etched away using the mask layer, and then the mask layer is removed;
[0117] Then, a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, leaving only the conductive layer in the first source and drain region 217 to form a first conductive portion 221;
[0118] Afterwards, step S41 of the above step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
[0119] See also Figure 4b As shown, in each second active region 215 , a second conductive portion 222 is formed on the second source / drain region 218 , and the second source / drain region 218 is connected to a corresponding bit line 205 through the second conductive portion 222 .
[0120] For example, before step S41 of step S4, the following steps are further included:
[0121] First, a patterned mask layer is disposed on the substrate 200 provided with the control line 219, and an opening disposed on the mask layer leaks out the second source and drain region 218;
[0122] Secondly, the upper part of the second source / drain region 218 is etched away using the mask layer, and then the mask layer is removed;
[0123] Then, a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, leaving only the conductive layer in the second source and drain region 218 to form a second conductive portion 222;
[0124] Finally, step S41 of the above step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
[0125] See also Figure 4b As shown, a third conductive portion 223 is formed on the first contact region 204, and in each row of the first active region 203 in each storage region 202, the third conductive portion 223 on each first contact region 204 is connected to a bit line 205. The third conductive portion 223 can reduce the contact resistance between the first contact region 204 and the bit line 205.
[0126] Specific preparation process, for example:
[0127] First, a patterned mask layer is disposed on the substrate 200 provided with the control line 219, and an opening disposed on the mask layer exposes the first contact region 204;
[0128] Secondly, using the mask layer, an upper half of the first contact region 204 is etched away, and then the mask layer is removed;
[0129] Then, a conductive line layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, leaving only the conductive layer in the first contact area 204 to form a third conductive portion 223;
[0130] Finally, step S41 of the above step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
[0131] See also Figure 4b As shown, in some embodiments, the first conductive part, the second conductive part 222 and the third conductive part 223 can be formed in the same process step. That is, in this embodiment, the preparation process is, for example:
[0132] First, a patterned mask layer is disposed on the substrate 200 provided with the control line 219, and the openings disposed on the mask layer can simultaneously expose the first source and drain regions 217, the second source and drain regions 218, and the first contact region 204;
[0133] Secondly, using the mask layer, an upper portion of the first source and drain region 217, an upper portion of the second source and drain region 218, and an upper portion of the first contact region 204 are etched away, and then the mask layer is removed;
[0134] Then, a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, leaving only the conductive layer in the first source and drain region 217, the conductive layer in the second source and drain region 218, and the conductive layer in the first contact region 204, to form a first conductive portion 221, a second conductive portion 222, and a third conductive portion 223;
[0135] Finally, step S41 of the above step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
[0136] See also Figure 3aAs shown, in the memory prepared by the memory preparation method of the present embodiment, in each storage area 202, a plurality of first active areas 203 are arranged into a plurality of columns along the second direction, and in the first active areas 203 in any two adjacent rows, the column where all the first active areas 203 in one row are located is alternately arranged with the column where all the first active areas 203 in the other row are located, and each first active area 203 in the same column intersects with two word lines 206, and in the first active areas 203 in any adjacent columns, the ends of the first active areas 203 in one column and the first active areas 203 in another column that are close to each other intersect with the same word line 206; two second gates 208 are formed in each first active area 203 in the same column, and the two second gates 208 are respectively connected to the two word lines 206 alternately arranged in the first active area 203. The first contact region 204 on each first active region 203 is located between two second gates on the first active region 203 , that is, the first contact region 204 on each first active region 203 is located between two word lines 206 interlaced with the first active region 203 .
[0137] It should be noted that the first gate 216 and the second gate 208 can be provided in the same process step to simplify the manufacturing process. Figure 3a and 3b As shown, for example, in the aforementioned step S3, step S32 also includes: forming two first gate grooves in each first active area 203, the first ion doping layer between the two first gate grooves forms a first contact area 204, the process of forming the first gate groove on the first active area 203 and the process of forming the second gate groove on the second active area 215 can be the same, only the corresponding improvement is made to the pattern of the mask plate, step S33 also includes, forming a second gate 208 in the first gate groove of the first active area 203, the preparation process of the second gate 208 is exactly the same as the preparation process of the first gate 216, only in the preparation process, the corresponding change is made to the pattern of the mask plate.
[0138] In the above embodiment, two first gate grooves are disposed on the first active region 203 , and the first ion implantation layer on the opposite sides of the two first gate grooves is the second contact region 212 .
[0139] In some embodiments, the memory prepared by the memory preparation method of this embodiment further forms a second contact region 212 located on the side of each second gate 208 away from the first contact region 204 in each first active region 203, and connects each second contact region 212 to a corresponding charge storage element. The charge storage source element is, for example, a capacitor 214.
[0140] See also Figure 5a , Figure 5b , Figure 5cAs shown, the preparation of capacitor 214 is specifically as follows:
[0141] First, a fourth conductive portion 213 is disposed above the second contact region 212 by photolithography, etching, and deposition processes;
[0142] Next, a capacitor 214 is formed on the fourth conductive portion 213 by photolithography, etching and deposition processes.
[0143] See also Figure 5b and Figure 5c As shown, in the memory of this embodiment and the memory prepared by the preparation method thereof, a capacitor 214 is formed only above the second contact area 212 of the first active area 203 in the storage area 202, and no capacitor 214 is arranged above the second active area 215 of the control area 201. Instead, only an insulating layer is deposited accordingly in the control area 201.
[0144] In some embodiments, a plurality of control areas 201 and a plurality of storage areas 202 are formed on the substrate 200, and each control area 201 and each storage area 202 are alternately arranged. Arranging a plurality of control areas 201 and storage areas 202 on the substrate 200 can make the storage speed of the memory faster and improve the storage performance. It should be noted that forming a plurality of control areas 201 and a plurality of storage areas 202 on the substrate 200, for example, setting one control area 201, two storage areas 202, or two control areas 201, three storage areas 202, all use the same preparation steps, which makes the prepared memory faster and improves the performance without increasing the preparation steps.
[0145] The preparation method of the memory of the present embodiment can form the first active area 203 and the second active area 215 in the same process step, form the first contact area 204, the second contact area 212, the first source and drain area 217 and the second source and drain area 218 in the same process step, form the first gate 216 and the second gate 208 in the same process step, form the word line 206 and the control line 219 in the same process step, and form the bit line 205 in the same process step, so that no new process steps are added to the preparation process of the entire memory. Moreover, compared with the first active area 203, the second active area 215 only needs to make corresponding modifications to the structure near the second gate 208. Therefore, only the opening position of the mask in the process needs to be modified accordingly. Moreover, the layout pattern of this mask does not change much compared with the related art. Therefore, the preparation method of the memory of the present embodiment has a simple process and is easy to operate.
[0146] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0147] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A memory, characterized in that: It comprises a base, the base is provided with a control area, and storage areas are respectively provided on both sides of the control area; Each of the storage areas comprises a plurality of first active areas, the plurality of first active areas are arranged into a plurality of rows along a first direction, each of the first active areas is provided with a first contact area, a third conductive portion is provided on the first contact area, and each of the first contact areas in each row of the first active areas is connected to a bit line through the third conductive portion; The control area includes a plurality of second active areas arranged along the first direction and corresponding one-to-one to the plurality of rows of first active areas; Each of the second active regions is provided with a first gate and a first source-drain region and a second source-drain region located on both sides of the first gate, and the first gates in the control region are connected to each other to form a control line; In the same second active region, a first conductive portion is arranged on the first source and drain region, and a second conductive portion is arranged on the second source and drain region, the first conductive portion, the second conductive portion and the third conductive portion are located in the same layer and are formed in the same process step, the first source and drain region is connected to a corresponding one of the bit lines through the first conductive portion, the second source and drain region is connected to a corresponding one of the bit lines through the second conductive portion, and the bit line connected to the first source and drain region and the bit line connected to the second source and drain region are located on both sides of the control line.
2. The memory according to claim 1, characterized in that: In each of the storage areas, a plurality of the first active areas are arranged into a plurality of columns along the second direction, and in any two adjacent rows of the first active areas, the column where all the first active areas of one row are located is alternately arranged with the column where all the first active areas of the other row are located, and each of the first active areas in the same column intersects with the same two word lines, and in any adjacent columns of the first active areas, the ends of the first active areas of one column and the first active areas of another column that are close to each other intersect with the same word line, wherein the second direction is arranged perpendicular to the first direction; Each of the first active regions in the same column is provided with two second gates, and the two second gates are respectively connected to two word lines alternately arranged in the first active region.
3. The memory according to claim 2, characterized in that: The first contact region on each of the first active regions is located between two of the second gates.
4. The memory according to claim 2, characterized in that: The first gate and the second gate are located in the same layer.
5. The memory according to claim 2, characterized in that: Each of the first active regions further includes a second contact region disposed on a side of each of the second gates away from the first contact region, and each of the second contact regions is connected to a corresponding charge storage element.
6. The memory according to any one of claims 1 to 5, characterized in that: A plurality of control areas and a plurality of storage areas are arranged on the substrate, and each of the control areas and each of the storage areas are arranged alternately and spaced apart.
7. A method for preparing a memory, characterized in that: The steps include: providing a substrate; A control area is formed on the substrate, and storage areas are formed on both sides of the control area; each of the storage areas includes a plurality of first active areas, the plurality of first active areas are arranged in a plurality of rows along a first direction, and the control area includes a plurality of second active areas arranged along the first direction and corresponding to the plurality of rows of first active areas one by one; A first contact region is formed in each of the first active regions, a first gate and a first source-drain region and a second source-drain region located on both sides of the first gate are provided in each of the second active regions, and the first gates in the control region are connected to each other to form a control line; forming a first conductive portion located in the first source and drain region, a second conductive portion located in the second source and drain region, and a third conductive portion located in the first contact region in the same process step; A bit line connected to each of the first contact areas through the first conductive portion is formed above each row of the first active areas. In the same second active area, the first source and drain areas are connected to a corresponding bit line through the first conductive portion, and the second source and drain areas are connected to a corresponding bit line through the second conductive portion. The bit line connected to the first source and drain areas and the bit line connected to the second source and drain areas are located on both sides of the control line.
8. The method for preparing a memory according to claim 7, characterized in that: In each of the storage areas, a plurality of the first active areas are arranged into a plurality of columns along the second direction, and in any two adjacent rows of the first active areas, a column where all the first active areas of one row are located is alternately arranged with a column where all the first active areas of the other row are located, and each of the first active areas in the same column is staggered with two word lines, and in any adjacent columns of the first active areas, ends of the first active areas of one column and the first active areas of another column that are close to each other are connected to a word line; Two second gates are formed in each of the first active regions in the same column, and the two second gates are respectively connected to the two word lines alternately arranged in the first active region.
9. The method for preparing a memory according to claim 8, characterized in that: The first contact region on each of the first active regions is located between two of the second gates.
10. The method for preparing a memory according to claim 8, characterized in that: The first gate and the second gate are provided in the same process step.
11. The method for preparing a memory according to claim 8, characterized in that: A second contact region is also formed in each of the first active regions and is located on a side of each of the second gates away from the first contact region, so as to connect each of the second contact regions to a corresponding charge storage element.
12. The method for preparing a memory according to any one of claims 7 to 11, characterized in that: A plurality of control areas and a plurality of storage areas are formed on the substrate, and the control areas and the storage areas are arranged alternately and spaced apart.