Solid-state imaging device and electronic device

Abstract

The present invention relates to a solid-state imaging device and an electronic device. The solid-state imaging device may include: a pixel array unit, the pixel array unit includes a plurality of pixels, the plurality of pixels include a first pixel and a second pixel adjacent to a first side of the first pixel; a first multi-segment light-shielding wall, the first multi-segment light-shielding wall is arranged between the first pixel and the second pixel, the first multi-segment light-shielding wall includes: a first light-shielding wall, the first light-shielding wall penetrates a first film; and a second light-shielding wall, the second light-shielding wall penetrates a second film, and in a cross-sectional view, the second light-shielding wall is offset from the first light-shielding wall in a direction toward the periphery of the pixel array unit; and a first light-shielding film, the first light-shielding film is in contact with a first end of the second light-shielding wall, wherein the width of the first light-shielding film is greater than the maximum width of the second light-shielding wall.

Description

[0001] This application is a divisional application of patent application No. 201680000828.4, filed on January 4, 2016, with the invention name “Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic device”. Technical Field

[0002] The present invention relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device, and in particular, to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device capable of improving oblique light characteristics and sensitivity. Background Art

[0003] Regarding CMOS solid-state imaging devices, front-illuminated type and back-illuminated type are known. In the front-illuminated CMOS solid-state imaging device, by setting the front surface of the substrate as the light receiving surface, light is caused to enter the front surface side of the substrate surface where the multilayer wiring layer and the pixel transistor are formed. In the back-illuminated CMOS solid-state imaging device, by setting the rear surface of the substrate as the light receiving surface, light is caused to enter the rear surface side which is the opposite side of the front surface of the substrate where the multilayer wiring layer and the pixel transistor are formed (for example, see Patent Document 1).

[0004] In the back-illuminated type, light enters the photodiode without being restricted by the multi-layer wiring layer. Therefore, when comparing the two types under the condition of the same pixel pitch, the opening of the photodiode in the back-illuminated type can be formed wider than that of the front-illuminated type, and higher sensitivity than that of the front-illuminated type can be achieved. In addition, since the back-illuminated type has no wiring layer on the light receiving surface side, the height of the focusing structure can be formed to be lower than that of the front-illuminated type, and good oblique light characteristics can be achieved (for example, see non-patent document 1).

[0005] Reference List

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-135101

[0008] Non-patent literature

[0009] Non-patent document 1: The latest trend in CMOS image sensors-high performance, versatile functions, and wide application thereof (2007 CMC Publishing Co., Ltd.) pp. 39-40, S. Iwabuchi et al. ISSCC Dig. Tech. Papers. pp. 302-303, (2006) Summary of the invention

[0010] Technical issues

[0011] However, for example, in an image sensor for a digital single-lens camera, light having an angle greater than the main beam angle of the mounted lens is often unnecessary light, such as reflected light within the camera housing, and in the case where the oblique light characteristic is higher than necessary, the unnecessary light may be detected and the image may be degraded. In the case where the oblique light characteristic is adjusted in a state where the height is lowered, consideration is given to adjusting the width of the light-shielding film between pixels, but since the distance between the on-chip lens and the light-shielding film is close, vignetting may occur at the opening of the light-shielding film, and the sensitivity may be degraded. In the case where the sensitivity is intended to have only light within the required angle range, the width of the light-shielding film between pixels may be adjusted in a state where the height is increased, and the focus may be adjusted to the light receiving surface (opening of the light-shielding film) to a certain extent. However, in this case, there may be a problem of color mixing caused by oblique light between the on-chip lens and the light-shielding film.

[0012] The present invention has been made in view of the above circumstances, and aims to achieve improvements in both oblique light characteristics and sensitivity in a back-illuminated solid-state imaging device.

[0013] Technical Solution

[0014] A solid-state imaging device according to a first aspect of the present invention includes a pixel array unit in which a plurality of pixels are arranged in a matrix in a two-dimensional manner and a plurality of sections of light shielding walls are provided between the pixels.

[0015] In the method for manufacturing a solid-state imaging device according to the second aspect of the present invention, when forming a pixel array unit in which a plurality of pixels are two-dimensionally arranged in a matrix, a plurality of stages of light shielding walls are formed between the pixels.

[0016] An electronic device according to a third aspect of the present invention includes a solid-state imaging device including a pixel array unit in which a plurality of pixels are two-dimensionally arranged in a matrix and a plurality of sections of light shielding walls are provided between the pixels.

[0017] According to the first to third aspects of the present invention, in the pixel array unit in which a plurality of pixels are arranged in a matrix in a two-dimensional manner, a plurality of stages of light shielding walls are formed between the pixels.

[0018] The solid-state imaging device and the electronic device may be independent devices, or may be modules incorporated in different devices.

[0019] Beneficial Effects

[0020] According to the first to third aspects of the present invention, both oblique light characteristics and sensitivity can be improved.

[0021] Note that the effects described herein are not necessarily limited thereto, and may be any effects described in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic configuration of a solid-state imaging device according to the present invention is shown.

[0023] Figure 2 is a cross-sectional view showing the structure of a pixel according to the first embodiment.

[0024] Figure 3 is a plan view showing a light-shielding film.

[0025] Figure 4 1 is an explanatory diagram of a method for manufacturing a pixel according to the first embodiment.

[0026] Figure 5 1 is an explanatory diagram of a method for manufacturing a pixel according to the first embodiment.

[0027] Figure 6 1 is an explanatory diagram of a method for manufacturing a pixel according to the first embodiment.

[0028] Figure 7 It is an explanatory diagram of the light receiving characteristics when a single-stage light shielding wall is formed and when a multi-stage light shielding wall is formed.

[0029] Figure 8 is a cross-sectional view showing the structure of a pixel according to the second embodiment.

[0030] Fig. 9 is a cross-sectional view showing the structure of a pixel according to the third embodiment.

[0031] Fig.10 is a cross-sectional view showing the structure of a pixel according to the fourth embodiment.

[0032] Fig.11 This is a diagram for explaining the pixel structure of a phase difference pixel.

[0033] Fig.12 This is an explanatory diagram of a method for forming an inner lens.

[0034] Fig.13 This is an explanatory diagram of the shape of the on-chip lens.

[0035] Fig.14 The relationship between the range-allowed limit and the flatness ratio during phase-difference autofocusing is shown.

[0036] Fig.15 A first exemplary configuration of a light shielding structure in the OPB region is illustrated.

[0037] Fig.16A second exemplary configuration of the light shielding structure in the OPB region is illustrated.

[0038] Fig.17 Picture shows Fig.16 A method for manufacturing a light shielding structure in an OPB region is shown.

[0039] Fig.18 Other exemplary structures of light-shielding walls in the OPB region are shown.

[0040] Fig.19 An exemplary substrate configuration of a solid-state imaging device is shown.

[0041] Fig. 20 is a block diagram showing an exemplary configuration of an imaging device as an electronic device according to the present invention. DETAILED DESCRIPTION

[0042] Modes for carrying out the present invention (hereinafter referred to as embodiments) will be described below. Note that the description will be given in the following order.

[0043] 1. Exemplary Schematic Configuration of Solid-State Imaging Device

[0044] 2. First Embodiment of Pixel (Exemplary Structure Not Including Inner Lens)

[0045] 3. Method for manufacturing pixel according to first embodiment

[0046] 4. Second Embodiment of Pixel (First Exemplary Structure Including Inner Lens)

[0047] 5. Third Embodiment of Pixel (Second Exemplary Structure Including Inner Lens)

[0048] 6. Fourth Embodiment of Pixel (Including Third Exemplary Structure of Inner Lens)

[0049] 7. Pixel structure of phase difference pixel

[0050] 8. Method for forming inner lens

[0051] 9. Shape of on-chip lens

[0052] 10. Shading structure in OPB area

[0053] 11. Exemplary Substrate Configuration of Solid-State Imaging Device

[0054] 12. Exemplary application examples of electronic devices

[0055] 1. Exemplary Schematic Configuration of Solid-State Imaging Device

[0056] Figure 1 A schematic configuration of a solid-state imaging device according to the present invention is shown.

[0057] Figure 1 The solid-state imaging device 1 in the embodiment is formed to include a pixel array unit 3 and a peripheral circuit unit on its periphery. In the pixel array unit 3, for example, on a semiconductor substrate 12 using silicon (Si) as a semiconductor, a plurality of pixels 2 are two-dimensionally arranged in a matrix. The peripheral circuit unit includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0058] The pixel 2 is formed to include a plurality of pixel transistors and a photodiode as a photoelectric conversion element. For example, the plurality of pixel transistors are formed of four MOS transistors including a transfer transistor, a selection transistor, a reset transistor, and an amplifier transistor.

[0059] In addition, the pixel 2 may have a shared pixel structure. The shared pixel structure is formed by a plurality of photodiodes, a plurality of transfer transistors, a shared floating diffusion (floating diffusion region), and another pixel transistor shared in each structure. More specifically, in the shared pixel structure, the photodiodes and transfer transistors constituting the plurality of unit pixels are formed in a manner that another pixel transistor is shared in each structure.

[0060] The control circuit 8 receives data such as an input clock and a command operation mode, and also outputs data such as internal information of the solid-state imaging device 1. More specifically, the control circuit 8 generates a clock signal and a control signal as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock. In addition, the control circuit 8 outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0061] For example, the vertical drive circuit 4 is formed of a shift register, and selects a predetermined pixel drive line 10, supplies a pulse to the selected pixel drive line 10 to drive the pixel 2, and drives the pixel 2 in units of rows. More specifically, the vertical drive circuit 4 selectively and sequentially scans the respective pixels 2 in the pixel array unit 3 in the vertical direction in units of rows, and supplies the pixel signal to the column signal processing circuit 5 via the vertical signal line 9 based on the signal charge generated in the photoelectric conversion unit in each pixel 2 according to the light reception amount.

[0062] For example, the column signal processing circuit 5 is arranged for each column of pixels 2, and is adapted to perform signal processing for each pixel column, such as noise elimination for a signal output from a row of pixels 2. The column signal processing circuit 5 performs signal processing such as AD conversion and correlated double sampling (CDS) to remove fixed pattern noise specific to a pixel.

[0063] The horizontal drive circuit 6 is formed of a shift register, for example, and sequentially selects the respective column signal processing circuits 5 by sequentially outputting horizontal scanning pulses and causes the respective column signal processing circuits 5 to output pixel signals to the horizontal signal lines 11 .

[0064] The output circuit 7 performs signal processing on the signals sequentially supplied from the respective column signal processing circuits 5 via the horizontal signal line 11, and outputs the signal processed. For example, the output circuit 7 may perform only buffering, or may perform black level adjustment, correction of column variation, various types of digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0065] The solid-state imaging device 1 thus configured is a CMOS image sensor in a so-called AD system in which a column signal processing circuit 5 adapted to perform CDS processing and AD conversion processing is arranged for each pixel column.

[0066] 2. First Embodiment of Pixel

[0067] Cross-sectional view of the structure of a pixel

[0068] Figure 2 is a cross-sectional view showing the structure of the pixel 2 according to the first embodiment.

[0069] In the solid-state imaging device 1, for example, a photodiode PD is formed for each pixel by forming an n-type (second conductivity type) semiconductor region 42 for each pixel 2 in a p-type (first conductivity type) semiconductor region 41 of a semiconductor substrate 12. The p-type semiconductor region 41 facing both the front and rear surfaces of the semiconductor substrate 12 also serves as a positive hole charge accumulation region to suppress dark current.

[0070] The front surface side 9 (lower side in the figure) of the semiconductor substrate 12 is formed with: a plurality of pixel transistors Tr adapted to read the charges accumulated in the photodiodes PD; and a multilayer wiring layer 45 including an interlayer dielectric film 44 and a plurality of wiring layers 43 .

[0071] Since light does not enter the multilayer wiring layer 45 side of the semiconductor substrate 12 , the layout of the wiring layer 43 can be arbitrarily set without limitation.

[0072] The insulating layer 46 is formed on the boundary surface on the rear surface side (upper side in the figure) of the semiconductor substrate 12. Figure 2 In the example of FIG. 4 , the insulating layer 46 is formed of a plurality of layers having different refractive indices, for example, two layers including a hafnium dioxide (HfO 2 ) film 48 and a silicon oxide film 47 , and the insulating layer 46 optically functions as an antireflection film.

[0073] A planarization film 49 is formed on the upper surface of the insulating layer 46, and an inter-pixel light-shielding film 50 is formed at a pixel boundary portion on the planarization film 49. The inter-pixel light-shielding film 50 needs to be at least a light-shielding material, and preferably the inter-pixel light-shielding film is formed of a film of a metal such as aluminum (Al), tungsten (W), or copper (Cu), which is a material having a high light-shielding property and can be accurately processed by fine processing such as etching.

[0074] like Figure 3 As shown, the inter-pixel light shielding film 50 and the optical black (OPB: optical black) film 51 outside the pixel effective area and the phase difference pixel 2P ( Fig.11 The pupil division shading film 52 of the phase difference pixel 2P is in the same layer and can be formed together at the same time. The inter-pixel shading film 50 suppresses color mixing between pixels and light of the light spot component incident at an unexpected angle. By covering the outside of the pixel effective area, the OPB forming film 51 forms an OPB clamp region suitable for detecting the black level as a reference for output in the dark. The pupil division shading film 52 divides the light from different viewpoints in the phase difference pixel 2P.

[0075] For example, Figure 3 As shown, there are two types of phase difference pixels 2P formed by the pupil-dividing light-shielding film 52: type A in which the left half of the light-receiving surface of the photodiode PD is open; and type B in which the right half of the light-receiving surface of the photodiode PD is open. These two types of phase difference pixels are arranged in pairs at predetermined positions of the pixel array unit 3. Since the positions at which the openings are formed are different, an image displacement occurs between the pixel signal from type A and the pixel signal from type B. Based on the image displacement, the defocus amount is calculated by calculating the phase shift amount, and autofocus is achieved by adjusting (moving) the photographic lens.

[0076] It is needless to say that the inter-pixel light shielding film 50, the OPB forming film 51, and the pupil division light shielding film 52 do not need to be formed at the same time, and these films can be formed separately. In addition, for example, in the case where sensitivity is improved by suppressing color mixing and light spots, the mesh width in the inter-pixel light shielding film 50 can be formed to be shorter.

[0077] Return to reference Figure 2 As described above, a multi-layered light shielding wall 61 and a planarization film 62 are formed in multiple stages on the inter-pixel light shielding film 50 and the insulating layer 46. More specifically, in the portion on the inter-pixel light shielding film 50, a first light shielding wall 61A is formed, and a first planarization film 62A is also formed between the first light shielding walls 61A. In addition, a second light shielding wall 61B and a second planarization film 62B are formed on the first light shielding wall 61A and the first planarization film 62A.

[0078] On the upper surfaces of the second light shielding wall 61B and the second planarizing film 62B, a color filter 71 is formed for each pixel. For the array of the color filter 71, for example, red (R), green (G), and blue (B) are arranged in a Bayer array, but the arrangement may also be based on a different arrangement method.

[0079] Compared with Figure 3 In the same plane direction of the inter-pixel light shielding film 50 shown, the first light shielding wall 61A and the second light shielding wall 61B are formed in a grid at the pixel boundary portion.

[0080] The second light shielding wall 61B located at the uppermost stage among the multiple stages may have a shape protruding from the second planarizing film 62B toward the layer of the color filter 71 to provide light shielding between adjacent color filters 71 .

[0081] The on-chip lens 72 is formed on the color filter 71 for each pixel. As for the material of the on-chip lens 72, for example, organic materials such as styrene resin, acrylic resin, styrene-acrylic copolymer resin, and siloxane resin can be applied. The refractive index of styrene resin is about 1.6, and the refractive index of acrylic resin is about 1.5. The refractive index of styrene-acrylic copolymer resin is about 1.5 to 1.6, and the refractive index of siloxane resin is about 1.45.

[0082] Alternatively, as for the organic material, an organic-inorganic hybrid material obtained by dispersing TiO fine particles in the above-mentioned resin and polyamide resin may also be used.

[0083] Alternatively, inorganic materials such as SiN and SiON may be used as the material of the on-chip lens 72. The refractive index of SiN is approximately 1.9 to 2.0, and the refractive index of SiON is approximately 1.45 to 1.9.

[0084] The surface of the on-chip lens 72 is covered with an anti-reflection film 73 .

[0085] In the drawing, a first light shielding wall 61A, a second light shielding wall 61B, a color filter 71 , and an on-chip lens 72 formed on the upper side of the inter-pixel light shielding film 50 are formed to perform pupil correction.

[0086] More specifically, since the incident angle of the main beam of incident light from the optical lens (not shown) becomes zero degrees at the center of the pixel array unit 3, there is no need to perform pupil correction, and the center of the photodiode PD coincides with the center of the color filter 71 and the on-chip lens 72.

[0087] On the other hand, since the incident angle of the main beam of the incident light from the optical lens has a predetermined angle according to design in the peripheral portion (outer peripheral portion) of the pixel array unit 3, pupil correction is performed. More specifically, as Figure 2 As shown in FIG. 1 , the centers of the color filter 71 and the on-chip lens 72 are arranged so as to deviate from the center of the photodiode PD toward the center side of the pixel array unit 3. As the position approaches the periphery of the pixel array unit 3, the deviation between the center position of the photodiode PD and the center position of the color filter 71 and the on-chip lens 72 becomes larger.

[0088] Additionally, according to such deviation of the color filter 71 and the on-chip lens 72 , the positions of the first light shielding wall 61A and the second light shielding wall 61B also deviate toward the center side as the positions approach the outer periphery of the pixel array unit 3 .

[0089] at the same time, Figure 2 The pixel structure shown is that the light shielding wall 61 is formed to include two segments of a first light shielding wall 61A and a second light shielding wall 61B, but the light shielding wall can be formed in an optional number of segments (Q segments (Q>2)). Hereinafter, the layer formed with the light shielding wall 61 is also referred to as a light shielding wall layer.

[0090] Regarding pupil correction of the light shielding walls 61 , by applying an optimum correction amount at the height of each light shielding wall 61 for any image height, it is possible to minimize sensitivity loss in the peripheral portion (edge ​​of the viewing field) of the pixel array unit 3 .

[0091] For any image height, the more the number of stages of the light shielding wall 61 increases (in other words, the closer the position is to the color filter 71), the greater the pupil correction amount. However, the pupil correction amount of the light shielding wall 61 at the uppermost stage is equal to or smaller than the pupil correction amount of the color filter 71.

[0092] In addition, regarding the pupil correction amount of the color filter 71, when the correction amount is large, there is a problem of color mixing caused by the color filter 71 of the own pixel entering the area surrounded by the light shielding wall 61 of the adjacent pixel. Therefore, the pupil correction amount of the color filter 71 is set within a range from the same correction amount as the uppermost light shielding wall 61 closest to the color filter 71 to the correction amount obtained by adding the half width of the uppermost light shielding wall 61 to the pupil correction amount of the uppermost light shielding wall 61. More specifically, assuming that the pupil correction amount and the width of the uppermost light shielding wall 61 are C and X, the color filter 71 is formed so that the pupil correction amount D of the color filter 71 becomes C≤D≤C+X / 2.

[0093] The pupil correction amount increases in the following order: inter-pixel light shielding film 50 ≤ first-stage light shielding wall 61 ≤ second-stage light shielding wall 61 ≤ ... ≤ uppermost light shielding wall 61 ≤ color filter 71 ≤ on-chip lens 72 .

[0094] In addition, in the case where a section of the light shielding wall 61 has the same height and the material of the planarizing film 62 is the same, preferably, the pupil correction amount of the light shielding wall 61 is proportional to the height of the layer where the light shielding wall 61 is located.

[0095] Additionally, when strong light such as sunlight enters the edge of the field of view, there is a problem of color mixing effects such as flare, because the light enters in a direction different from the normal light incident from the lens due to the reflected light inside the camera housing (the different direction may be the direction opposite to the pupil correction direction). Therefore, in order to handle incident light from various directions, preferably, the pupil correction of the color filter 71 is the same as the correction amount of the uppermost light shielding wall 61 located below the color filter 71.

[0096] Since the pupil correction amount is large at the edge of the field of view, the upper light shielding wall 61 does not overlap with the light shielding wall 61 of the next stage at all, and the upper light shielding wall 61 is in a state of being separated from the light shielding wall 61 of the next stage. In this case, there is a problem that arcing may occur when etching the flattening film 62 when the light shielding wall 61 is patterned. However, at the center of the image height, the pupil correction amount of the light shielding wall 61 of each stage becomes almost equal, and the wall of the lower stage is obviously connected, and the upper light shielding wall 61 and the lower light shielding wall 61 that have been connected have the same potential. Therefore, there is no problem of arcing.

[0097] In addition, when the light shielding wall 61 is patterned, a forward tapering process is adopted during etching of the planarization film 62. In the forward tapering process, as the position approaches the upper side from the bottom surface, the area in the plane direction of the light shielding wall 61 is formed larger. Therefore, the small bottom surface of the upper light shielding wall 61 can be supported by the upper surface of the lower light shielding wall 61 having a larger area than the small bottom surface. Therefore, the risk of the upper light shielding wall 61 being separated from the light shielding wall 61 of the next stage can be reduced, and the metal embedding characteristics are improved, and the processing margin can also be ensured.

[0098] The pixel structure of the solid-state imaging device 1 is formed as described above, and the solid-state imaging device 1 is a back-illuminated MOS solid-state imaging device in which light is incident from the rear surface side of the semiconductor substrate 12 opposite to the front surface side where the pixel transistor Tr is formed.

[0099] In addition, the solid-state imaging device 1 has a structure in which at least two stages of light shielding walls 61 adapted to block incidence of oblique light from adjacent pixels are provided separately from the inter-pixel light shielding film 50 .

[0100] 3. Method for manufacturing pixel according to first embodiment

[0101] Next, we will refer to Figures 4 to 6 A method for manufacturing the pixel 2 according to the above-described first embodiment will be described.

[0102] First, if Figure 4 As shown in A, on the semiconductor substrate 12, an n-type semiconductor region 42 is formed on the p-type semiconductor region 41 for each pixel 2, thereby forming a photodiode PD for each pixel. For example, a plurality of pixel transistors Tr suitable for reading the charge accumulated in the photodiode PD, and a multilayer wiring layer 45 including a plurality of wiring layers 43 and an interlayer dielectric film 44 are formed on the front surface side of the semiconductor substrate 12 (the lower side of the figure). In addition, an insulating layer 46 and a planarization film 49 are formed on the rear surface side of the semiconductor substrate 12 (the upper side of the figure). Until this step, the pixel can be formed by the same method as in the case of forming a normal back-illuminated solid-state imaging device.

[0103] Below, as Figure 4 As shown in FIG. 8B , in the pixel boundary portion on the planarization film 49 , an inter-pixel light shielding film 50 is formed of a metal material such as aluminum (Al), tungsten (W), or copper (Cu).

[0104] Next, an inorganic material film such as SiO2 is formed as the planarization film 62A, and then planarization is performed by chemical mechanical polishing (CMP) or the like, thereby forming a planarization layer on the upper surface of the inter-pixel light shielding film 50. Figure 4 As shown in FIG. 3C , a predetermined portion of the inter-pixel light shielding film 50 is etched to form an opening 101 which is a portion opened in the planarizing film 62A where the first light shielding wall 61A is to be formed.

[0105] Next, a metal material such as tungsten or copper is embedded in the opening 101, and then the entire surface is subjected to chemical mechanical polishing (CMP), thereby forming a Figure 4 The first light shielding wall 61A is shown in FIG.

[0106] Meanwhile, for example, when a metal material is buried in the opening 101, TiN is formed as an adhesion layer on the inner peripheral surface. At this time, the effect of reducing unnecessary light by reducing reflection can be expected by the adhesion layer.

[0107] In addition, in the case where aluminum is used as the metal material of the first light shielding wall 61A, the planarization film 62A can be formed after the first light shielding wall 61A is first formed. More specifically, first, an aluminum film to be the first light shielding wall 61A is formed to a desired height on the entire surface, and the first light shielding wall 61A is formed by planarization by photolithography. Thereafter, an inorganic material such as SiO2 to be the planarization film 62A is buried between the formed first light shielding walls 61A, and the entire surface is planarized by CMP, thereby forming a planarization film 62A as shown in FIG. Figure 4 The subject shown in D.

[0108] Although the first light-shielding wall 61A uses the inter-pixel light-shielding film 50 as a base during the etching process, even if the inter-pixel light-shielding film 50 is not formed due to sensitivity priority, the first light-shielding wall 61A can be formed by fixing the time for the etching process when patterning the first light-shielding wall 61A, or by using an insulating layer such as SiN on the photodiode PD as a stop layer to stop etching.

[0109] By repeated reference Figure 4 C and Figure 4 The steps described in D form Figure 5 The second light shielding wall 61B and the second planarizing film 62B of the second segment shown in A. In the case of forming more than three segments of the light shielding wall 61 and the planarizing film 62, the same steps are repeated. At the same time, due to the coverage of the barrier metal and the thickness of the resist film, preferably, the height of one segment of the light shielding wall 61 is 2um or less.

[0110] Below, as Figure 5 As shown in FIG. 1B, a color filter 71 is formed on the second light shielding wall 61B and the second planarizing film 62B of the second stage by rotationally coating a photosensitive resin containing a pigment such as a colorant and a dye. Preferably, from the viewpoint of anti-color mixing at a large incident angle, the gap between the color filter 71 and the second light shielding wall 61B of the uppermost stage is formed to be as small as possible.

[0111] In the case where the second light shielding wall 61B of the uppermost stage is formed in a manner protruding from the second planarizing film 62B toward the layer of the color filter 71 to shield the light between the adjacent color filters 71, the film formation is performed by burying the metal material to be the second light shielding wall 61B, and then only the opening portion of the pixel is etched and removed by photolithography so that the metal material remains in the upper portion of the light shielding wall between the pixels. Thus, the protruding portion of the second light shielding wall 61B is formed, and the color filter 71 is buried between the second light shielding walls 61B.

[0112] Then, if Figure 5 As shown in FIG. 7C, an on-chip lens material 102 and a photoresist 103 are formed on the color filter 71. As described above, a resin-based organic material, an inorganic material such as SiN, and an organic / inorganic hybrid material can be used for the on-chip lens material 102. In addition, as the photoresist 103, a photosensitive material mainly containing a phenolic resin can be used.

[0113] like Figure 6As shown in A of FIG. 1 , the photoresist 103 is heat-treated at a temperature higher than the thermal softening point to form the photoresist 103 into a lens-like shape. Next, the photoresist 103 having the lens-like shape is used as a mask, and a dry etching method is used to perform pattern transfer of the lens-like shape to the on-chip lens material 102 of the underlying layer, thereby forming a lens-like shape. Figure 6 The on-chip lens 72 is shown in B.

[0114] Note that the method for forming the on-chip lens 72 is not limited to the above method. For example, a method may be employed in which, after sequentially performing processes including film formation of a lens material formed of a photosensitive resin, prebaking, exposure, development, and bleaching exposure processing, heat treatment is performed at a temperature higher than or equal to the thermal softening point of the photosensitive resin.

[0115] As described above, it is possible to manufacture Figure 2 The cross-sectional structure of pixel 2 is shown.

[0116] Comparison with single-stage shading wall

[0117] Figure 7 Distributions of light receiving characteristics for a case where a single-stage light shielding wall 61 is formed and a case where a plurality of stages (two stages) of light shielding walls 61 are formed (such as the pixel structure in the present invention) are illustrated.

[0118] The pixel structure of the present invention includes a multi-stage light shielding wall 61, and different pupil corrections are set for each light shielding wall 61. More specifically, the multi-stage light shielding wall 61 has a stacked structure near the center (viewing field center) of the pixel array unit 3, and the closer the position is to the periphery (viewing field edge) of the pixel array unit 3, the more the upper stage light shielding wall 61 deviates toward the center side of the pixel array unit 3 relative to the lower stage light shielding wall 61. The higher the number of stages, the greater the pupil correction amount, and the pupil correction amount of the uppermost stage is equal to or less than the pupil correction amount of the color filter.

[0119] like Figure 7 As shown, when a single-stage light shielding wall 61 is formed, vignetting and leakage of incident light may occur at the edge of the viewing field, as shown in the distribution of light receiving characteristics, sensitivity deteriorates, and shadows may appear at the edge of the viewing field.

[0120] In contrast, when a plurality of (at least two) light shielding walls 61 are formed (as in the pixel structure of the present invention), it is possible to change the pupil correction amount of each light shielding wall 61. Therefore, since light can enter the photodiode PD without leakage, it is possible to prevent sensitivity degradation even at the edge of the field of view.

[0121] Therefore, according to Figure 2The pixel structure of the pixel 2 of the first embodiment shown can solve the problem of color mixing of adjacent pixels and suppress shadows at the edge of the viewing field.

[0122] Furthermore, since the amount of pupil correction of each stage of the light shielding wall 61 can be changed, the degree of freedom in the light focusing design can be increased.

[0123] Furthermore, since a plurality of light shielding walls 61 are formed, the aspect ratio (ratio between width and depth in the plane direction) of each light shielding wall 61 can be reduced, and the embedding property and processing margin of the metal material can be ensured when forming the light shielding wall 61. Therefore, the processing margin can be expanded, and process construction can be facilitated.

[0124] 4. Second Embodiment of Pixel

[0125] Figure 8 is a cross-sectional view showing the structure of a pixel 2 according to the second embodiment.

[0126] The pixel 2 according to the second embodiment is formed of a light shielding wall 61 having three stages, and an inner lens 121 is formed on one of the stages.

[0127] More specifically, the second light-shielding wall 61B and the second planarizing film 62B as the second light-shielding wall layer are formed on the first light-shielding wall 61A and the first planarizing film 62A as the first light-shielding wall layer, and the third light-shielding wall 61C and the third planarizing film 62C as the third light-shielding wall layer are formed on the second light-shielding wall 61B and the second planarizing film 62B.

[0128] In addition, Figure 8 In the pixel structure of A, the inner lens 121 is formed in the middle layer (second light-shielding wall layer) of the three-stage light-shielding wall layers.

[0129] In contrast, Figure 8 In the pixel structure of B, the inner lens 121 is formed in the uppermost layer (third light-shielding wall layer) of the three-stage light-shielding wall layer.

[0130] In addition, Figure 8 In the pixel structure of C, the inner lens 121 is formed in the lowest layer (first light shielding wall layer) of the three-stage light shielding wall layer.

[0131] At the same time, although Figure 8 A to Figure 8 In the example of C, each pixel 2 includes the inner lens 121 in one of the three-stage light shielding wall layers, but the pixel 2 may not include the inner lens 121.

[0132] 5. Third Embodiment of Pixel

[0133] Fig. 9 is a cross-sectional view showing the structure of a pixel 2 according to the third embodiment.

[0134] The pixel structure of the third embodiment has Figure 8 The same structure as the second embodiment is shown, in which the light shielding wall 61 is formed into three stages.

[0135] However, the pixel structure of the third embodiment is different from that of the second embodiment in that the light shielding wall layer in which the inner lens 121 is to be formed among the three stages of the light shielding wall layer varies according to the color of the color filter 71 .

[0136] Fig. 9 A is a cross-sectional view showing the structure of two pixels in a pixel row in which G and R color filters 71 are alternately arranged, Fig. 9 B is a cross-sectional view showing the structure of two pixels in a pixel row in which G and B color filters 71 are alternately arranged.

[0137] like Fig. 9 A and Fig. 9 As shown in FIG. 1B , in the pixel 2 formed with the R color filter 71, the inner lens 121 is formed on the uppermost layer (third light-shielding wall layer) of the three-stage light-shielding wall layer, and in the pixel 2 formed with the G color filter 71, the inner lens 121 is formed on the middle layer (second light-shielding wall layer). In addition, in the pixel 2 formed with the B color filter 71, the inner lens 121 is formed on the lowermost layer (first light-shielding wall layer).

[0138] therefore, Fig. 9 The inner lens 121 in the embodiment is arranged in such a manner that the longer the wavelength, the higher the inner lens 121 is located. The higher the light shielding wall layer where the inner lens 121 is located, the better the effect of bending light can be provided. Therefore, the longer the wavelength of light, the more chromatic aberration can be reduced by focusing light earlier (on the upper layer side) using the inner lens 121.

[0139] 6. Fourth Embodiment of Pixel

[0140] Fig.10 is a cross-sectional view showing the structure of a pixel 2 according to the fourth embodiment.

[0141] The pixel structure of the fourth embodiment has the same Figure 8 The same structure as the second embodiment is shown, wherein the light shielding wall 61 is formed into three sections.

[0142] The pixel structure of the fourth embodiment is different from that of the second embodiment in that the inner lens 121 is formed on a plurality of light shielding wall layers in the three-stage light shielding wall layer.

[0143] exist Fig.10In the pixel structure of A, the inner lens 121 is formed in the middle layer (the second light-shielding wall layer) and the lowermost layer (the first light-shielding wall layer) of the three-stage light-shielding wall layer.

[0144] exist Fig.10 In the pixel structure of B, the inner lens 121 is formed in all layers (the first light-shielding wall layer to the third light-shielding wall layer) of the three-stage light-shielding wall layer.

[0145] exist Fig.10 In the pixel structure of C, the light-shielding wall layer in which the inner lens 121 is to be formed among the three light-shielding wall layers changes according to the color of the color filter 71. More specifically, in the pixel 2 formed with the R color filter 71, the inner lens 121 is formed on the lowermost layer (the first light-shielding wall layer) and the uppermost layer (the third light-shielding wall layer), and in the pixel 2 formed with the G color filter 71, the inner lens 121 is formed on the middle layer (the second light-shielding wall layer) and the lowermost layer (the first light-shielding wall layer).

[0146] Note that the number of segments of the light-shielding wall layer and the light-shielding wall layer where the inner lens 121 is to be formed can be appropriately selected and determined without being limited to Figures 8 to 10 Example shown.

[0147] 7. Pixel structure of phase difference pixel

[0148] Will refer to Fig.11 The pixel structure of the phase difference pixel 2P will be described.

[0149] exist Fig.11 In FIG. 1 , for the sake of comparison, a normal pixel 2X for outputting a pixel signal for image formation and a phase difference pixel 2P for outputting a phase difference signal are shown in parallel.

[0150] Fig.11 A in FIG. 1 shows that Figure 2 The pixel structure of the phase difference pixel 2P is shown in the first embodiment when the inner lens 121 is not included.

[0151] Fig.11 B in FIG. 1 shows a pixel structure of a phase difference pixel 2P including an inner lens 121 as in the second embodiment. Fig.11 B in FIG. 1 is an example in which the light shielding wall layer including the inner lens 121 is the same in both the normal pixel 2X and the phase difference pixel 2P. However, the light shielding wall layer including the inner lens 121 may be different between the normal pixel 2X and the phase difference pixel 2P.

[0152] Fig.11 C in FIG. 1 shows a pixel structure in which an inner lens 121 is provided in a normal pixel 2X but an inner lens 121 is not provided in a phase difference pixel 2P. Fig.11In C, as in the phase difference pixel 2P, although the material of the inner lens 121 is formed flat and remains, the material of the inner lens 121 may be removed.

[0153] In the phase difference pixel 2P, the pupil dividing light shielding film 52 is as shown in FIG. Figure 3 It is illustrated that it is formed on the same plane as the inter-pixel light shielding film 50. Fig.11 In the example of FIG. 5 , the pupil dividing light shielding film 52 shields light at the right half of the photodiode PD.

[0154] In addition, in the phase difference pixel 2P, a different material 141 is embedded relative to the color filter 71 portion of the normal pixel 2X. For example, the material 141 of the color filter 71 portion of the phase difference pixel 2P may be a cyan color filter material to improve the sensitivity in the phase difference pixel 2P and improve the low brightness performance in the phase difference pixel 2P. Alternatively, the same material as the upper on-chip lens 72 may be embedded as the material 141 of the color filter 71 portion of the phase difference pixel 2P.

[0155] Since the pupil-dividing shading film 52 is additionally provided, the phase difference pixel 2P is affected by the light blocking and reflection of the pupil-dividing shading film 52 compared with the ordinary pixel 2X, and there may be a problem of outputting an image in which the peripheral portion of the phase difference pixel 2P appears to be lifted.

[0156] However, by providing a multi-stage light shielding wall 61 as in the present invention, the normal pixel 2X can prevent color mixing caused by light from the phase difference pixel 2P. In addition, by providing a multi-stage light shielding wall 61, the focus can be set arbitrarily without considering the influence of the periphery. Therefore, since the focus can be adjusted to the pupil division light shielding film 52, the separation characteristics can be optimized.

[0157] In the normal pixel 2X, the pupil correction amount can be changed in each of the multi-stage light shielding wall 61. Therefore, the degree of freedom of the focusing design can be improved, and color mixing and shadow degradation can be prevented. Therefore, the oblique light characteristics and sensitivity can be improved, and both the normal pixel characteristics and the phase difference pixel characteristics can be realized.

[0158] In addition, in Fig.11 B and Fig.11 When the inner lens 121 is provided in the normal pixel 2X as in C in FIG. 1 , it is possible to maintain or control the separation characteristics of the phase difference pixel 2P while improving the oblique light characteristics of the normal pixel 2X.

[0159] 8. Method for forming inner lens

[0160] Will refer to Fig.12 A method of forming the inner lens 121 in the case where the inner lens 121 is provided in the light shielding wall layer will be described.

[0161] Fig.12 The formation method is shown in the case where the inner lens 121 is provided in the second stage of the light shielding wall layer among the two stages of the light shielding wall layer.

[0162] First, if Fig.12 As shown in FIG. 1A , the manufacturing is performed until the first light shielding wall layer (the first light shielding wall 61A and the first planarization film 62A) is formed, and then a film of the inner lens material 121A is formed on the formed first light shielding wall layer. As for the inner lens material 121A, an inorganic material such as SiN and SiON can be used.

[0163] Next, with reference Figure 6 A and Figure 6 The method for forming the on-chip lens 72 described in B is the same as that for transferring the lens shape pattern of the photoresist (not shown), thereby forming a Fig.12 The inner lens 121 is shown in B.

[0164] Preferably, the pupil correction amount of the inner lens 121 is the same as the pupil correction amount of the light-shielding wall 61 having the light-shielding wall layer of the inner lens 121, so that even if there is a processing difference between the light-shielding wall layers, the light-shielding wall 61 can be prevented from being formed on the inner lens 121. In the case where the processing difference is not significant, there is no problem in adopting a pupil correction amount different from the pupil correction amount of the light-shielding wall 61 having the light-shielding wall layer of the inner lens 121 as the pupil correction amount of the inner lens 121.

[0165] Below, as Fig.12 As shown in FIG. 3C, a second planarization film 62B is formed on the inner lens 121 formed, and as shown in FIG. Fig.12 As shown in D, the formed second planarizing film 62 is planarized by CMP or the like.

[0166] After this, if Fig.12 As shown in E, refer to Figure 4 C and Figure 4 The second light shielding wall 61B is formed in the same manner as described in FIG.

[0167] After that, the color filter 71 and the on-chip lens 72 (not shown) are sequentially formed in the same manufacturing method as the pixel 2 according to the above-described first embodiment.

[0168] Fig.12 This is a forming method in the case of forming the light shielding wall 61 on the light shielding wall layer of the second stage, but it is not limited to the second stage, and the light shielding wall can be formed on any light shielding wall layer by the same forming method.

[0169] 9. Shape of on-chip lens

[0170] Will refer to Fig.13 The shape of the on-chip lens 72 will be described.

[0171] Although any shape may be selected as the shape of the on-chip lens 72, typical shapes may be: a circle, in which the on-chip lens 72 has the same curvature in a horizontal section and an oblique section; and a square, in which the curvature of the on-chip lens 72 in a horizontal section is different from the curvature in an oblique section.

[0172] Fig.13 A horizontal cross section and an oblique cross section of the on-chip lens 72 in the case of a circle and a square are respectively shown; and the shape of a light-converging point on the same light-shielding film surface as the inter-pixel light-shielding film 50 and the pupil-dividing light-shielding film 52 .

[0173] In the case where the shape of the on-chip lens 72 is a square, shapes with different curvatures are formed on the horizontal section and the oblique section. Therefore, the refraction angle of the incident light changes, and the focal point becomes wider. However, according to the pixel structure of the present invention, a multi-stage light shielding wall 61 is formed, and pupil correction is optimized for each light shielding wall 61. Therefore, compared with a single-stage light shielding wall 61, the sensitivity loss is further reduced.

[0174] In the case where the phase difference pixel 2P is arranged inside the pixel array unit 3, it is preferable to form the shape of the on-chip lens 72 into a circle because it is desired that the light-converging point be converged small to obtain the phase difference characteristic.

[0175] Assuming that the ratio of the curvature radius in the oblique direction and the horizontal direction of the on-chip lens 72 (=curvature radius in the oblique direction / curvature radius in the horizontal direction) is called the flatness, then preferably, the flatness is in the range of 1 to 1.2 to maintain the following level: Fig.14 As shown, the limit of distance measurement allowed by phase difference autofocus is prevented from decreasing. In the solid-state imaging device 1 having a pixel size of 3 μm or more, in most cases, it is difficult for the curvature of the on-chip lens 72 in the horizontal direction and the curvature in the oblique direction to become the same. In this case, it is preferable to set the flattening ratio within the range of 1 to 1.2 to maintain the phase difference characteristics.

[0176] 10.Shading structure of OPB area

[0177] Next, the light shielding structure in the OPB area outside the pixel effective area will be described.

[0178] Fig.15 1 is a diagram illustrating a first exemplary configuration of a light shielding structure in an OPB region outside a pixel effective region.

[0179] In the pixel effective area, two sections of the light-shielding wall 61, namely the first light-shielding wall 61A and the second light-shielding wall 61B, are formed as described above, and the light-shielding wall is formed so that the closer the position is from the center (center of the field of view) of the pixel array unit 3 to the peripheral portion (edge ​​of the field of view), the greater the pupil correction amount becomes.

[0180] In contrast, in the OPB region outside the pixel effective area, it is possible to Fig.15 As shown, there is only a formation Figure 3 The light shielding structure of the OPB forming film 51 shown in FIG. Fig.15 In the example of FIG. 1 , although the G color filter 71 is formed in the OPB region, since the OPB region is a region that does not receive light, the color and presence of the color filter 71 are not limited.

[0181] Fig.16 2 is a diagram illustrating a second exemplary configuration of a light shielding structure in an OPB region outside a pixel effective region.

[0182] In the OPB area outside the pixel effective area, it is possible to apply not only Fig.15 The light shielding structure shown is formed with only the OPB forming film 51, and it is also possible to apply, for example, Fig.16 As shown in FIG. 1 , a light shielding structure of two light shielding walls 61 including a first light shielding wall 61A and a second light shielding wall 61B which are the same as those in the pixel effective area is formed on the OPB forming film 51. Fig.15 Compared with the case where only the OPB forming film 51 is formed shown in , the light shielding property can be improved.

[0183] Since the two sections of the light shielding wall 61 are formed as shown in the OPB region Fig.16 As shown, the first light shielding wall 61A and the second light shielding wall 61B are respectively located at different positions along the plane direction, so that a dense pattern can be formed along the plane direction and the light shielding effect can be further improved. In addition, the smaller the interval (pattern spacing) of the light shielding wall 61 along the plane direction, the better the light shielding effect can be.

[0184] Will refer to Fig.17 right Fig.16 The method for manufacturing the light shielding structure in the OPB region shown in FIG. Fig.17 Only the formation of the OPB forming film 51, the first light shielding wall 61A and the second light shielding wall 61B is described. For other parts, the manufacturing method is the same as that of reference Figures 4 to 6 The method of description is the same.

[0185] First, if Fig.17 As shown in A, the inter-pixel light shielding film 50 is formed in the pixel effective region, and at the same time, an OPB forming film 51 is formed in the OPB region using the same material as the inter-pixel light shielding film 50.

[0186] Then, if Fig.17 As shown in FIG. 8B , a first light shielding wall 61A is formed in the pixel effective area, and a first light shielding wall 61A is formed in the OPB area at the same time.

[0187] Then, if Fig.17 As shown in C, a second light shielding wall 61B is formed in the pixel effective area, and a second light shielding wall 61B is also formed in the OPB area. Here, the first light shielding wall 61A and the second light shielding wall 61B in the pixel effective area are arranged at positions where pupil correction is performed according to the image height. For the first light shielding wall 61A and the second light shielding wall 61B in the OPB area, the position of the first light shielding wall 61A of the first segment is arranged in a manner that is offset from the position of the second light shielding wall 61B of the second segment in the planar direction.

[0188] As described above, the light shielding wall 61 in the OPB area and the light shielding wall 61 in the pixel effective area can be formed simultaneously through the same process. Therefore, the light shielding property in the OPB area can be improved without increasing the number of processes. In addition, by forming the same pattern in the pixel effective area and the OPB area, processing uniformity is improved.

[0189] Meanwhile, the detailed formation method of the light shielding wall 61 in the OPB region is similar to that of the reference Figure 4 The method for forming the light shielding wall 61 in the pixel effective area is the same as described above. More specifically, the multi-stage light shielding wall 61 can be formed by repeating the following process: forming a film of an inorganic material such as SiO2 as a flattening film 62; forming an opening 101 by etching the portion where the light shielding wall 61 is to be formed; burying a metal material such as tungsten or copper in the opening 101; and then performing CMP on the entire surface.

[0190] Fig.18 2 is a diagram showing another exemplary structure of the light shielding wall 61 that can be formed in the OPB region.

[0191] Fig.18 A shows an exemplary structure of the light shielding wall 61 in which the first light shielding wall 61A of the first stage and the second light shielding wall 61B of the second stage are arranged in a vertically overlapping manner.

[0192] Fig.18 B shows an exemplary structure of the light shielding wall 61 in which the cross-sectional shape of each segment of the light shielding wall 61 is formed in a manner inclined (tapered) in the depth direction. Fig.18B shows an exemplary structure of an inverted tapered light-shielding wall 61 having a planar area of ​​the lower surface greater than the planar area of ​​the upper surface. However, it is also possible to form a positive tapered light-shielding wall 61 having a planar area of ​​the lower surface less than the planar area of ​​the upper surface. By forming the cross-sectional shape of the light-shielding wall 61 in an inclined (tapered) manner, a pattern can be formed more densely. In addition, since the light-shielding wall 61 is not used as wiring, there is no problem in contacting the upper light-shielding wall 61 and the lower light-shielding wall 61 with each other. It is possible to achieve a thickness of the light-shielding layer that cannot be formed and processed by forming the film 51 only with OPB.

[0193] At the same time, although Figures 16 to 18 In the example in which the number of segments of the light shielding wall 61 formed in the OPB region is two, however, when the number of segments of the light shielding wall 61 formed in the pixel effective region is three or more, the number of segments of the light shielding wall 61 formed in the OPB region is also three or more (the same as the number of segments of the light shielding wall 61 in the pixel effective region). Fig.16 As shown, the position of the light shielding wall 61 in each section along the plane direction may be different, but it may also be as follows Fig.18 The shown are the same.

[0194] 11. Exemplary Substrate Configuration of Solid-State Imaging Device

[0195] like Fig.19 As shown in A, Figure 1 The solid-state imaging device 1 in the embodiment has a configuration in which a pixel region 221 in which a plurality of pixels 2 are arranged, a control circuit 222 adapted to control the pixels 2, and a logic circuit 223 including a signal processing circuit for pixel signals are formed on one semiconductor substrate 12.

[0196] However, if Fig.19 As shown in FIG. 1B , the solid-state imaging device 1 may also have a configuration in which a first semiconductor substrate 231 having a pixel region 221 and a control circuit 222 formed therein is stacked with a second semiconductor substrate 232 having a logic circuit 223 formed therein. For example, the first semiconductor substrate 231 and the second semiconductor substrate 232 are electrically connected via a through hole or by Cu-Cu metal bonding.

[0197] Alternatively, if Fig.19 As shown in FIG. 1C, the solid-state imaging device 1 may also have a configuration in which a first semiconductor substrate 241 having only a pixel region 221 is stacked with a second semiconductor substrate 242 having a control circuit 222 and a logic circuit 223. For example, the first semiconductor substrate 241 and the second semiconductor substrate 242 are electrically connected via a through hole or by Cu-Cu metal bonding.

[0198] 12. Exemplary application examples of electronic devices

[0199] The present invention is not limited to application to solid-state imaging devices. More specifically, the present invention can be applied to all electronic devices that use solid-state imaging devices in imaging units (photoelectric conversion units) (for example, imaging devices such as digital cameras or video cameras, portable terminal devices with imaging functions, and printers that use solid-state imaging devices in image reading units). The solid-state imaging device may be a structure formed as a single chip, or may be a structure in the form of a module with an imaging function in which an imaging unit is packaged together with a signal processing unit or an optical system.

[0200] Fig. 20 is a block diagram showing an exemplary configuration of an imaging device as an electronic device according to the present invention.

[0201] Fig. 20 The imaging device 300 includes an optical unit 301 formed by a lens group, etc., using Figure 1 The structure of the solid-state imaging device 1 includes a solid-state imaging device (imaging device) 302 and a digital signal processor (DSP) circuit 303 as a camera signal processing circuit. In addition, the imaging device 300 includes a frame memory 304, a display unit 305, a recording unit 306, an operation unit 307, and a power supply unit 308. The DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, the operation unit 307, and the power supply unit 308 are connected to each other via a bus 309.

[0202] The optical unit 301 captures incident light (image light) from an object and forms an image on an imaging surface of the solid-state imaging device 302. The solid-state imaging device 302 converts the light amount of the incident light formed on the imaging surface by each pixel of the optical unit 301 into an electrical signal. Figure 1 The solid-state imaging device 1 , more specifically, a solid-state imaging device in which a plurality of stages of light-shielding wall layers are provided and optimized pupil correction is performed in the light-shielding wall layers of the respective stages can be used.

[0203] The display unit 305 is formed of a flat-panel display device such as a liquid crystal display panel or an organic electroluminescence (EL) panel, for example, and displays a dynamic image or a still image captured by the solid-state imaging device 302. The recording unit 306 records the dynamic image or the still image captured by the solid-state imaging device 302 in a storage medium such as a hard disk and a semiconductor memory.

[0204] Under the control of the user, the operation unit 307 provides operation commands to various functions possessed by the imaging device 300. The power supply unit 308 appropriately supplies various power supplies to the DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, and the operation unit 307 as operation power supplies for these supply objects.

[0205] As described above, by using the solid-state imaging device 1 according to each of the above-described embodiments as the solid-state imaging device 302, both the normal pixel characteristics and the phase difference pixel characteristics can be realized, and high sensitivity can be obtained. Therefore, high image quality of captured images can also be achieved in the imaging device 300 such as a video camera, a digital camera, and a camera module for a mobile device such as a mobile phone.

[0206] In the above example, a solid-state imaging device in which electrons are regarded as signal charges by setting the first conductivity type to p-type and the second conductivity type to n-type is described. However, the present invention is also applicable to a solid-state imaging device in which positive holes are regarded as signal charges. In other words, each of the above semiconductor regions can be formed by a semiconductor region having opposite conductivity types in which the first conductivity type is set to n-type and the second conductivity type is set to p-type.

[0207] In addition, the application of the present invention is not limited to application to solid-state imaging devices for detecting the distribution of the amount of incident light of visible light and capturing the distribution as an image. The present invention can be applied to solid-state imaging devices that capture the distribution of the amount of incident light of infrared rays, X-rays or particles, etc. as an image, and in a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) that detect the distribution of other physical quantities such as pressure and electrostatic capacitance and capture such distribution as an image, such as fingerprint detection sensors.

[0208] The embodiments of the present invention are not limited to the above-described embodiments, and various modifications may be made within the scope not departing from the gist of the present invention.

[0209] For example, an embodiment combining all or part of the above-described embodiments may be adopted.

[0210] Note that the effects listed in this specification are merely examples and are not limited thereto, and effects not listed in this specification may also be provided.

[0211] In addition, the present invention may also have the following configurations. (1)

[0213] A solid-state imaging device includes a pixel array unit, wherein a plurality of pixels are arranged in a matrix in a two-dimensional manner, and a plurality of sections of light shielding walls are provided between the pixels. (2)

[0215] The solid-state imaging device according to (1) above, wherein the solid-state imaging device is a back-illuminated type. (3)

[0217] The solid-state imaging device according to (1) or (2) above, wherein:

[0218] Each of the plurality of stages of light shielding walls is formed in a position where pupil correction is performed. (4)

[0220] The solid-state imaging device according to any one of (1) to (3) above, wherein

[0221] The pupil correction amount D of the color filter satisfies the condition C≤D≤C+X / 2, where C is the pupil correction amount of the light-shielding wall layer closest to the color filter, and X is the width of the light-shielding wall layer closest to the color filter. (5)

[0223] The solid-state imaging device according to (4) above, wherein

[0224] The pupil correction amount D of the color filter is equal to the pupil correction amount C of the light shielding wall of the light shielding wall layer closest to the color filter. (6)

[0226] The solid-state imaging device according to (3) above, wherein

[0227] The pupil correction amount of the Qth segment (Q>2) among the multiple segments of the light shielding wall is equal to or greater than the pupil correction amount of the Q-1th segment immediately below the Qth segment. (7)

[0229] The solid-state imaging device according to any one of (1) to (6) above, wherein

[0230] In the pixel array unit, the Qth light-shielding wall (Q>2) among the multiple light-shielding walls is at least partially connected to the Q-1th light-shielding wall immediately below, and the Qth light-shielding wall and the Q-1th light-shielding wall have the same potential. (8)

[0232] The solid-state imaging device according to any one of (1) to (7) above, wherein

[0233] The light shielding wall has a forward tapered shape in which an area along a plane direction increases as a position approaches an upper side from a bottom surface. (9)

[0235] The solid-state imaging device according to any one of (1) to (8) above, wherein

[0236] The ratio of the curvature radius in the oblique direction to the curvature radius in the horizontal direction of the on-chip lens of the pixel is 1 to 1.2. (10)

[0238] The solid-state imaging device according to any one of (1) to (9) above, wherein

[0239] Among the plurality of light shielding wall layers as the layer forming the plurality of light shielding wall layers, an inner lens is formed in a predetermined pixel of at least one of the light shielding wall layers. (11)

[0241] The solid-state imaging device according to (10) above, wherein

[0242] The inner lens is formed in a pixel having a predetermined color filter color. (12)

[0244] The solid-state imaging device according to (10) above, wherein

[0245] The light shielding wall layer formed with the inner lens varies according to the color of a color filter. (13)

[0247] The solid-state imaging device according to (10) above, wherein

[0248] Whether or not the inner lens is present differs between normal pixels and phase difference pixels. (14)

[0250] The solid-state imaging device according to (10) above, wherein

[0251] The light shielding wall layer on which the inner lens of the normal pixel is formed is different from the light shielding wall layer on which the inner lens of the phase difference pixel is formed. (15)

[0253] The solid-state imaging device according to any one of (1) to (14) above, wherein

[0254] A portion of the plurality of pixels are phase difference pixels. (16)

[0256] The solid-state imaging device according to any one of (1) to (15) above, wherein

[0257] The plurality of light shielding walls are formed in an OPB region outside a pixel effective region inside the pixel array unit. (17)

[0259] The solid-state imaging device according to (16) above, wherein

[0260] The plurality of stages of light shielding walls in the OPB region have a tapered cross-sectional shape. (18)

[0262] The solid-state imaging device according to (16) or (17) above, wherein

[0263] Positions of the plurality of stages of light shielding walls in the OPB region along a planar direction are different in the light shielding walls of each stage. (19)

[0265] A method for manufacturing a solid-state imaging device, the method comprising:

[0266] A plurality of light shielding walls are formed between pixels when forming a pixel array unit, and in the pixel array unit, a plurality of the pixels are two-dimensionally arranged in a matrix. (20)

[0268] An electronic device, comprising:

[0269] A solid-state imaging device includes a pixel array unit in which a plurality of pixels are two-dimensionally arranged in a matrix and a plurality of sections of light shielding walls are provided between the pixels.

[0270] Reference numerals list

[0271] 1 Solid-state imaging device

[0272] 2 pixels

[0273] 2P Phase Difference Pixel

[0274] 2X normal pixels

[0275] 3 Pixel Array Unit

[0276] 51 OPB film formation

[0277] 61(61A, 61B, 61C) Light-shielding wall

[0278] 71 Color Filters

[0279] 72 On-chip lens

[0280] 231 first semiconductor substrate

[0281] 232 second semiconductor substrate

[0282] 241 first semiconductor substrate

[0283] 242 second semiconductor substrate

[0284] 300 Imaging equipment

[0285] 302 Solid-state imaging device

Claims

1. A solid-state imaging device, comprising: A pixel array unit, the pixel array unit comprising a plurality of pixels, the plurality of pixels comprising a first pixel and a second pixel adjacent to a first side of the first pixel; A first plurality of light shielding walls, wherein the first plurality of light shielding walls are arranged between the first pixel and the second pixel, and the first plurality of light shielding walls include: a first light-shielding wall that penetrates the first film; and a second light-shielding wall, the second light-shielding wall penetrating the second film and, in a cross-sectional view, offset from the first light-shielding wall in a direction toward the periphery of the pixel array unit; A first light shielding film is in contact with a first end of the second light shielding wall, wherein a width of the first light shielding film is greater than a maximum width of the second light shielding wall.

2. The solid-state imaging device according to claim 1, wherein The first light shielding wall and the second light shielding wall are made of the same material.

3. The solid-state imaging device according to claim 1, wherein The first light shielding film partially covers the photoelectric conversion region of the second pixel.

4. The solid-state imaging device according to claim 1, further comprising: a third pixel of the plurality of pixels, the third pixel being adjacent to a second side of the first pixel, the second side of the first pixel being opposite to the first side of the first pixel; A second plurality of light shielding walls, wherein the second plurality of light shielding walls are located between the first pixel and the third pixel, and the second plurality of light shielding walls include: a third light-shielding wall extending through the first film; and a fourth light-shielding wall which penetrates through the second film and is offset from the third light-shielding wall in the direction toward the periphery of the pixel array unit in the cross-sectional view; and A second light shielding film is in contact with a first end of the fourth light shielding wall, wherein a width of the second light shielding film is greater than a maximum width of the fourth light shielding wall.

5. The solid-state imaging device according to claim 4, wherein The width of the second light-shielding film is smaller than the width of the first light-shielding film.

6. The solid-state imaging device according to claim 4, wherein The width of the second light-shielding film is the same as the width of the first light-shielding film.

7. The solid-state imaging device according to claim 5, wherein The third pixel, the first pixel, and the second pixel are arranged in this order in a row in the pixel array unit.

8. The solid-state imaging device according to claim 4, wherein A portion of the third light-shielding wall contacts a portion of the first end of the fourth light-shielding wall.

9. The solid-state imaging device according to claim 1, wherein A portion of the first light shielding wall contacts a portion of the first end of the second light shielding wall.

10. The solid-state imaging device according to claim 1, wherein An inner lens is formed in a predetermined pixel of at least one of the plurality of light-shielding wall layers including the first plurality of light-shielding wall layers.

11. The solid-state imaging device according to claim 1, wherein The first pixel, the second pixel, or both the first pixel and the second pixel include an inner lens and an outer lens.

12. The solid-state imaging device according to claim 1, further comprising: An on-chip lens, wherein the on-chip lens is located above the first plurality of light-shielding walls; and An inner lens is located in the first film and adjacent to a second end of the second light-shielding wall, the second end of the second light-shielding wall being opposite to the first end of the second light-shielding wall.

13. The solid-state imaging device according to claim 4 or 5, wherein: The first pixel includes a first inner lens, the second pixel includes a second inner lens, and the third pixel includes a third inner lens, and Wherein, the first light-shielding wall is located between the first inner lens and the second inner lens, and the third light-shielding wall is located between the third inner lens and the first inner lens.

14. The solid-state imaging device according to claim 1, wherein In a plan view, the first light shielding film is adjacent to the first side of the first pixel, and the solid-state imaging device further includes: a third pixel among the plurality of pixels, wherein in the plan view, the second pixel is located between the first pixel and the third pixel; a second light-shielding film, wherein in the plan view, the second light-shielding film is adjacent to a second side of the first pixel, the second side of the first pixel being opposite to the first side of the first pixel; and a third light shielding film, wherein in the plan view, the third light shielding film is adjacent to the first side of the third pixel, The width of the first light-shielding film is smaller than the width of the second light-shielding film and the width of the third light-shielding film. 15 . An electronic device comprising the solid-state imaging device according to claim 1 .

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