Power semiconductor element and manufacturing method thereof

Abstract

The present disclosure relates to a power semiconductor element and a method for manufacturing the same. The power semiconductor element includes: a first electrical epitaxial layer, a second electrical first doping region, a first electrical second doping region, an element electrode, a first terminal electrode, and a second terminal electrode. The epitaxial layer includes an active region and a terminal region. The first doping region is located in the active region; the second doping region is located in the first doping region. The contact metal layer is located on the epitaxial layer and is in electrical contact with the second doping region. The element electrode is located in an element groove in the active region and is electrically isolated from the epitaxial layer and the contact metal layer. The first terminal electrode is located in a first terminal groove in the terminal region and is electrically isolated from the epitaxial layer. The second terminal electrode is located at the bottom of the first terminal groove and is electrically isolated from the first terminal electrode and the epitaxial layer. Both the first terminal electrode and the second terminal electrode can be optionally floated.

Description

Technical Field

[0001] The present application relates to a power electronic component and a manufacturing method thereof, and in particular to a power semiconductor component and a manufacturing method thereof. Background Art

[0002] Power semiconductor components are generally used in switch-mode power supplies or other high-speed power switching devices. In addition to being able to pass large currents in the active region, power semiconductor components are generally required to be able to withstand a large breakdown voltage in the termination region. Currently, several power semiconductor components (e.g., Schottky barrier diodes, metal oxide semiconductor field effect transistors, or metal oxide semiconductor Schottky diodes) are widely used. However, because conventional planar Schottky barrier diodes have a low breakdown voltage, trench MOS barrier Schottky diodes (TMBS diodes) have recently been developed.

[0003] A typical power semiconductor device, such as a trench metal-oxide-semiconductor Schottky barrier diode, is constructed by first forming an N-epitaxial layer on an N+ substrate. Multiple trench gates are then formed within the N-epitaxial layer, with a gate oxide layer positioned between the trench gates and the N-epitaxial layer. A Schottky barrier metal layer and anode metal are then deposited on the surface of the N-epitaxial layer and the trench gates.

[0004] However, as the density of power semiconductor devices increases, the gate-drain charge (Qgd) increases, slowing the gate's charging and discharging, which in turn affects device performance. To reduce the gate-drain charge and improve device switching losses, device capacitance must be reduced, for example by using a split-gate architecture to reduce the gate-drain area. However, this further complicates device charge balance.

[0005] Therefore, there is a need to provide an advanced power semiconductor element and a manufacturing method thereof to solve the problems faced by the prior art. Summary of the Invention

[0006] One embodiment of the present specification discloses a power semiconductor element, which includes: an epitaxial layer, a first doped region, a second doped region, a contact metal layer, a gate electrode, a first terminal electrode, and a second terminal electrode. The epitaxial layer has a first electrical property and includes an active region and a terminal region. The first doped region has the second electrical property and is located in the epitaxial layer of the active region; the second doped region has the first electrical property and is located in the first doped region. The contact metal layer is located on the epitaxial layer and is in electrical contact with the second doped region. The gate electrode is located in a device trench in the active region and is electrically isolated from the epitaxial layer and the contact metal layer. The first terminal electrode is located in a first terminal trench in the terminal region and is electrically isolated from the epitaxial layer. The second terminal electrode is located at the bottom of the first terminal trench and is electrically isolated from the first terminal electrode and the epitaxial layer. The first terminal electrode and the second terminal electrode can both be floating or in electrical contact with the contact metal layer.

[0007] Another embodiment of the present specification discloses a method for manufacturing a power semiconductor device, comprising the following steps: first, providing an epitaxial layer having a first electrical property, the epitaxial layer including an active region and a terminal region; forming a first doped region having a second electrical property in the epitaxial layer in the active region; forming a second doped region having the first electrical property in the first doped region; forming a contact metal layer on the epitaxial layer so as to be in electrical contact with the second doped region; forming a gate electrode in the active region, the gate electrode being located in a device trench extending into the epitaxial layer and being electrically isolated from the epitaxial layer and the contact metal layer; forming a first terminal electrode in the terminal region, the gate electrode being located in a first terminal trench extending into the epitaxial layer and being electrically isolated from the epitaxial layer; forming a second terminal electrode at the bottom of the first terminal trench, the gate electrode being electrically isolated from the first terminal electrode and the epitaxial layer; and allowing both the first terminal electrode and the second terminal electrode to be floating or in electrical contact with the contact metal layer.

[0008] According to the above embodiments, this specification provides a power semiconductor element and a method for manufacturing the same, wherein at least one trench is configured in the terminal region of a power semiconductor element having a trench structure, and at least two terminal electrode field plates stacked one above the other and isolated from each other are configured in the trench, so that both are electrically connected to the source at the same time, or are simultaneously floating; or one of them is electrically connected to the source and the other is floating. The aforementioned power element having a trench structure can be, for example (but not limited to), a metal oxide semiconductor field effect transistor, a metal oxide semiconductor Schottky diode, a Schottky barrier diode, or other suitable power semiconductor element. The number of trenches and the selection of the terminal electrode field plate connection method can be pre-designed based on the electric field requirements during operation of the power semiconductor element, thereby improving the charge balance of the power metal oxide-semiconductor transistor unit.

[0009] The foregoing summary of the invention is only a general overview of various aspects of this specification, and introduces some related concepts of the disclosure, which will be further described in detail in the following embodiments. The foregoing summary of the invention is not intended to limit the key or essential features of the claimed invention, nor is it solely intended to limit the scope of the invention claimed in this specification. The scope of the invention claimed in this specification is based on the claims described below. By referring to the entire disclosure of the following specification, the drawings, and each claim, you can have a better understanding of the above and other technical contents of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To make the above-mentioned features and advantages of the present invention more clearly understood, the following embodiments are specifically described in detail. However, it should be noted that these specific implementation examples and embodiments are not intended to limit the present invention. The present invention may be implemented using other features, components, methods, and parameters. The preferred embodiments are provided merely to illustrate the technical features of the present invention and are not intended to limit the claims of the present invention.

[0011] Figures 1A to 1G 1 is a schematic cross-sectional view of a series of process structures for manufacturing a power semiconductor device according to an embodiment of the present specification;

[0012] Figure 2A is a top view of a partial wiring structure of a power semiconductor element according to an embodiment of this specification;

[0013] Figure 2B It is along Figure 2A A cross-sectional view of a portion of the structure of a power semiconductor element as shown by a tangent line S1;

[0014] Figure 2C It is along Figure 2A A cross-sectional view of a portion of the structure of a power semiconductor element as shown by a tangent line S2;

[0015] Figure 2D is a partial structural cross-sectional view of a power semiconductor element according to another embodiment of the present specification;

[0016] Figure 3 is a partial structural cross-sectional view of a power semiconductor element according to another embodiment of the present specification; and

[0017] Figure 4 It is a partial structural cross-sectional view of a power semiconductor element according to another embodiment of the present specification. DETAILED DESCRIPTION

[0018] This specification provides a power semiconductor element and a method for manufacturing the same, which can adjust the electric field distribution in the terminal region of the power semiconductor element to improve the charge balance of the power semiconductor element during operation. Several embodiments are presented below and described with reference to the accompanying drawings. In the drawings, similar reference numerals are used to represent similar or equivalent elements. The drawings are for illustration only and are not shown to scale. The following embodiments are merely illustrative of the limited scope and implementation of the present invention.

[0019] It should be understood that the specific details, connection relationships and manufacturing methods described are only used to enhance understanding. A person skilled in the relevant art can easily ignore one or more specific details or elements, or implement the present invention through other methods. In order to avoid making this specification obscure, existing structures or operating methods are not described in detail here. The order of steps or components of different embodiments is not limited by the illustrated content. Therefore, in some embodiments, the order of performing steps or assembling components may be the same as or different from the illustrated embodiments. In addition, not all illustrated steps or components are necessary to implement the present invention.

[0020] Please refer to Figures 1A to 1G , Figures 1A to 1G 1 is a schematic cross-sectional view of a series of process structures for manufacturing a power semiconductor device 100 according to an embodiment of the present specification. The method for manufacturing the power semiconductor device 100 includes the following steps: First, an epitaxial layer 102 having a first electrical property is provided on a semiconductor substrate 101. In some embodiments of the present specification, the semiconductor substrate 101 may include a semiconductor base layer having n-type dopants (e.g., pentavalent atoms such as arsenic, phosphorus, and antimony). In some embodiments of the present specification, the material constituting the semiconductor base layer may be, for example, monocrystalline silicon, polycrystalline silicon, or silicon carbide (SiC). In this embodiment, the semiconductor substrate 101 may be a wafer including a monocrystalline silicon layer.

[0021] In some embodiments of the present disclosure, the formation of the epitaxial layer 102 may include growing a semiconductor epitaxial layer 102 having an n-type dopant on a semiconductor substrate 101 using an epitaxial deposition process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The epitaxial layer 102 may be made of the same or different material as the semiconductor epitaxial layer 102 , and the doping concentration of the n-type dopant in the semiconductor substrate 101 may be greater than the doping concentration of the n-type dopant in the epitaxial layer 102 .

[0022] For example, in this embodiment, a molecular beam epitaxy (MBE) technique (but not limited thereto) can be used to form a single crystal silicon epitaxial layer 102 having n-type doping on a single crystal silicon semiconductor substrate 101 having n-type doping. In some embodiments of the present specification, the epitaxial layer 102 can be divided into at least one active region 102A and a termination region 102T located outside the active region (e.g., Figure 1A shown).

[0023] Next, the epitaxial layer 102 is subjected to at least one photoresist etching process to form a plurality of device trenches (e.g., device trenches 103a and 103b) in the active region 102A of the epitaxial layer 102, and a plurality of termination trenches (e.g., device trenches 104a, 104b, 104c, and 104d) in the termination region 102T of the epitaxial layer 102. In some embodiments of the present disclosure, the device trenches 103a and 103b and the termination trenches 104a, 104b, 104c, and 104d may be formed using different photoresist etching processes.

[0024] In this embodiment, the device trenches 103a and 103b and the terminal trenches 104a, 104b, 104c and 104d are formed simultaneously by the same photoresist etching process. The device trenches 103a and 103b and the terminal trenches 104a, 104b, 104c and 104d extend downward from the surface 102s of the epitaxial layer 102 into the epitaxial layer 102 (as shown in FIG. Figure 1B (not shown). The spacing P1 between the device trenches 103a and 103b can be the same as or different from the spacing P2 between the terminal trenches 104a, 104b, 104c, and 104d. Furthermore, the distance d1 between the device trench 103a at the edge of the active region 102A and the terminal trench 104a at the edge of the terminal region 102T can be the same as or different from the spacing P1 or P2.

[0025] Then, a dielectric layer 105 is formed on the epitaxial layer 102, so that the dielectric layer 105 covers the bottom 103r and sidewalls 103s of the element trenches 103a and 103b, and covers the bottom 104r and sidewalls 104s of the terminal trenches 104a, 104b, 104c and 104d (as shown in FIG. Figure 1C shown).

[0026] Then, polysilicon material is deposited on the gate dielectric layer (gate dielectric layer) 105 to fill the device trenches 103a and 103b and the terminal trenches 104a, 104b, 104c and 104d. The dielectric layer 105 is used as a stop layer to remove the polysilicon material on the gate dielectric layer 105. Another photoresist etching process (not shown) is then performed to remove a portion of the polysilicon material in the device trenches 103a and 103b and the terminal trenches 104a, 104b, 104c and 104d to form separation electrodes 106a and 106b at the bottom 103r of the device trenches 103a and 103b, respectively, and to form a lower terminal electrode 107a, 107b, 107c and 107d (as shown in FIG. 1 ) at the bottom 104r of the terminal trenches 104a, 104b, 104c and 104d, respectively. Figure 1D shown)

[0027] Then, through a thermal oxidation or deposition process, dielectric isolation layers 109a and 109b are formed over the isolation electrodes 106a and 106b, respectively. Meanwhile, dielectric isolation layers 110a, 110b, 110c, and 110d are formed over the lower terminal electrodes 107a, 107b, 107c, and 107d. Polysilicon material is then deposited to fill the device trenches 103a and 103b and the terminal trenches 104a, 104b, 104c, and 104d. After planarization, gate electrodes 111a and 111b are formed in the filled device trenches 103a and 103b, and upper terminal electrodes 112a, 112b, 112c, and 112d are formed in the terminal trenches 104a, 104b, 104c, and 104d.

[0028] In this embodiment, gate electrodes 111a and 111b are stacked above separator electrodes 106a and 106b, respectively, and are electrically isolated from each other by dielectric isolation layers 109a and 109b, respectively. Upper terminal electrodes 112a, 112b, 112c, and 112d are stacked above lower terminal electrodes 107a, 107b, 107c, and 107d, respectively, and are electrically isolated from each other by dielectric isolation layers 110a, 110b, 110c, and 110d, respectively.

[0029] The gate electrodes 111a and 111b and the separation electrodes 106a and 106b are electrically isolated from the epitaxial layer 102 in the active region 102A by a portion of the dielectric layer 105 formed on the bottom 103r and sidewalls 103s of the device trenches 103a and 103b, respectively. The upper terminal electrodes 112a, 112b, 112c, and 112d and the lower terminal electrodes 107a, 107b, 107c, and 107d are electrically isolated from the epitaxial layer 102 in the terminal region 102T by a portion of the dielectric layer 105 formed on the bottom 104r and sidewalls 104s of the terminal trenches 104a, 104b, 104c, and 104d, respectively (e.g., Figure 1E shown).

[0030] Then, a dielectric protection layer 114 is formed over the active region 102A and the terminal region 102T. The terminal region 102T is shielded with a mask (not shown), and multiple ion implantation processes are performed on the active region 102A. A plurality of p-type doped well regions 115 are formed in the epitaxial layer 102 in the active region 102A. A p-type boundary doped region 113 is formed between the device trench 103a at the edge of the active region 102A and the terminal trench 104a at the edge of the terminal region 102T. A plurality of n-type source doped regions 116 are then formed in the doped well region 115, adjacent to the corresponding gate electrodes 111a and 111b (as shown in FIG. 1 ). Figure 1F shown).

[0031] Next, the dielectric protection layer 114 is patterned using a photoresist etching process (not shown) to form a plurality of openings that expose the source doped regions 116 within the active region 102A. A contact metal layer 118 is then formed on the patterned dielectric protection layer 114 to fill the openings, forming contact plugs 117 a and 117 b that electrically contact the source doped regions 116. In this embodiment, the contact metal layer 118 also covers the termination region 102T and overlaps all upper termination electrodes 112 a, 112 b, 112 c, and 112 d and lower termination electrodes 107 a, 107 b, 107 c, and 107 d within the termination region 102T. Furthermore, the contact metal layer 118 is electrically isolated from a portion of the epitaxial layer 102 within the termination region 102T by the patterned dielectric protection layer 114. However, in some embodiments of the present disclosure, the contact metal layer 118 may overlap only a portion of the upper terminal electrodes 112a, 112b, 112c, and 112d and a portion of the lower terminal electrodes 107a, 107b, 107c, and 107d in the terminal region 102T.

[0032] In some embodiments of the present disclosure, an ion implantation process may be selectively performed outside the terminal trenches 104a, 104b, 104c, and 104d to form a p-type annular doped region 123 surrounding the terminal region 102T. In this embodiment, the doping depth t1 of the annular doped region 123 is greater than the doping depth t2 of the p-type doped well region 115.

[0033] In addition, an upper dielectric layer 124 and a passivation layer 125 may be formed above the terminal region 102T, covering a portion of the contact metal layer 118 above the terminal trenches 104a, 104b, 104c, and 104d. In some embodiments of the present specification, the upper dielectric layer 124 may be a multilayer structure including silicon nitride and polyimide (PI). The passivation layer 125 may be a silicon oxide layer, silicon nitride, a plastic layer (e.g., a polyimide (PI) layer), or a combination thereof (e.g., Figure 1G shown).

[0034] Subsequently, a series of back-end of line (BEOL) processes are performed. According to the design of the power semiconductor device 100, a plurality of contact plugs (described below) are formed in the termination region 102T. These contact plugs selectively electrically contact the upper termination electrodes 112a, 112b, 112c, and 112d, and the lower termination electrodes 107a, 107b, 107c, and 107d in the termination trenches 104a, 104b, 104c, and 104d with the contact metal layer 118. Furthermore, a plurality of contact plugs 120a and 120b are formed in the active region 102A. These contact plugs 120a and 120b electrically contact the separated electrodes 106a and 106b with the contact metal layer 118 via the contact plugs 120a and 120b. A gate structure 121 is formed outside the terminal trenches 104a, 104b, 104c and 104d, and is electrically contacted with the gate electrodes 111a and 111b respectively through contact plugs 122a and 122b, thereby completing the following steps: Figures 2A to 2C The production of a power semiconductor component 100 is shown.

[0035] Figure 2A is a top view of a partial wiring structure of a power semiconductor element 100 according to an embodiment of this specification; Figure 2B It is along Figure 2A A partial structural cross-sectional view of the power semiconductor element 100 as shown by the tangent line S1; and Figure 2C It is along Figure 2A FIG. 1 is a cross-sectional view of a portion of the structure of the power semiconductor element 100 shown along a tangent line S2.

[0036] In this embodiment, the upper terminal electrode 112a and the lower terminal electrode 107a located in the terminal trench 104a are electrically contacted with the contact metal layer 118 via contact plugs 119a and 119b, respectively. The upper terminal electrode 112b located in the terminal trench 104b is electrically contacted with the contact metal layer 118 via contact plug 119c. The lower terminal electrode 107b located in the terminal trench 104b is floating and not in electrical contact with any metal layer or conductive line. The upper terminal electrode 112c and the lower terminal electrode 107c located in the terminal trench 104c are also floating and not in electrical contact with any metal layer or conductive line. The lower terminal electrode 107d located in the terminal trench 104d is electrically contacted with the contact metal layer 118 via contact plug 119c. The upper terminal electrode 112d located in the terminal trench 104d is floating and not in electrical contact with any metal layer or conductive line.

[0037] By selecting (changing) the electrical connection method of the upper terminal electrodes 112a, 112b, 112c and 112d and the lower terminal electrodes 107a, 107b, 107c and 107d located in the terminal trenches 104a, 104b, 104c and 104d, the electric field distribution during operation of the power semiconductor device 100 can be adjusted, which helps to improve the charge balance of the power metal oxide-semiconductor transistor unit.

[0038] In addition, in some embodiments of the present specification, the contact plugs 119a' and 119b' located in the terminal trench 104a' and connected to the upper terminal electrode 112a' and the lower terminal electrode 107a' can have different manufacturing methods and structures. Figure 2D , Figure 2D This is a partial structural cross-sectional view of a power semiconductor element 100' according to another embodiment of this specification. Since the connection method of the upper terminal electrode 112a' and the lower terminal electrode 107a' can be predetermined, when forming the upper terminal electrode 112a', the lower terminal electrode 107a' dielectric isolation layer 110a', and the dielectric layer 105', the lower terminal electrode 107a' can be directly extended upward at the location where the contact plug 119b' is predetermined to be formed, and electrically connected to the upper terminal electrode 112a'. Then, the interface layer opening is directly filled with metal material to form contact plugs 119a' and 119b', electrically connecting the upper terminal electrode 112a' and the lower terminal electrode 107a' to the contact metal layer 118, respectively; there is no need to form a dielectric layer on the sidewalls of the interface layer opening.

[0039] Please refer to Figure 3 , Figure 32 is a cross-sectional view of a portion of the structure of a power semiconductor element 200 according to another embodiment of the present specification. The structure of the power semiconductor element 200 is generally similar to that of the power semiconductor element 100, with the difference being that the structures of the gates 211a and 211b in the active region 102A of the power semiconductor element 200 are different. In this embodiment, the gates 211a and 211b fill the element trenches 103a and 103b, respectively, and do not include any separate electrodes. Furthermore, the electrical properties of the annular doped region 123 of the power semiconductor element 200 are not limited to p-type. In one embodiment, the annular doped region 123 of the power semiconductor element 200 may be an n-type electrical property, extending from the surface 102s of the epitaxial layer 102 into the doped well region of the epitaxial layer 102.

[0040] Please refer to Figure 4 , Figure 4 FIG4 is a cross-sectional view of a portion of the structure of a power semiconductor device 400 according to another embodiment of the present disclosure. The structure of the active region 402A of the power semiconductor device 400 is substantially similar to that of the active region 102A of the power semiconductor device 100. The difference is that the annular doped region 423 of the power semiconductor device 400 is extended a distance H beyond the edge of the termination region 402T, preventing the annular doped region 423 from directly contacting the termination trench 104d. Furthermore, the termination region 402T also includes an oxide layer 426 and a metal pad 427.

[0041] In this embodiment, an oxide layer 426 covers the surface 102s of the epitaxial layer 102 in the termination region 402T, partially overlaps the annular doped region 423 located in the termination region 402T, and is encapsulated by the overlying dielectric layer 424 and passivation layer 425. The annular doped region 423 may be a doped well region 423a having p-type or n-type electrical properties (denoted by P / N) extending from the surface 102s of the epitaxial layer 102 into the epitaxial layer 102. A metal pad 427 is located above and electrically contacts the annular doped region 423 and is encapsulated by the dielectric layer 424 and passivation layer 425, thereby further providing better charge balance for the power semiconductor device 400.

[0042] According to the above embodiments, this specification provides a power semiconductor element and a method for manufacturing the same, wherein at least one trench is configured in the terminal region of a power semiconductor element having a trench structure, and at least two terminal electrode field plates stacked one above the other and isolated from each other are configured in the trench, so that both are electrically connected to the source at the same time, or are simultaneously floating; or one of them is electrically connected to the source and the other is floating. The aforementioned power semiconductor element having a trench structure can be, for example (but not limited to) a metal oxide semiconductor field effect transistor, a metal oxide semiconductor Schottky diode, a Schottky barrier diode, or other suitable power semiconductor element. The number of trenches and the selection of the terminal electrode field plate connection method can be pre-designed based on the electric field requirements during operation of the power semiconductor element, thereby improving the charge balance of the power metal oxide semiconductor transistor unit.

[0043] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A power semiconductor component, comprising: an epitaxial layer having a first electrical property and including an active region and a terminal region; a first doped region having a second electrical property and located in the epitaxial layer of the active region; a second doped region having the first electrical property and located in the first doped region; a contact metal layer, located on the epitaxial layer, electrically contacting the second doped region, and continuously extending from the active region to the terminal region; a device electrode located in a device trench in the active region and electrically isolated from the epitaxial layer and the contact metal layer; a first terminal electrode located in a first terminal trench in the terminal region and electrically isolated from the epitaxial layer; as well as a second terminal electrode located at a bottom of the first terminal trench and electrically isolated from the first terminal electrode and the epitaxial layer; The first terminal electrode and the second terminal electrode can be selectively floated or electrically contacted with the contact metal layer, and The contact metal layer is continuous in the terminal region. 2 . The power semiconductor device as claimed in claim 1 , wherein the non-floating one of the first terminal electrode and the second terminal electrode is electrically connected to the contact metal layer. 3 . The power semiconductor device as claimed in claim 1 , further comprising a separation electrode located at a bottom of the device trench, electrically isolated from the device electrode and the epitaxial layer, and electrically connected to the contact metal layer.

4. A power semiconductor element as described in claim 3, wherein the element electrode is located above the separation electrode and is electrically isolated from each other by a dielectric isolation layer; and the element electrode and the separation electrode are electrically isolated from the epitaxial layer by a dielectric layer covering a bottom and a side wall of the element trench. 5 . The power semiconductor device as claimed in claim 1 , wherein the contact metal layer covers the terminal region and is electrically isolated from the terminal region by a dielectric layer. 6 . The power semiconductor device as claimed in claim 1 , further comprising a boundary doped region having the second electrical property, located between the device trench and the first terminal trench, and electrically isolated from the contact metal layer.

7. The power semiconductor device according to claim 1 , further comprising: a third terminal electrode located in a second terminal trench in the terminal region away from the active region and electrically isolated from the epitaxial layer; and a fourth terminal electrode, located at a bottom of the second terminal trench and electrically isolated from the third terminal electrode and the epitaxial layer; in, The third terminal electrode and the fourth terminal electrode can be selectively floated or electrically contacted with the contact metal layer. 8 . The power semiconductor device as claimed in claim 1 , further comprising another device electrode located in another device trench in the active region extending into the epitaxial layer and electrically isolated from the epitaxial layer and the contact metal layer.

9. A method for manufacturing a power semiconductor element, comprising: Providing an epitaxial layer having a first electrical property and including an active region and a terminal region; forming a first doped region in the epitaxial layer of the active region to have a second electrical property; forming a second doped region in the first doped region, the second doped region having the first electrical property; forming a contact metal layer on the epitaxial layer to electrically contact the second doped region; forming a device electrode in the active region, extending into a device trench of the epitaxial layer and electrically isolated from the epitaxial layer and the contact metal layer; forming a first terminal electrode in the terminal region so as to be located in a first terminal trench extending into the epitaxial layer and electrically isolated from the epitaxial layer; as well as forming a second terminal electrode at a bottom of the first terminal trench to be electrically isolated from the first terminal electrode and the epitaxial layer; wherein the first terminal electrode and the second terminal electrode can be selectively floated or electrically contacted with the contact metal layer; The contact metal layer continuously extends from the active region to the terminal region, and the contact metal layer is continuous in the terminal region. 10 . The method for manufacturing a power semiconductor device as claimed in claim 9 , wherein the device trench and the first terminal trench are formed simultaneously; and the device electrode and the first terminal electrode are formed simultaneously.

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