A Fine-Tuning Method, Device, Equipment and Storage Medium for a Flash Memory Chip Reference Circuit

Abstract

An embodiment of the present invention discloses a fine-tuning method, device, equipment and storage medium for a reference circuit of a flash memory chip. The solution includes: obtaining the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip; setting a first interval range of the fine-tuning gear position values, discretizing the fine-tuning gear position values within the first interval range at a predetermined step length to obtain a first number of fine-tuning gear position values; sorting all the fine-tuning gear position values among the first number of fine-tuning gear position values according to the magnitude order of the probability values in the probability distribution information to obtain a second number of fine-tuning gear position values consistent with the first number of values; for the flash memory chip to be tested, sequentially select the fine-tuning gear position value to be set from the second number of fine-tuning gear position values, and test the flash memory chip to be tested based on the fine-tuning gear position value to be set. When the absolute value of the difference between the measured value obtained by the test and the preset target value is less than the predetermined threshold, set this fine-tuning gear position value to be set as the first target fine-tuning gear position value.

Description

Technical Field

[0001] The present application relates to the technical field of non-volatile memories, and in particular to a method, device, equipment and storage medium for fine-tuning a reference circuit of a flash memory chip. Background Art

[0002] Flash memory is a long-life non-volatile memory that can still retain the stored data information in the case of power failure. Since it can still save data when powered off, flash memory is usually used to save setting information, such as saving data in the motherboard program of a computer, a personal digital assistant, a digital camera, etc.

[0003] The design of a flash memory chip includes a storage area and a peripheral control circuit, where an internal voltage reference unit controls the voltage distribution of the chip. In order to eliminate the influence of process parameter fluctuations on the accuracy of the reference voltage, the circuit design is in a micro-adjustable mode. For example, before leaving the factory, the flash memory chip needs to test and fine-tune the programming voltage in its programming state or the erase voltage in its erase state, etc., and store the fine-tuned programming voltage or erase voltage in the internal memory of the embedded flash memory. The prior art generally tests the fine-tuning gear positions of the flash memory chip based on the linear scanning method. In this way, starting from zero each time and gradually increasing until the target fine-tuning gear position value is found, it takes a lot of test time and test costs.

[0004] Therefore, it is necessary to provide a method for efficiently testing the fine-tuning gear position value of a flash memory chip. Summary of the Invention

[0005] Embodiments of the present specification provide a method and device for fine-tuning a reference circuit of a flash memory chip to provide a method for efficiently testing the fine-tuning gear position value of a flash memory chip.

[0006] To solve the above technical problems, the embodiments of the present specification are implemented as follows:

[0007] A method for fine-tuning a reference circuit of a flash memory chip provided by an embodiment of the present specification includes:

[0008] Obtaining the probability distribution information of the fine-tuning gear position historical data of the flash memory chip; the data types of the fine-tuning gear position historical data are the programming voltage of the flash memory chip in the programming state or the erase voltage in the erase state;

[0009] Setting a first interval range of the fine-tuning gear position value, and discretizing the fine-tuning gear position values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear position values;

[0010] Sorting all the fine-tuning gear position values in the first number of fine-tuning gear position values according to the magnitude order of the probability values in the probability distribution information to obtain a second number of fine-tuning gear position values that is the same as the value of the first number;

[0011] For the flash memory chip to be tested, sequentially select the fine-tuning gear value to be set from the second quantity of fine-tuning gear values, test the flash memory chip to be tested based on the fine-tuning gear value to be set, and when the absolute value of the difference between the measured value obtained by the test and the preset target value is less than a predetermined threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value;

[0012] Among them, the obtaining of the probability distribution information of the historical data of the fine-tuning gear of the flash memory chip specifically includes:

[0013] Pre-obtain a predetermined number of flash memory chips, and set a second interval range consistent with the first interval range;

[0014] Based on the second interval range, test the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain a second target fine-tuning gear value consistent with the predetermined number of values;

[0015] Analyze the statistical law of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

[0016] Preferably, the probability distribution information of the actual fine-tuning gear value is the normal distribution probability information of the actual fine-tuning gear value.

[0017] Preferably, the range of the predetermined number is from 1000 to 20000.

[0018] A fine-tuning device for a reference circuit of a flash memory chip provided by an embodiment of this specification includes:

[0019] A fine-tuning gear value probability distribution acquisition module, configured to acquire the probability distribution information of the historical data of the fine-tuning gear of the flash memory chip; the data type of the historical data of the fine-tuning gear is the programming voltage of the flash memory chip in the programming state or the erasing voltage in the erasing state;

[0020] A fine-tuning gear value discretization module, configured to set a first interval range of the fine-tuning gear value, and discretize the fine-tuning gear values within the first interval range according to a predetermined step length to obtain a first quantity of fine-tuning gear values;

[0021] A fine-tuning gear value sorting module, configured to sort all the fine-tuning gear values in the first quantity of fine-tuning gear values based on the magnitude order of the probability values in the probability distribution information to obtain a second quantity of fine-tuning gear values consistent with the first quantity of values;

[0022] A fine-tuning gear value test module is used to sequentially select a fine-tuning gear value to be set from the second quantity of fine-tuning gear values for the flash memory chip to be tested, test the flash memory chip to be tested based on the fine-tuning gear value to be set, and when the absolute value of the difference between the measured value obtained from the test and a preset target value is less than a predetermined threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value;

[0023] Among them, the probability distribution information of the fine-tuning gear historical data of the flash memory chip obtained in the fine-tuning gear value probability distribution acquisition module specifically includes: pre-acquiring a predetermined number of flash memory chips and setting a second interval range consistent with the first interval range; based on the second interval range, testing the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values consistent with the predetermined number of values; analyzing the statistical rules of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

[0024] A fine-tuning device for a reference circuit of a flash memory chip provided by an embodiment of this specification includes:

[0025] At least one processor; and,

[0026] A memory communicatively connected to the at least one processor; wherein,

[0027] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0028] Obtain the probability distribution information of the fine-tuning gear historical data of the flash memory chip; the data type of the fine-tuning gear historical data is the programming voltage of the flash memory chip in the programming state or the erasing voltage in the erasing state;

[0029] Set a first interval range of fine-tuning gear values, discretize the fine-tuning gear values within the first interval range according to a predetermined step size to obtain a first quantity of fine-tuning gear values;

[0030] Sort all the fine-tuning gear values among the first quantity of fine-tuning gear values according to the magnitude order of the probability values in the probability distribution information to obtain a second quantity of fine-tuning gear values consistent with the first quantity of values;

[0031] For the flash memory chip to be tested, select the fine-tuning gear value to be set from the second quantity of fine-tuning gear values in sequence, and test the flash memory chip to be tested based on the fine-tuning gear value to be set. When the absolute value of the difference between the measured value obtained from the test and the preset target value is less than the predetermined threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value;

[0032] Among them, the obtaining of the probability distribution information of the historical data of the fine-tuning gear of the flash memory chip specifically includes: pre-obtaining a predetermined number of flash memory chips, and setting a second interval range consistent with the first interval range; based on the second interval range, test the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values consistent with the predetermined number of values; analyze the statistical law of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

[0033] A computer-readable medium provided by an embodiment of the present specification stores computer-readable instructions thereon, and the computer-readable instructions can be executed by a processor to implement a fine-tuning method for a flash memory chip reference circuit.

[0034] An embodiment of the present specification can achieve the following beneficial effects:

[0035] In the technical solution of this embodiment, based on the probability distribution of the fine-tuning gear values of the flash memory chip, the fine-tuning gear values of the flash memory chip to be tested are tested. In this way, based on the statistical law, the fine-tuning gear values that meet the error requirements with the target values of the fine-tuning gear values can be quickly tested, saving test time and test costs. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic illustration diagram of a fine-tuning circuit in a fine-tuning method for a flash memory chip reference circuit provided by an embodiment of the present specification;

[0038] Figure 2 It is a normal distribution diagram of the target values of the fine-tuning gear values obtained by testing several chips in a fine-tuning method for a flash memory chip reference circuit provided by an embodiment of the present specification;

[0039] Figure 3It is a flowchart of a fine-tuning method for a reference circuit of a flash memory chip provided by an embodiment of this specification;

[0040] Figure 4 It is a schematic diagram of a fine-tuning device for a reference circuit of a flash memory chip provided by an embodiment of this specification;

[0041] Figure 5 It is a schematic structural diagram of a fine-tuning device for a reference circuit of a flash memory chip provided by an embodiment of this specification. Specific embodiments

[0042] To make the objectives, technical solutions, and advantages of one or more embodiments of this specification clearer, the technical solutions of one or more embodiments of this specification will be clearly and completely described below in conjunction with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope protected by one or more embodiments of this specification.

[0043] The following will detail the technical solutions provided by each embodiment of this specification in conjunction with the drawings.

[0044] As Figure 1 shown, Figure 1 This is a schematic explanatory diagram of a fine-tuning circuit in a fine-tuning method for a reference circuit of a flash memory chip provided by an embodiment of this specification. The design principle of the fine-tuning of the flash memory chip reference circuit is that the flash memory chip design includes a storage area and a peripheral control circuit, where the internal voltage reference unit controls the voltage distribution of the chip. To eliminate the influence of process parameter fluctuations on the accuracy of the reference old voltage, the circuit is designed to be a micro-adjustable mode. Its basic principle is that the NMOS switch circuit realizes the selection of different voltage-dividing resistors, thereby achieving high-precision voltage control.

[0045] The prior art generally tests the fine-tuning gears of a flash memory chip based on the linear scanning method. In this way, each time it gradually increases from zero until the target fine-tuning gear value is found, which requires a lot of test time and test costs.

[0046] To solve the defects in the prior art, the following embodiments are given in this solution:

[0047] Figure 3 This is a schematic overall flow diagram of a fine-tuning method for a reference circuit of a flash memory chip in an embodiment of this specification. As Figure 3 shown, this solution may include:

[0048] Step S302: Obtain the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip; the data types of the historical data of the fine-tuning gear positions are the programming voltages of the flash memory chip in the programming state or the erasing voltages in the erasing state.

[0049] In the technical solution of this embodiment, the historical data may refer to the actual target values of the fine-tuning gear position values of several flash memory chips obtained by a certain method of testing, and then the probability distribution information of the actual target values is obtained by using statistical methods. In other words, the purpose of this step is to obtain the probability distribution information of the actual target values of the flash memory chip through the historical data. For Figure 2 example, Figure 2 is the normal distribution graph of the target values of the fine-tuning gear position values obtained by testing several chips in a fine-tuning method of a flash memory chip reference circuit provided by an embodiment of this specification. Through this normal distribution graph, the probability distribution of the target values of the fine-tuning gear position values can be clearly known.

[0050] Step S304: Set the first interval range of the fine-tuning gear position values, and discretize the fine-tuning gear position values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear position values.

[0051] In the technical solution of this embodiment, the first interval range may refer to a candidate numerical interval of the fine-tuning gear position values set in advance. Since the actual target value of the fine-tuning gear position value cannot be determined in advance, a certain method is needed to test the actual fine-tuning gear position value within this first interval range, that is, the target value of the fine-tuning gear position value. Because various tests are subject to errors, an error upper limit can be set in advance. When the test value of the fine-tuning gear position value obtained by the test is less than this error upper limit compared with this target value, it can be considered that this test value meets the requirements.

[0052] Because from a mathematical point of view, the values within the first interval range are continuous. For actual engineering needs, the values within this interval range need to be discretized to obtain several discrete values.

[0053] Step S306: Sort all the fine-tuning gear position values among the first number of fine-tuning gear position values according to the order of the probability values in the probability distribution information to obtain a second number of fine-tuning gear position values that is the same as the first number of values.

[0054] Since the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip has been obtained in step S302, in this step, the probability values in the probability distribution information obtained in step S302 are sorted according to their magnitudes. The probability values with larger magnitudes are ranked in the front, and the probability values with smaller magnitudes are ranked in the back. For example, the probability corresponding to the fine-tuning gear position value of 10 is 30%, which is the highest probability. Then, the probability of 30% is ranked at the front. In other words, it can also be said that the specific fine-tuning gear position value of 10 is ranked at the front.

[0055] S308: For the flash memory chip to be tested, sequentially select the fine-tuning gear value to be set from the second quantity of fine-tuning gear values, and test the flash memory chip to be tested based on the fine-tuning gear value to be set. When the absolute value of the difference between the measured value obtained from the test and the preset target value is less than the preset threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value.

[0056] In this step, for a specific flash memory chip, in order to quickly test and obtain the target value of the fine-tuning gear value of this flash memory chip, test this specific flash memory chip one by one based on the fine-tuning gear values corresponding to the sorted probability values in step S306. Due to certain engineering errors, a threshold is preset in this step. When testing this specific flash memory chip based on a certain fine-tuning gear value, when the absolute value of the difference between the measured value obtained from the test and the preset target value is less than the preset threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value.

[0057] It should be noted that in a flash memory chip, there is a complex input-output relationship between the fine-tuning gear value and the test value of the flash memory chip. In the technical solution of the present invention, for a newly manufactured flash memory chip, set a specific fine-tuning gear value for it, then measure the test value of this flash memory chip through a high-precision source meter, and compare this test value with the preset target value. If the absolute value of the difference is less than a preset difference, the test is qualified.

[0058] In the technical solution of this embodiment, based on the probability distribution of the fine-tuning gear values of the flash memory chip, test the fine-tuning gear values of the flash memory chip to be tested. In this way, based on statistical laws, it is possible to quickly test and obtain the fine-tuning gear values that meet the error requirements with the target values of the fine-tuning gear values, saving test time and test costs.

[0059] For a further optimized solution, the obtaining of the probability distribution information of the historical fine-tuning gear data of the flash memory chip specifically includes:

[0060] Pre-obtain a predetermined number of flash memory chips, and set a second interval range that is the same as the first interval range;

[0061] Based on the second interval range, test the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values that are the same as the predetermined number of values;

[0062] Analyze the statistical laws of the second target fine-tuning gear values that are the same as the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

[0063] In this step, through the linear scanning method, by testing the fine-tuning gear values of a large number of flash memory chips, the target values of the fine-tuning gear values of these large numbers of flash memory chips are obtained. Thus, based on this data and according to statistical methods, the distribution law of the fine-tuning gear values of the flash memory chips is obtained.

[0064] In a further optimized solution, the probability distribution information of the actual fine-tuning gear value is the normal distribution probability information of the actual fine-tuning gear value.

[0065] In a further optimized solution, the range of the predetermined quantity is from 1000 to 20000.

[0066] Based on the same idea, the embodiments of this specification also provide a device corresponding to the above method. Figure 4 For the embodiment of this specification, it provides a Figure 3 structural schematic diagram of a fine-tuning device for a reference circuit of a flash memory chip. As Figure 4 shown, the device may include:

[0067] A fine-tuning gear value probability distribution acquisition module 402, configured to acquire the probability distribution information of the fine-tuning gear historical data of the flash memory chip; the data types of the fine-tuning gear historical data are the programming voltage of the flash memory chip in the programming state or the erasing voltage in the erasing state.

[0068] A fine-tuning gear value discretization module 404, configured to set a first interval range of the fine-tuning gear values, and discretize the fine-tuning gear values within the first interval range according to a predetermined step size to obtain a first quantity of fine-tuning gear values.

[0069] A fine-tuning gear value sorting module 406, configured to sort all the fine-tuning gear values in the first quantity of fine-tuning gear values according to the magnitude order of the probability values in the probability distribution information to obtain a second quantity of fine-tuning gear values that is the same as the value of the first quantity.

[0070] A fine-tuning gear value testing module 408, configured to, for a flash memory chip to be tested, sequentially select a fine-tuning gear value to be set from the second quantity of fine-tuning gear values, and test the flash memory chip to be tested based on the fine-tuning gear value to be set. When the absolute value of the difference between the measured value obtained from the test and a pre-set target value is less than a predetermined threshold, set the fine-tuning gear value to be set as a first target fine-tuning gear value;

[0071] Among them, in the fine-tuning gear value probability distribution acquisition module 402, obtaining the probability distribution information of the fine-tuning gear historical data of the flash memory chip specifically includes: pre-obtaining a predetermined number of flash memory chips, and setting a second interval range consistent with the first interval range; based on the second interval range, testing the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values consistent with the predetermined number of values; analyzing the statistical law of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

[0072] Based on the same idea, an embodiment of this specification also provides a device corresponding to the above method.

[0073] Figure 5 For the corresponding one provided by the embodiment of this specification Figure 3 is a schematic structural diagram of a fine-tuning device for a flash memory chip reference circuit. As Figure 5 shown, the device 500 may include:

[0074] At least one processor 510; and,

[0075] A memory 530 communicatively connected to the at least one processor; wherein,

[0076] The memory 530 stores instructions 520 executable by the at least one processor 510, and when the instructions are executed by the at least one processor 510, the at least one processor 510 is enabled to:

[0077] Obtain the probability distribution information of the fine-tuning gear historical data of the flash memory chip; the data type of the fine-tuning gear historical data is the programming voltage of the flash memory chip in the programming state or the erasing voltage in the erasing state;

[0078] Set a first interval range of the fine-tuning gear values, and discretize the fine-tuning gear values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear values;

[0079] Based on the magnitude order of the probability values in the probability distribution information, sort all the fine-tuning gear values in the first number of fine-tuning gear values to obtain a second number of fine-tuning gear values consistent with the first number of values;

[0080] For the flash memory chip to be tested, sequentially select the fine-tuning gear value to be set from the second number of fine-tuning gear values, and test the flash memory chip to be tested based on the fine-tuning gear value to be set. When the absolute value of the difference between the measured value obtained by the test and a preset target value is less than a predetermined threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value;

[0081] Among them, obtaining the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chips specifically includes: pre-obtaining a predetermined number of flash memory chips, and setting a second range consistent with the first range; based on the second range, testing the fine-tuning gear position values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear position values consistent with the predetermined number of values; analyzing the statistical rules of the second target fine-tuning gear position values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear position values of the predetermined number of flash memory chips.

[0082] Based on the same idea, an embodiment of this specification also provides a computer-readable medium corresponding to the above method. Computer-readable instructions are stored on the computer-readable medium, and the computer-readable instructions can be executed by a processor to implement the following method:

[0083] Obtaining the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chips; the data types of the historical data of the fine-tuning gear positions are the programming voltages of the flash memory chips in the programming state or the erasing voltages in the erasing state;

[0084] Setting a first range of fine-tuning gear position values, discretizing the fine-tuning gear position values within the first range according to a predetermined step size to obtain a first number of fine-tuning gear position values;

[0085] Based on the magnitude order of the probability values in the probability distribution information, sorting all the fine-tuning gear position values in the first number of fine-tuning gear position values to obtain a second number of fine-tuning gear position values consistent with the first number of values;

[0086] For the flash memory chip to be tested, sequentially select the fine-tuning gear position value to be set from the second number of fine-tuning gear position values, and test the flash memory chip to be tested based on the fine-tuning gear position value to be set. When the absolute value of the difference between the measured value obtained by the test and a pre-set target value is less than a predetermined threshold, set the fine-tuning gear position value to be set as the first target fine-tuning gear position value;

[0087] Among them, obtaining the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chips specifically includes: pre-obtaining a predetermined number of flash memory chips, and setting a second range consistent with the first range; based on the second range, testing the fine-tuning gear position values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear position values consistent with the predetermined number of values; analyzing the statistical rules of the second target fine-tuning gear position values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear position values of the predetermined number of flash memory chips.

[0088] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0089] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software improvements (improvements to method flows). However, with the development of technology, many method flow improvements today can be regarded as direct improvements to hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented using a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is an integrated circuit whose logical function is determined by the user programming the device. Designers can program themselves to "integrate" a digital character system onto a single PLD, without having to ask a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a Hardware Description Language (HDL). There is not just one type of HDL, but many, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be aware that by simply performing a little logical programming on the method flow using the above-mentioned several hardware description languages and programming it into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.

[0090] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to logically program the method steps to enable the controller to be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. to achieve the same function. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or structures within the hardware component.

[0091] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0092] For the convenience of description, when describing the above devices, they are described separately as various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0093] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program code.

[0094] The present invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each flow and / or block of the flowchart illustrations and / or block diagrams, and combinations of flows and / or blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus create means for implementing the functions specified in the flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0095] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in the flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0097] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0098] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0099] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0100] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0101] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0102] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0103] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and variations can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A fine-tuning method for a reference circuit of a flash memory chip, characterized in that, The method includes: Obtaining the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip; the data types of the historical data of the fine-tuning gear positions are the programming voltages of the flash memory chip in the programming state or the erasing voltages in the erasing state; Setting a first interval range of the fine-tuning gear position values, and discretizing the fine-tuning gear position values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear position values; Sorting all the fine-tuning gear position values in the first number of fine-tuning gear position values according to the magnitude order of the probability values in the probability distribution information to obtain a second number of fine-tuning gear position values that is the same as the number of the first number of values; For the flash memory chip to be tested, sequentially select the fine-tuning gear position value to be set from the second number of fine-tuning gear position values, and test the flash memory chip to be tested based on the fine-tuning gear position value to be set. When the absolute value of the difference between the measured value obtained from the test and a preset target value is less than a predetermined threshold, set the fine-tuning gear position value to be set as the first target fine-tuning gear position value; Wherein, the obtaining of the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip specifically includes: Pre-obtaining a predetermined number of flash memory chips, and setting a second interval range that is the same as the first interval range; Based on the second interval range, testing the fine-tuning gear position values of the predetermined number of flash memory chips by the linear scanning method to obtain a second target fine-tuning gear position value that is the same as the number of the predetermined number of values; Analyzing the statistical law of the second target fine-tuning gear position values that are the same as the number of the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear position values of the predetermined number of flash memory chips.

2. The fine-tuning method of the flash memory chip reference circuit according to claim 1, characterized in that The probability distribution information of the actual fine-tuning gear position values is the normal distribution probability information of the actual fine-tuning gear position values.

3. The fine-tuning method of the flash memory chip reference circuit according to claim 1, wherein The range of the predetermined number is from 1000 to 20000.

4. A fine-tuning device for a reference circuit of a flash memory chip, characterized in that, Including: A fine-tuning gear position value probability distribution obtaining module, configured to obtain the probability distribution information of the historical data of the fine-tuning gear positions of the flash memory chip; The data types of the historical data of the fine-tuning gear positions are the programming voltages of the flash memory chip in the programming state or the erasing voltages in the erasing state; A fine-tuning gear position value discretization module, configured to set a first interval range of the fine-tuning gear position values, and discretize the fine-tuning gear position values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear position values; A fine-tuning gear position value sorting module, configured to sort all the fine-tuning gear position values in the first number of fine-tuning gear position values according to the magnitude order of the probability values in the probability distribution information to obtain a second number of fine-tuning gear position values that is the same as the number of the first number of values; A fine-tuning gear position value testing module, configured to, for the flash memory chip to be tested, sequentially select the fine-tuning gear position value to be set from the second number of fine-tuning gear position values, and test the flash memory chip to be tested based on the fine-tuning gear position value to be set. When the absolute value of the difference between the measured value obtained from the test and a preset target value is less than a predetermined threshold, set the fine-tuning gear position value to be set as the first target fine-tuning gear position value; Among them, the obtaining of the probability distribution information of the fine-tuning gear value historical data of the flash memory chip in the fine-tuning gear value probability distribution obtaining module specifically includes: pre-obtaining a predetermined number of flash memory chips, setting a second interval range consistent with the first interval range; based on the second interval range, testing the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values consistent with the predetermined number of values; analyzing the statistical rules of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

5. A fine-tuning device for a reference circuit of a flash memory chip, characterized in that, Including: At least one processor; And, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to: Obtain the probability distribution information of the fine-tuning gear value historical data of the flash memory chip; the data types of the fine-tuning gear value historical data are the programming voltage of the flash memory chip in the programming state or the erasing voltage in the erasing state; Set a first interval range of the fine-tuning gear values, and discretize the fine-tuning gear values within the first interval range according to a predetermined step size to obtain a first number of fine-tuning gear values; Based on the magnitude order of the probability values in the probability distribution information, sort all the fine-tuning gear values among the first number of fine-tuning gear values to obtain a second number of fine-tuning gear values consistent with the first number of values; For the flash memory chip to be tested, sequentially select the fine-tuning gear value to be set from the second number of fine-tuning gear values, and test the flash memory chip to be tested based on the fine-tuning gear value to be set. When the absolute value of the difference between the measured value obtained by the test and a preset target value is less than a predetermined threshold, set the fine-tuning gear value to be set as the first target fine-tuning gear value; Among them, the obtaining of the probability distribution information of the fine-tuning gear value historical data of the flash memory chip specifically includes: pre-obtaining a predetermined number of flash memory chips, setting a second interval range consistent with the first interval range; based on the second interval range, testing the fine-tuning gear values of the predetermined number of flash memory chips by the linear scanning method to obtain second target fine-tuning gear values consistent with the predetermined number of values; analyzing the statistical rules of the second target fine-tuning gear values consistent with the predetermined number of values to obtain the probability distribution information of the actual fine-tuning gear values of the predetermined number of flash memory chips.

6. A computer-readable medium having computer-readable instructions stored thereon, the computer-readable instructions being executable by a processor to implement the fine-tuning method of the flash memory chip reference circuit according to any one of claims 1 to 3.

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