Integrated circuit data access method, device, system, equipment and chip

Abstract

The present disclosure provides a data memory access method, apparatus, system, device and chip for an integrated circuit, wherein the method comprises: detecting a data memory access request sent by a requesting end, and detecting a target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on an idle identifier among a plurality of preset identifiers; determining a memory access identifier of the data memory access request based on the target dynamic identifier found; executing the data memory access request at a responding end based on the memory access identifier to obtain a data memory access result, and returning the data memory access result to the requesting end based on the memory access identifier.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular to a data access method, device, system, equipment and chip for an integrated circuit. Background Art

[0002] With the continuous development of artificial intelligence and high-performance computing, the amount of data that needs to be processed by the computing system is becoming increasingly large, and a large amount of data transmission is required during the computing process. However, in the related art, an ID is usually assigned to each computing unit in the computing system to execute data request instructions according to the ID. Only after the data request instruction is completed will the ID of the data request instruction be released; after that, the next data request instruction of the computing unit can be executed based on the ID. When the amount of data that the computing system needs to transmit is large or the storage level of the computing system is very deep, when the data processing process is executed for the corresponding computing unit through the ID, the processing performance of the computing system will be reduced, resulting in the inability of existing data storage technology to meet the high-performance computing requirements of the computing unit. Summary of the invention

[0003] The embodiments of the present disclosure at least provide a method, device, system, equipment and chip for accessing data of an integrated circuit.

[0004] In a first aspect, an embodiment of the present disclosure provides a data memory access device of an integrated circuit, characterized in that it includes: a request detection unit, configured to detect a data memory access request sent by a requesting end, and detect a target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on an idle identifier among multiple preset identifiers; an access identifier generation unit, configured to determine an access identifier of the data memory access request based on the target dynamic identifier found; a request execution unit, configured to execute the data memory access request at a responding end based on the access identifier, obtain a data memory access result, and return the data memory access result to the requesting end based on the access identifier.

[0005] It can be known from the above description that the target dynamic identifier to be allocated can be dynamically generated in advance based on the idle identifiers in multiple preset identifiers; after the data access request sent by the request end is detected, the target dynamic identifier to be allocated can be allocated to the data access request as the access identifier, so as to execute the data access request according to the access identifier. Through this processing method, it is possible to dynamically allocate an access identifier for each detected data access request after the corresponding data access request is detected, thereby alleviating the problem of data access efficiency caused by allocating an ID to each computing unit in the prior art, thereby improving the efficiency of data access and meeting the high-performance computing requirements of the computing unit.

[0006] In an optional embodiment, the request detection unit is further configured to: obtain the value of the status data bit of the identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification; and when it is determined that the value of the status data bit is the target value, determine that the preset identification contained in the identification register is the target dynamic identification.

[0007] In the above implementation, the value of the status data bit of the identification register can be determined to determine whether the identification register contains the target dynamic identification, so as to complete the detection of the target dynamic identification to be allocated, thereby simplifying the detection process of the target dynamic identification and improving the detection efficiency.

[0008] In an optional implementation, the data access request is a read request, and the access identifier is a read identifier; the access identifier generation unit includes: a read identifier generation unit; the read identifier generation unit is configured to determine the target dynamic identifier found as the read identifier of the read request.

[0009] In the above implementation, the target dynamic identifier contained in the identifier register can be determined as the read identifier corresponding to the read request, thereby saving the time for generating the read identifier corresponding to the read request and improving the processing efficiency of the system. At the same time, by generating the target dynamic identifier in advance and saving it in the identifier register, the delay problem caused by the method of searching for an idle identifier after the data access request arrives and determining the access identifier corresponding to the data access request based on the idle identifier in the prior art can be solved, thereby further improving the performance of the system.

[0010] In an optional embodiment, the data memory access request is a write request, and the memory access identifier is a write identifier; the memory access identifier generation unit includes: a write identifier generation unit; the write identifier generation unit is configured to determine the data write address corresponding to the write request in the response end when the target dynamic identifier is found; and determine the write identifier based on the numerical values ​​of multiple preset consecutive data bits in the data write address.

[0011] In the above implementation, when the target dynamic identifier is found, the write identifier corresponding to the write request can be determined based on the data write address corresponding to the write request in the response end, so that the write request corresponding to each data write address can be determined more clearly and accurately.

[0012] In an optional embodiment, when the data memory access request includes at least one write request corresponding to the same data write address, and the memory access identifier is a write identifier; the request execution unit is configured to: obtain a target mapping linked list; the target mapping linked list is used to indicate the mapping relationship between the write identifier and the target dynamic identifier of each write request, and the mapping relationship is used to indicate the execution order of the at least one write request; based on the target mapping linked list, execute each write request at the response end to obtain the corresponding data memory access result.

[0013] In the above implementation, by obtaining the target mapping linked list and executing each write request at the response end based on the target mapping linked list, the write order of multiple write requests for the same data write address can be guaranteed, thereby ensuring the accuracy of the obtained data access result.

[0014] In an optional embodiment, the request execution unit is also configured to: obtain the first target dynamic identifier stored at the first address in the response end linked list of the target mapping linked list; the first address is an address determined based on the write identifier; determine a target write request that matches the first target dynamic identifier among multiple write requests, and execute the target write request to obtain a corresponding data access result.

[0015] In the above implementation, by obtaining the first target dynamic identifier stored in the response end linked list, determining and executing the target write request that matches the first target dynamic identifier, and obtaining the data access result, the execution order of the target write request in each write request can be guaranteed, thereby ensuring the matching degree and accuracy of the data access result and the data access request.

[0016] In an optional embodiment, the request execution unit also includes: a first linked list update unit; the first linked list update unit is configured to determine a second target dynamic identifier in the dynamic identifier linked list of the target mapping linked list; wherein the second target dynamic identifier is a target dynamic identifier stored in the dynamic identifier linked list with the first target dynamic identifier as the address; and, update the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier.

[0017] In the above implementation, the execution order of each write request can be controlled by determining the second target dynamic identifier in the dynamic identifier linked list of the target mapping linked list, and updating the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier, thereby ensuring the accuracy of the data access results obtained after executing each write request.

[0018] In an optional embodiment, when the data memory access request includes at least one write request corresponding to the same data write address, the device also includes: a second linked list update unit; the second linked list update unit is configured to update the target mapping linked list based on the write identifier of the write request and the target dynamic identifier to be allocated after determining the memory access identifier of the data memory access request based on the target dynamic identifier found; the target mapping linked list is used to indicate the mapping relationship between the write identifier and the target dynamic identifier of each write request, and the mapping relationship is used to indicate the execution order of at least one of the write requests.

[0019] In an optional embodiment, the second linked list update unit is further configured to: if the write request is not the first request to write data to the data write address, then write the target dynamic identifier to be allocated in the request end linked list of the target mapping linked list at the address represented by the write identifier; write the target dynamic identifier to be allocated in the dynamic identifier linked list of the target mapping linked list at the address represented by the first dynamic identifier; the first dynamic identifier is the target dynamic identifier of the previous write request of the current write request.

[0020] In the above implementation, if the write request is not the first request to write data to the data write address, the target dynamic identifier to be allocated is written to the address represented by the write identifier in the request end linked list of the target mapping linked list, and to the address represented by the first dynamic identifier in the dynamic identifier linked list of the target mapping linked list, thereby realizing the update of the target mapping linked list, and then realizing the update of the execution order of each write request, thereby ensuring the accuracy of the execution order of each write request, and then ensuring the accuracy of the obtained data access result.

[0021] In an optional embodiment, the memory access identifier generation unit is further configured to: after determining the memory access identifier of the data memory access request based on the target dynamic identifier found, store the target address information carried in the data memory access request in a storage location with the target dynamic identifier as the address in the local storage unit; wherein the target address information is used to indicate the storage location of the data memory access result in the requesting end.

[0022] In the above implementation, the target address information carried by the read request and the write request can be stored in the same local storage unit, thereby solving the resource waste problem caused by storing the target address information carried by the read request and the write request in different local storage units in the prior art.

[0023] In an optional embodiment, the request execution unit includes: an information recovery unit, configured to determine target address information in a local storage unit based on the memory access identifier; the target address information is used to indicate the storage location of the response result in the request end; and a response return unit, configured to return the data memory access result and the target address information to the request end.

[0024] In the above implementation, the target address information can be determined in the local storage unit based on the memory access identifier, and the data memory access result and the target address information can be returned to the requesting end, thereby ensuring the accuracy of the data memory access result when it is returned to the requesting end.

[0025] In a second aspect, an embodiment of the present disclosure also provides a data memory access system for an integrated circuit, comprising: a requesting end, for generating and sending a data memory access request; a processing end, for detecting a target dynamic identifier to be allocated after receiving the data memory access request sent by the requesting end, and determining a memory access identifier of the data memory access request based on the found target dynamic identifier, and sending a data memory access request carrying the memory access identifier to a responding end; wherein the target dynamic identifier is dynamically generated based on an idle identifier among multiple preset identifiers; a responding end, for executing the data memory access request based on the memory access identifier, obtaining a data memory access result, and returning the data memory access result to the requesting end through the processing end based on the memory access identifier.

[0026] In a third aspect, an embodiment of the present disclosure further provides a data access method for an integrated circuit, comprising:

[0027] Detect the data memory access request sent by the requesting end, and detect the target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on the idle identifier among multiple preset identifiers; determine the memory access identifier of the data memory access request based on the found target dynamic identifier; execute the data memory access request at the responding end based on the memory access identifier, obtain the data memory access result, and return the data memory access result to the requesting end based on the memory access identifier.

[0028] In a fourth aspect, an embodiment of the present disclosure further provides a chip, characterized in that it comprises a data access device of an integrated circuit as described in any one of the above items.

[0029] In a fifth aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the above-mentioned third aspect, or the steps in any possible implementation of the third aspect, or include the chip included in the above-mentioned fourth aspect are executed.

[0030] In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned third aspect or any possible implementation of the third aspect are executed.

[0031] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0033] Figure 1 A flow chart of a data access method for an integrated circuit provided by an embodiment of the present disclosure is shown;

[0034] Figure 2 A flowchart of a method for executing a data access request at a response end based on a memory access identifier and obtaining a data access result provided by an embodiment of the present disclosure is shown;

[0035] Figure 3 A schematic diagram of a target mapping linked list provided by an embodiment of the present disclosure is shown;

[0036] Figure 4 A schematic diagram of a data access system for an integrated circuit provided by an embodiment of the present disclosure is shown;

[0037] Figure 5 A schematic diagram showing another integrated circuit data access system provided by an embodiment of the present disclosure is shown;

[0038] Figure 6 A schematic diagram showing a data access device of an integrated circuit provided by an embodiment of the present disclosure is shown;

[0039] Figure 7 A schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0042] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0043] Research has found that with the continuous development of artificial intelligence and high-performance computing, the amount of data that the computing system needs to process is becoming increasingly large, and a large amount of data transmission is required during the computing process. However, in the related art, an ID is usually assigned to each computing unit in the computing system to execute data request instructions according to the ID. Only after the data request instruction is completed will the ID of the data request instruction be released; after that, the next data request instruction of the computing unit can be executed based on the ID. When the amount of data that the computing system needs to transmit is large or the storage level of the computing system is very deep, when the data processing process is executed for the corresponding computing unit through the ID, the processing performance of the computing system will be reduced, resulting in the inability of existing data storage technology to meet the high-performance computing requirements of the computing unit.

[0044] Based on the above research, the present disclosure provides a data access method for an integrated circuit. It can be seen from the above description that a target dynamic identifier to be allocated can be dynamically generated in advance based on the idle identifiers in a plurality of preset identifiers; after detecting a data access request sent by a requesting end, the target dynamic identifier to be allocated can be assigned to the data access request as an access identifier to execute the data access request according to the access identifier. Through this processing method, after detecting the corresponding data access request, a dynamic allocation of an access identifier can be achieved for each detected data access request, thereby alleviating the problem of data access efficiency caused by allocating an ID to each computing unit in the prior art, thereby improving the efficiency of data access and meeting the high-performance computing requirements of the computing unit.

[0045] To facilitate understanding of this embodiment, a data access method for an integrated circuit disclosed in the embodiment of the present disclosure is first introduced in detail. The executor of the data access method for the integrated circuit provided in the embodiment of the present disclosure is generally a computer device with certain computing capabilities.

[0046] See also Figure 1 FIG. 1 is a flowchart of a data access method for an integrated circuit provided in an embodiment of the present disclosure, wherein the method comprises steps S101 to S105, wherein:

[0047] S101: Detecting a data access request sent by a requesting end, and detecting a target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on an idle identifier among a plurality of preset identifiers.

[0048] Here, the request end may be a component in a memory access unit of a processor. Specifically, the processor may include an instruction processing unit and an instruction execution unit, wherein the memory access unit is a component in the instruction execution unit for executing data reading and data writing.

[0049] In the disclosed embodiment, the data access request sent by the requesting end may be a data read request and / or a data write request, wherein the data read request is an instruction for the requesting end to request to obtain data from the storage system, and the data write request is an instruction for the requesting end to request to write data to the storage system.

[0050] In the disclosed embodiment, multiple identifiers (ie, preset identifiers) for executing the data access request initiated by the requesting end may be pre-allocated. In addition, an idle identifier may be selected from the pre-allocated multiple preset identifiers to generate a target dynamic identifier to be allocated.

[0051] The number of preset identifiers is N, and N is a natural number greater than 1. For example, the value of N can be 10, 32, or 100. The present disclosure does not specifically limit the number of preset identifiers, and is based on actual needs.

[0052] S103: Determine a memory access identifier of the data memory access request based on the found target dynamic identifier.

[0053] In an embodiment of the present disclosure, after detecting a data memory access request sent by a requesting end, it is necessary to detect whether a target dynamic identifier has been generated, and if it is detected that the target dynamic identifier has been generated, the target dynamic identifier can be assigned to the detected data memory access request, and then the memory access identifier of the data memory access request can be determined based on the target dynamic identifier.

[0054] S105: Execute the data memory access request at the responding end based on the memory access identifier to obtain a data memory access result, and return the data memory access result to the requesting end based on the memory access identifier.

[0055] Here, the responding end and the requesting end may be devices in the same electronic device. For example, the requesting end may be a processor in the electronic device, and the responding end may be a storage system in the electronic device for storing or writing data, such as a local database.

[0056] In addition, the responding end and the requesting end may also be devices in different electronic devices. For example, the requesting end may be a processor in a terminal device, and the responding end may be a storage system in a server, such as a database.

[0057] In the disclosed embodiment, a corresponding data access request can be executed on the responding end based on the access identifier of the data access request to obtain a data access result. Afterwards, the obtained data access result can be returned to the requesting end based on the access identifier. When the data access request is a read request, the data access result can be a data read result; when the data access request is a write request, the data access result can be a data write result.

[0058] The data access result includes information such as the read data and the access identifier of the read request; the data write result includes information such as the access identifier of the write request, the target dynamic identifier of the write request, the write result of the write request (for example, write success, write failure), and the data write position of the write request at the response end.

[0059] It can be known from the above description that the target dynamic identifier to be allocated can be dynamically generated in advance based on the idle identifiers in multiple preset identifiers; after the data access request sent by the request end is detected, the target dynamic identifier to be allocated can be allocated to the data access request as the access identifier, so as to execute the data access request according to the access identifier. Through this processing method, it is possible to dynamically allocate an access identifier for each detected data access request after the corresponding data access request is detected, thereby alleviating the problem of data access efficiency caused by allocating an ID to each computing unit in the prior art, thereby improving the efficiency of data access and meeting the high-performance computing requirements of the computing unit.

[0060] In an optional implementation, with respect to S101: detecting a target dynamic identifier to be allocated, the following steps are specifically included:

[0061] Step S1011: Acquire the value of the status data bit of the identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification;

[0062] Step S1012: when it is determined that the value of the status data bit is the target value, the preset identifier contained in the identifier register is determined to be the target dynamic identifier.

[0063] Here, the identification register may be understood as a register used to store a target dynamic identification to be allocated.

[0064] In the disclosed embodiment, whether the identification register contains a preset identification can be determined by the status data bit of the identification register. The status data bit is represented as did_vld, and the status data bit can be understood as a circuit signal. For example, when the value of the status data bit did_vld is 0, the circuit signal corresponding to the status data bit did_vld is a low level, and at this time, it indicates that the identification register does not contain a preset identification. When the value of the status data bit did_vld is 1, the circuit signal corresponding to the status data bit did_vld is a high level, and at this time, it indicates that the identification register contains a preset identification.

[0065] Therefore, it can be known from the above description that the above target value can be understood as 1 (i.e., the state data bit is at a high level). In the embodiment of the present disclosure, when it is determined that the value of the state data bit is the target value, it can be determined that the flag register contains a preset flag, and the preset flag is determined as the target dynamic flag.

[0066] In addition, when it is determined that the value of the state data bit did_vld is not the target value (that is, the data of the state data bit is 0), it indicates that the target dynamic identifier to be allocated is not included in the identification register. In this case, it indicates that the corresponding target dynamic identifier has not been generated in multiple preset identifiers. If it is determined that a plurality of preset identifiers contain an identifier in an idle state, at this time, the target dynamic identifier to be allocated at the current moment can be determined based on the identifier in the idle state, and the target dynamic identifier to be allocated is saved in the identification register. At this time, the value of the state data bit is updated to 1. If it is determined that a plurality of preset identifiers do not contain an identifier in an idle state, then it is necessary to wait for a plurality of preset identifiers to contain an identifier in an idle state before generating the target dynamic identifier to be allocated.

[0067] In the above implementation, the value of the status data bit of the identification register can be determined to determine whether the identification register contains the target dynamic identification, so as to complete the detection of the target dynamic identification to be allocated, thereby simplifying the detection process of the target dynamic identification and improving the detection efficiency.

[0068] In an optional implementation, when the data memory access request is a read request and the memory access identifier is a read identifier, for S103: determining the memory access identifier of the data memory access request based on the target dynamic identifier found, specifically includes: determining the target dynamic identifier found as the read identifier of the read request.

[0069] In an embodiment of the present disclosure, when the data access request sent by the requesting end is a read request, the target dynamic identifier in the found identifier register may be determined as the read identifier corresponding to the read request.

[0070] In a specific implementation, when it is detected that the data access request sent by the requesting end is a read request, the value of the status data bit of the identification register can be first obtained; wherein the status data bit is used to indicate whether the identification register contains a preset identification, and when it is determined that the value of the status data bit is a target value, the preset identification contained in the identification register is determined to be the target dynamic identification. At this time, the target dynamic identification can be determined as the read identification corresponding to the read request by the read identification generation unit.

[0071] In the above implementation, the target dynamic identifier contained in the identifier register can be determined as the read identifier corresponding to the read request, thereby saving the time for generating the read identifier corresponding to the read request and improving the processing efficiency of the system. At the same time, by generating the target dynamic identifier in advance and saving it in the identifier register, the delay problem caused by the method of searching for an idle identifier after the data access request arrives and determining the access identifier corresponding to the data access request based on the idle identifier in the prior art can be solved, thereby further improving the performance of the system.

[0072] In an optional implementation, when the data memory access request is a write request and the memory access identifier is a write identifier, S103: determining the memory access identifier of the data memory access request based on the found target dynamic identifier specifically includes the following steps:

[0073] Step S1031: when the target dynamic identifier is found, determining a data write address corresponding to the write request in the response end;

[0074] Step S1032: determining the write flag based on the values ​​of a plurality of preset consecutive data bits in the data write address.

[0075] In an embodiment of the present disclosure, when it is detected that the data access request sent by the requesting end is a write request, the value of the status data bit of the identification register can be first obtained; wherein, the status data bit is used to indicate whether the identification register contains a preset identification, and when it is determined that the value of the status data bit is a target value, the preset identification contained in the identification register is determined to be the target dynamic identification. Afterwards, a write identification corresponding to the write request can be generated based on the target dynamic identification. When it is determined that the value of the status data bit is not the target value, at this time, it can be determined that the identification register does not store the target dynamic identification determined based on the preset identification. At this time, it is necessary to determine an idle identification from multiple preset identifications and save the idle identification in the identification register. Afterwards, based on determining the idle identification as a new target dynamic identification to be allocated, the step of determining the corresponding write identification for the write request can be performed.

[0076] Here, after detecting that the identification register contains the target dynamic identification to be allocated, the method of determining the corresponding write identification for the write request is to ensure that the writing order of the write request at the responding end is correct.

[0077] In specific implementation, first, determine the data write address corresponding to the write request in the response end. Then, determine the values ​​of multiple preset continuous data bits in the data write address. At this time, the determined values ​​of the multiple preset continuous data bits can be determined as the write identifier corresponding to the write request.

[0078] In the embodiment of the present disclosure, the number of the plurality of preset consecutive data bits may be M. The number M is calculated as follows: M=log2N, where N is the number of the plurality of preset identifiers.

[0079] For example, when N is 32, based on the above calculation formula, it can be determined that the value of M is 5. At this time, the values ​​of 5 consecutive data bits can be determined from the above data write address as the write identifier corresponding to the write request.

[0080] The write identifier may be a value taken from the first bit of the data write address, and the values ​​of multiple preset consecutive data bits are intercepted as the write identifier, or a value taken from the second bit of the data write address, and the values ​​of multiple preset consecutive data bits are intercepted as the write identifier. The present disclosure does not specifically limit the position where the data write address starts to be taken, which is subject to implementation.

[0081] In the above implementation, when the target dynamic identifier is found, the write identifier corresponding to the write request can be determined based on the data write address corresponding to the write request in the response end, so that the write request corresponding to each data write address can be determined more clearly and accurately.

[0082] In an optional embodiment, if Figure 2 As shown, when the data memory access request includes at least one write request corresponding to the same data write address, and the memory access identifier is a write identifier, for S105: executing the data memory access request at the response end based on the memory access identifier to obtain a data memory access result, specifically includes the following steps:

[0083] Step S21: obtaining a target mapping linked list; the target mapping linked list is used to indicate a mapping relationship between the write identifier and a target dynamic identifier of each write request, and the mapping relationship is used to indicate an execution order of the at least one write request;

[0084] Step S22: executing each write request at the response end based on the target mapping linked list to obtain corresponding data access results.

[0085] It can be seen from the above steps that, in the case where the target dynamic identifier is found, the write identifier can be determined based on the data write address corresponding to the write request in the response end.

[0086] Meanwhile, in the disclosed embodiment, the found target dynamic identifier to be allocated may be determined as the target dynamic identifier of the write request, and the target dynamic identifier of the write request may be saved in the target mapping linked list.

[0087] In the disclosed embodiment, after each data access request is detected, a target dynamic identifier can be assigned to each data access request. For example, after each write request is detected, a corresponding target dynamic identifier can be assigned to each write request. When the data write addresses corresponding to the write requests at the response end are the same, the write identifiers determined for the write requests are the same. In general, corresponding target dynamic identifiers are assigned to different write requests, and the same write identifier is determined for write requests with the same data write address.

[0088] In an optional embodiment, after detecting a new write request, the write identifier of the write request can be determined; then, the target dynamic identifier with the write identifier as the address is searched in the target mapping linked list; if the target dynamic identifier is found, it can indicate that before the new write request, the requesting end has initiated at least one write request corresponding to the same data write address to the responding end.

[0089] In another optional embodiment, after detecting a new write request, it is also possible to search in historical write requests for a historical write request corresponding to the same data write address as the new write request, and when the historical write request is found, it is determined that before the new write request, the requesting end has already initiated at least one write request corresponding to the same data write address to the responding end.

[0090] When it is determined that the data access request includes multiple write requests corresponding to the same data write address, when executing the multiple write requests on the responding end, it is necessary to execute the corresponding data write operations on the responding end according to the initiation order (or execution order) of the multiple write requests.

[0091] At this time, in order to ensure the execution order of write requests corresponding to the same data write address, a target mapping linked list needs to be set in advance to ensure the validity of the execution order of write requests corresponding to the same data write address through the target mapping linked list.

[0092] like Figure 3 As shown, the target mapping linked list includes three sub-linked lists, namely the request end linked list, the dynamic identification linked list and the response end linked list.

[0093] Here, the request end linked list is used to store the latest target dynamic identifier corresponding to each write identifier, wherein the latest target dynamic identifier is the target dynamic identifier of the latest write request corresponding to the write identifier.

[0094] The dynamic identifier chain table is used to store each target dynamic identifier corresponding to each write identifier and the order of each target dynamic identifier, wherein each corresponding target dynamic identifier can be understood as the target dynamic identifier of each write request corresponding to the write identifier.

[0095] The responder linked list includes the target dynamic identifier of the write request to be executed at the current moment, that is, the responder linked list is used to indicate the write request to be executed at the current moment to the responder.

[0096] In such Figure 3 The three sub-linked lists shown contain corresponding mapping relationships, and the specific mapping relationships can be expressed as follows:

[0097] The address of the latest target dynamic identifier stored in the request-side linked list is the corresponding write identifier; the address of the target dynamic identifier of the write request to be executed at the current moment stored in the response-side linked list is also the corresponding write identifier. The address of each target dynamic identifier stored in the dynamic identifier linked list is the previous target dynamic identifier. For example, the storage address of dynamic id2 is dynamic id1, and the storage address of dynamic id3 is dynamic id2.

[0098] In specific implementation, when the data access request includes at least one write request corresponding to the same data write address, each time a write request for the same data write address sent by the request end is detected and the target dynamic identifier to be assigned is detected, the found target dynamic identifier is assigned to the corresponding write request, and the target dynamic identifier is saved in the target mapping linked list. At this time, the target dynamic identifier of each write request can be obtained in the target mapping linked list, and the order in which the target dynamic identifier is saved in the target mapping linked list is the execution order of each write request. The specific implementation process of the target mapping linked list is described as follows:

[0099] Assume that the write identifier is write ID1, and the write requests corresponding to write ID1 are write request 1, write request 2 and write request 3 respectively; among them, the target dynamic identifier assigned to write request 1 is dynamic id1, the target dynamic identifier assigned to write request 2 is dynamic id2, and the target dynamic identifier assigned to write request 3 is dynamic id3.

[0100] When the first generation of write ID1 is detected, that is, when the first write request 1 to the data write address corresponding to write ID1 is detected, dynamic id1 is written into the request side linked list and the response side linked list respectively, where the write address of dynamic id1 is write ID1.

[0101] When the same write ID1 is detected to appear again, that is, when the second write request 2 to the data write address corresponding to write ID1 is detected, dynamic id2 is written to the position corresponding to write ID1 in the request end linked list, and dynamic id2 is written in the dynamic identification linked list, where the write address of dynamic id2 in the dynamic identification linked list is dynamic id1.

[0102] When the same write ID1 is detected to appear again, that is, the third write request 3 to the data write address corresponding to write ID1 is detected, dynamic ID3 is written to the position corresponding to write ID1 in the request end linked list, and dynamic ID3 is written in the dynamic identification linked list, where the write address of dynamic ID3 in the dynamic identification linked list is dynamic ID2.

[0103] In this case, the responder executes write request 1, write request 2, and write request 3 as follows:

[0104] When executing the above-mentioned write request 1, write request 2 and write request 3 at the responding end, the corresponding dynamic id can be read from the position corresponding to the write ID1 in the responding end linked list first. For example, the dynamic id1 can be read first, and the corresponding write request 1 can be determined based on the dynamic id1, and the write request 1 can be executed. After the write request 1 is successfully executed, the dynamic id2 is obtained in the dynamic identification linked list with the dynamic id1 as the address, and the dynamic id2 is stored in the position corresponding to the write ID1 in the responding end linked list. At this time, the responding end can read the corresponding dynamic id in the position corresponding to the write ID1 in the responding end linked list. For example, the dynamic id2 is read, and the corresponding write request 2 is determined based on the dynamic id2, and the write request 2 is executed. After the write request 2 is successfully executed, the dynamic id3 is obtained in the dynamic identification linked list with the dynamic id2 as the address, and the dynamic id3 is stored in the position corresponding to the write ID1 in the responding end linked list. At this time, the responding end can read the corresponding dynamic id3 in the position corresponding to the write ID1 in the responding end linked list, and determine the corresponding write request 3 based on the dynamic id3, and execute the write request 3.

[0105] After the responding end completes a write request, the data write result of the write request is obtained. Afterwards, the data write result can be returned to the requesting end to complete the response to the write request. At this point, the write request is completed. Afterwards, the target dynamic identifier allocated for the write request can be released (i.e., the target dynamic identifier is set to an idle state).

[0106] In the embodiment of the present disclosure, after the target mapping linked list described above is obtained, each write request can be executed on the response end based on the target mapping linked list, thereby obtaining the data access result corresponding to each write request.

[0107] In specific implementation, each write request can be executed based on the target dynamic identifier stored in the response end linked list in the target mapping linked list to obtain the corresponding data access result.

[0108] It should be noted here that the number of the at least one write request may be 2, 3, or 5. The present disclosure does not specifically limit the number of the at least one write request, which is subject to meeting actual needs.

[0109] Assume that, when the data write address is "data write address 1", the request end sends three write requests for "data write address 1", and the sending order is "write request 1", "write request 2", and "write request 3". At this time, assume that the write identifier determined based on "data write address 1" is "write ID 1", the target dynamic identifier determined for "write request 1" is "dynamic id 1", the target dynamic identifier determined for "write request 2" is "dynamic id 2", and the target dynamic identifier determined for "write request 3" is "dynamic id 3".

[0110] At this time, the target dynamic identifiers "dynamic id1", "dynamic id2" and "dynamic id3" corresponding to the above three write requests can be saved in the target mapping linked list in sequence according to the working principle of the target mapping linked list described above, such as Figure 3 In the three sub-lists shown.

[0111] Afterwards, each write request can be executed in sequence based on "dynamic id1", "dynamic id2" and "dynamic id3" contained in the target mapping linked list (i.e., first execute "write request 1" corresponding to "dynamic id1", then execute "write request 2" corresponding to "dynamic id2", and finally execute "write request 3" corresponding to "dynamic id3") to obtain the data access results of the above three write requests. The specific execution process is as described in "Response end to write request 1, write request 2 and write request 3" above, and will not be described in detail here.

[0112] In the above implementation, by obtaining the target mapping linked list and executing each write request at the response end based on the target mapping linked list, the write order of multiple write requests for the same data write address can be guaranteed, thereby ensuring the accuracy of the obtained data access result.

[0113] In an optional implementation, the above step S22: executing each write request at the response end based on the target mapping linked list specifically includes the following steps:

[0114] Step S31: obtaining a first target dynamic identifier stored at a first address in a response end linked list of the target mapping linked list; the first address is an address determined based on the write identifier;

[0115] Step S32: determining a target write request that matches the first target dynamic identifier from a plurality of write requests, and executing the target write request to obtain a corresponding data access result.

[0116] Here, the first target dynamic identifier is used to indicate the target dynamic identifier of the first write request initiated by the requesting end for the data write address. At this time, the storage address of the first target dynamic identifier is the address determined based on the write identifier (ie, the first address mentioned above).

[0117] In the embodiments of the present disclosure, Figure 3 As shown, the target mapping linked list may include a responder linked list. At this time, the first target dynamic identifier may be stored in the responder linked list at a first address.

[0118] For example, Figure 3 The target mapping linked list shown assumes that, when the write request includes the three write requests described above, it can be determined that the first address is the address determined based on "write ID1", the first target dynamic identifier is "dynamic id1", and the target write request matching the first target dynamic identifier is "write request 1".

[0119] When executing each write request on the responding end based on the target mapping linked list, first, obtain the first target dynamic identifier stored at the first address in the responding end linked list of the target mapping linked list. Then, determine the target write request matching the first target dynamic identifier among multiple write requests, and execute the target write request on the responding end, thereby obtaining the data access result corresponding to the target write request.

[0120] In the above implementation, by obtaining the first target dynamic identifier stored in the response end linked list, determining and executing the target write request that matches the first target dynamic identifier, and obtaining the data access result, the execution order of the target write request in each write request can be guaranteed, thereby ensuring the matching degree and accuracy of the data access result and the data access request.

[0121] In an optional embodiment, with respect to the above steps S31 to S32, the method of the present disclosure further includes the following steps:

[0122] Step S41: determining a second target dynamic identifier in the dynamic identifier chain table of the target mapping chain table; wherein the second target dynamic identifier is a target dynamic identifier stored in the dynamic identifier chain table with the first target dynamic identifier as the address;

[0123] Step S42: Update the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier.

[0124] In the embodiments of the present disclosure, Figure 3 As shown, the target mapping linked list may also include a dynamic identifier linked list. The number of target dynamic identifiers stored in the dynamic identifier linked list may be one or more. The present disclosure does not specifically limit the number of target dynamic identifiers stored in the dynamic identifier linked list. The number of target dynamic identifiers corresponding to the write requests other than the first write request sent for the same data write address shall prevail.

[0125] For example, when the number of write requests is 3 as described above, it can be determined that the number of target dynamic identifiers stored in the dynamic identifier chain list is 2, namely "dynamic id2" and "dynamic id3".

[0126] Here, the second target dynamic identifier is used to indicate the target dynamic identifier of a write request whose execution order is one position after the above target write request in each write request. At this time, the storage address of the second target dynamic identifier is the first target dynamic identifier.

[0127] In the disclosed embodiment, after executing the target write request to obtain the corresponding data access result, the second target dynamic identifier can be determined in the dynamic identifier linked list, and the first target dynamic identifier stored in the response end linked list can be updated to the second target dynamic identifier. Afterwards, a write request matching the second target dynamic identifier can be determined from multiple write requests, and the matching write request can be executed to obtain the corresponding data access result.

[0128] For example, Figure 3 In the target mapping linked list shown, when the number of target dynamic identifiers stored in the dynamic identifier linked list is 2 ("dynamic id2" and "dynamic id3"), the second target dynamic identifier can be determined to be "dynamic id2". Afterwards, the first target dynamic identifier (i.e., "dynamic id1") stored in the response end linked list can be updated to the second target dynamic identifier (i.e., "dynamic id2"). Afterwards, the write request that matches the second target dynamic identifier can be determined as "write request 2" among multiple write requests, and the "write request 2" can be executed to obtain the corresponding data access result.

[0129] In the above implementation, the execution order of each write request can be controlled by determining the second target dynamic identifier in the dynamic identifier linked list of the target mapping linked list, and updating the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier, thereby ensuring the accuracy of the data access results obtained after executing each write request.

[0130] In an optional implementation, when the data memory access request includes at least one write request corresponding to the same data write address, after determining the memory access identifier of the data memory access request based on the found target dynamic identifier, the disclosed method further includes:

[0131] The target mapping linked list is updated based on the write identifier of the write request and the target dynamic identifier to be allocated; the target mapping linked list is used to indicate the mapping relationship between the write identifier and the target dynamic identifier of each write request, and the mapping relationship is used to indicate the execution order of at least one of the write requests.

[0132] In the embodiment of the present disclosure, when the data access request includes at least one write request corresponding to the same data write address, the target mapping linked list can be updated based on the write identifier of the write request and the target dynamic identifier to be allocated. For example, Figure 3 The three sub-lists shown in the figure, the specific process of updating the target mapping list can be described as follows:

[0133] Step S51: if the write request is not the first request to write data to the data write address, then writing the target dynamic identifier to be allocated at the address represented by the write identifier in the request end linked list of the target mapping linked list;

[0134] Step S52: writing the target dynamic identifier to be allocated at the address represented by the first dynamic identifier in the dynamic identifier chain list of the target mapping chain list; the first dynamic identifier is the target dynamic identifier of the previous write request of the current write request.

[0135] Here, the first request may also be understood as a write request for performing a write operation to a certain data write address for the first time, for example, the write request 1 in the above embodiment.

[0136] In the embodiments of the present disclosure, Figure 3 As shown, the target mapping linked list may also include a request end linked list. At this time, the target dynamic identifier to be allocated may be written in the request end linked list of the target mapping linked list at the address represented by the write identifier. In addition, in the disclosed embodiment, the target dynamic identifier to be allocated may also be written in the dynamic identifier linked list of the target mapping linked list at the address represented by the first dynamic identifier.

[0137] For example, when at least one write request is the three write requests described above (respectively "write request 1", "write request 2", and "write request 3"), the write identifiers of the three write requests are "write ID 1", and the target dynamic identifiers to be allocated corresponding to each write request are "dynamic id 1", "dynamic id 2", and "dynamic id 3". At this time, the target mapping linked list can be updated according to the above "write ID 1", "dynamic id 1", "dynamic id 2", and "dynamic id 3", and the specific update is as follows:

[0138] When the first generation of write ID1 is detected, that is, when the first write request 1 to the data write address corresponding to write ID1 is detected, dynamic id1 is written into the request side linked list and the response side linked list respectively, where the write address of dynamic id1 is write ID1.

[0139] When the same write ID1 is detected to appear again, that is, when the second write request 2 to the data write address corresponding to write ID1 is detected, dynamic id2 is written to the position corresponding to write ID1 in the request end linked list, and dynamic id2 is written in the dynamic identification linked list, where the write address of dynamic id2 in the dynamic identification linked list is dynamic id1.

[0140] When the same write ID1 is detected to appear again, that is, the third write request 3 to the data write address corresponding to write ID1 is detected, dynamic ID3 is written to the position corresponding to write ID1 in the request end linked list, and dynamic ID3 is written in the dynamic identification linked list, where the write address of dynamic ID3 in the dynamic identification linked list is dynamic ID2.

[0141] In the above implementation, if the write request is not the first request to write data to the data write address, the target dynamic identifier to be allocated is written to the address represented by the write identifier in the request end linked list of the target mapping linked list, and to the address represented by the first dynamic identifier in the dynamic identifier linked list of the target mapping linked list, thereby realizing the update of the target mapping linked list, and then realizing the update of the execution order of each write request, thereby ensuring the accuracy of the execution order of each write request, and then ensuring the accuracy of the obtained data access result.

[0142] In an optional embodiment, the method disclosed herein also includes: after determining the memory access identifier of the data memory access request based on the target dynamic identifier found, storing the target address information carried in the data memory access request in a storage location with the target dynamic identifier as the address in a local storage unit; wherein the target address information is used to indicate the storage location of the data memory access result in the request end.

[0143] In the embodiment of the present disclosure, the target address information is used to indicate the storage location of the data access result in the requesting end. For example, the target address information may be identification information of a register in the requesting end.

[0144] In the embodiment of the present disclosure, after the memory access identifier of the data memory access request is determined based on the found target dynamic identifier, the target address information carried in the data memory access request can be stored in the local storage unit with the target dynamic identifier as the storage address.

[0145] Afterwards, a data access request can be executed on the responding end based on the access identifier to obtain a data access result, and the data access result can be returned to the requesting end based on the access identifier.

[0146] In the above implementation, the target address information carried by the read request and the write request can be stored in the same local storage unit, thereby solving the resource waste problem caused by storing the target address information carried by the read request and the write request in different local storage units in the prior art.

[0147] In an optional implementation, with respect to the above: returning the data access result to the requesting end based on the access identifier specifically includes the following process:

[0148] (1) determining target address information in a local storage unit based on the memory access identifier; the target address information is used to indicate a storage location of the response result in the requesting end;

[0149] (2) Returning the data access result and the target address information to the requesting end.

[0150] In the embodiment of the present disclosure, the target address information may be determined in the local storage unit based on the memory access identifier.

[0151] In specific implementation, when the access identifier is a read identifier, the found target dynamic identifier can be determined based on the read identifier. At this time, the storage information in the storage location with the target dynamic identifier as the address can be determined in the local storage unit as the target address information.

[0152] After the target address information is determined, the data access result and the corresponding target address information may be returned to the requesting end.

[0153] In the above implementation, the target address information can be determined in the local storage unit based on the memory access identifier, and the data memory access result and the target address information can be returned to the requesting end, thereby ensuring the accuracy of the data memory access result when it is returned to the requesting end.

[0154] Based on the same inventive concept, the presently disclosed embodiment also provides a data memory access system for an integrated circuit corresponding to the data memory access method for an integrated circuit. Since the principle of solving the problem by the system in the presently disclosed embodiment is similar to the data memory access method for the integrated circuit mentioned above in the presently disclosed embodiment, the implementation of the system can refer to the implementation of the method, and the repeated parts will not be repeated.

[0155] Reference Figure 4 , which is a schematic diagram of a data access system of an integrated circuit provided in an embodiment of the present disclosure, the system includes: a request end 41, a processing end 42, and a response end 43.

[0156] The request end 41 is used to generate and send a data access request.

[0157] The processing end 42 is used to detect the target dynamic identifier to be allocated after receiving the data access request sent by the requesting end, and determine the access identifier of the data access request based on the found target dynamic identifier, and send the data access request carrying the access identifier to the responding end; wherein the target dynamic identifier is dynamically generated based on the idle identifier among multiple preset identifiers.

[0158] Here, the process performed by the requesting end 41 and the processing end 42 is the same as the process performed by the above-mentioned steps S101 and S103 and their corresponding implementation methods, and will not be described in detail here.

[0159] The responding end 43 is used to execute the data memory access request based on the memory access identifier, obtain a data memory access result, and return the data memory access result to the requesting end through the processing end based on the memory access identifier.

[0160] Here, the process performed by the responding end 43 is the same as the process performed by the above-mentioned step S105 and its corresponding implementation method, and will not be described in detail here.

[0161] It can be known from the above description that the target dynamic identifier to be allocated can be dynamically generated in advance based on the idle identifiers in multiple preset identifiers; after the data access request sent by the request end is detected, the target dynamic identifier to be allocated can be allocated to the data access request as the access identifier, so as to execute the data access request according to the access identifier. Through this processing method, it is possible to dynamically allocate an access identifier for each detected data access request after the corresponding data access request is detected, thereby alleviating the problem of data access efficiency caused by allocating an ID to each computing unit in the prior art, thereby improving the efficiency of data access and meeting the high-performance computing requirements of the computing unit.

[0162] like Figure 5As shown, the processing end 42 also includes: a read identifier generation unit, a response return unit, an information recovery unit, a target dynamic identifier generation unit, a local storage unit, a target mapping linked list, and a write identifier generation unit.

[0163] The following will combine Figure 5 The data access memory system of the integrated circuit shown in the figure performs a detailed process of the data access memory method of the integrated circuit mentioned above, and the specific process is described as follows:

[0164] In the case where it is detected that the data access request sent by the requesting end is a read request, it is detected whether the target dynamic identifier generation unit generates a target dynamic identifier to be allocated based on multiple preset identifiers, and the target dynamic identifier to be allocated is saved in the identifier register. In the case where the target dynamic identifier is found from the identifier register, the target dynamic identifier can be determined as the read identifier of the above-mentioned read request based on the read identifier generation unit. At the same time, the target address information carried by the read request can be stored in the local storage unit at the address represented by the target dynamic identifier.

[0165] Then, the storage system (that is, the above-mentioned responding end) can execute the read request according to the read identifier and obtain the data reading result of the read request. At this time, the data reading result of the read request may include the read data and the target dynamic identifier. Afterwards, the target address information carried by the read request can be restored through the information recovery unit. In specific implementation, the information recovery unit can search the local storage unit for a storage location with the target dynamic identifier of the read request as the address, read the data stored in the storage location, and determine the read data as the target address information carried by the read request. Afterwards, the above-mentioned data access result and target address information can be returned to the requesting end through the response return unit, thereby completing the data read request.

[0166] In the case where it is detected that the data access request sent by the requesting end is a write request, it is detected whether the target dynamic identifier generation unit generates a target dynamic identifier to be allocated based on multiple preset identifiers, and the target dynamic identifier to be allocated is saved in the identifier register. In the case where the target dynamic identifier is found from the identifier register, the numerical values ​​of multiple preset continuous data bits of the data write address corresponding to the write request in the responding end can be determined as the write identifier based on the write identifier generation unit. At the same time, the target mapping linked list is updated based on the target dynamic identifier (the method for updating the target mapping linked list is as described above, and the present disclosure will not be described in detail here), and the target address information carried by the write request is stored in the local storage unit at the address represented by the target dynamic identifier.

[0167] Afterwards, the storage system (that is, the above-mentioned responding end) can execute the write request according to the write identifier and obtain the data access result of the write request. At this time, the data access result of the write request can include the access identifier of the write request and the target dynamic identifier at the address represented by the access identifier of the write request. Then, the target address information carried by the write request can be recovered through the information recovery unit. In specific implementation, the information recovery unit can search the local storage unit for a storage location with the target dynamic identifier of the write request as the address, read the data stored in the storage location, and determine the read data as the target address information carried by the write request. Finally, the above-mentioned data access result and target address information are returned to the requesting end through the response return unit, thereby completing the data write request.

[0168] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0169] Based on the same inventive concept, the embodiments of the present disclosure also provide a data memory access device for an integrated circuit corresponding to the data memory access method for an integrated circuit. Since the principle of solving the problem by the device in the embodiments of the present disclosure is similar to the data memory access method for the integrated circuit mentioned above in the embodiments of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0170] Reference Figure 6 , which is a schematic diagram of a data memory access device of an integrated circuit provided in an embodiment of the present disclosure, the device comprises: a request detection unit 61, a memory access identifier generation unit 62, and a request execution unit 63. Here, the data memory access device of the integrated circuit can be understood as the processing end 42 in the above embodiment, specifically:

[0171] The request detection unit 61 is used to detect the data access request sent by the request end, and detect the target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on the idle identifiers among the multiple preset identifiers;

[0172] A memory access identifier generating unit 62, configured to determine a memory access identifier of the data memory access request based on the found target dynamic identifier;

[0173] The request execution unit 63 is used to execute the data memory access request at the response end based on the memory access identifier, obtain the data memory access result, and return the data memory access result to the request end based on the memory access identifier.

[0174] It can be known from the above description that the target dynamic identifier to be allocated can be dynamically generated in advance based on the idle identifiers in multiple preset identifiers; after the data access request sent by the request end is detected, the target dynamic identifier to be allocated can be allocated to the data access request as the access identifier, so as to execute the data access request according to the access identifier. Through this processing method, it is possible to dynamically allocate an access identifier for each detected data access request after the corresponding data access request is detected, thereby alleviating the problem of data access efficiency caused by allocating an ID to each computing unit in the prior art, thereby improving the efficiency of data access and meeting the high-performance computing requirements of the computing unit.

[0175] In one possible implementation, the request detection unit is further configured to: obtain the value of the status data bit of the identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification; and when it is determined that the value of the status data bit is the target value, determine that the preset identification contained in the identification register is the target dynamic identification.

[0176] Here, the request detection unit can determine whether the identification register contains a preset identification through the status data bit of the identification register. The specific determination process is the same as the process described in step S1011 and step S1012 in the above embodiment, and will not be described one by one here.

[0177] In the embodiment of the present disclosure, it is possible to pre- Figure 5 The target dynamic identifier generation unit in the illustrated embodiment generates a target dynamic identifier from multiple preset identifiers and stores the target dynamic identifier in the identifier register. When the request detection unit determines that a preset identifier is included, it can determine that the preset identifier included in the identifier register is the target dynamic identifier.

[0178] In a possible implementation, when the data access request is a read request and the access identifier is a read identifier, the access identifier generation unit includes: a read identifier generation unit configured to determine the found target dynamic identifier as the read identifier of the data read request.

[0179] In the embodiment of the present disclosure, when the data access request sent by the requesting end is a read request, the access identifier generation unit can determine the target dynamic identifier in the found identifier register as the read identifier corresponding to the read request. The specific determination process is as described in the embodiment corresponding to the read request in step S103 above, and will not be described in detail here.

[0180] In one possible implementation, when the data memory access request is a write request and the memory access identifier is a write identifier, the memory access identifier generation unit includes: a write identifier generation unit, configured to determine the data write address corresponding to the write request in the response end when the target dynamic identifier is found; and determine the write identifier based on the numerical values ​​of multiple preset consecutive data bits in the data write address.

[0181] In the embodiment of the present disclosure, when it is detected that the data access request sent by the requesting end is a write request, the write identifier generation unit first detects whether the target dynamic identifier has been generated, and when it is detected that it has been generated, it determines that the target dynamic identifier can be found. At this time, the write identifier can be determined based on the data write address corresponding to the write request. The process of detecting whether the target dynamic identifier has been generated and the process of determining the write identifier can be as described in the embodiment corresponding to the write request in step S103 above, and will not be described in detail here.

[0182] In one possible implementation, when a data memory access request includes at least one write request corresponding to the same data write address, and the memory access identifier is a write identifier, the request execution unit is further configured to: obtain a target mapping linked list; the target mapping linked list is used to indicate a mapping relationship between the write identifier and a target dynamic identifier of each write request, and the mapping relationship is used to indicate an execution order of the at least one write request; and execute each write request at the response end based on the target mapping linked list to obtain a corresponding data memory access result.

[0183] Through the above steps, it can be known that when the request execution unit finds the target dynamic identifier, the request execution unit can determine the write identifier based on the data write address corresponding to the write request in the response end. At the same time, the target dynamic identifier to be allocated can be determined as the target dynamic identifier of the write request, and the target dynamic identifier of the write request can be saved in the target mapping linked list.

[0184] Here, the target mapping linked list can be as follows in the above embodiment: Figure 3 The linked list introduced will not be described in detail here. The process of executing each write request on the responding end based on the target mapping linked list is the same as the process described in the above steps S21 to S22, and will not be described in detail here.

[0185] In one possible implementation, the request execution unit is also configured to: obtain a first target dynamic identifier stored at a first address in a response end linked list of the target mapping linked list; the first address is an address determined based on the write identifier; determine a target write request that matches the first target dynamic identifier among multiple write requests, and execute the target write request to obtain a corresponding data access result.

[0186] Here, the first target dynamic identifier is used to indicate the target dynamic identifier of the first write request initiated by the requesting end for the data write address. At this time, the storage address of the first target dynamic identifier is the address determined based on the write identifier (ie, the first address mentioned above).

[0187] When the request execution unit executes each write request on the response end based on the target mapping linked list, first, the request execution unit obtains the first target dynamic identifier stored at the first address in the response end linked list of the target mapping linked list. After that, the request execution unit determines the target write request matching the first target dynamic identifier among multiple write requests, and executes the target write request on the response end, thereby obtaining the data access result corresponding to the target write request.

[0188] In one possible implementation, the request execution unit includes: a first linked list update unit, configured to: determine a second target dynamic identifier in the dynamic identifier linked list of the target mapping linked list; wherein the second target dynamic identifier is a target dynamic identifier stored in the dynamic identifier linked list with the first target dynamic identifier as the address; and update the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier.

[0189] Here, the target mapping linked list can be as follows in the above embodiment: Figure 3 The linked list introduced will not be described in detail here.

[0190] In the embodiment of the present disclosure, the process of the first linked list updating unit updating the first target dynamic identifier stored in the response end linked list to the second target dynamic identifier is as described in the embodiments corresponding to the above steps S41 and S42, and will not be described in detail here.

[0191] In one possible implementation, when a data memory access request includes at least one write request corresponding to the same data write address, the device further includes: a second linked list update unit, configured to update a target mapping linked list based on the write identifier of the write request and the target dynamic identifier to be allocated after determining the memory access identifier of the data memory access request based on the target dynamic identifier found; the target mapping linked list is used to indicate a mapping relationship between the write identifier and the target dynamic identifier of each write request, and the mapping relationship is used to indicate an execution order of at least one of the write requests.

[0192] In the embodiment of the present disclosure, when the data access request includes at least one write request corresponding to the same data write address, the second linked list updating unit may update the target mapping linked list based on the write identifier of the write request and the found target dynamic identifier to be allocated. The specific process of updating the target mapping linked list may be described as follows:

[0193] The second linked list update unit is also configured to: if the write request is not the first request to write data to the data write address, then write the target dynamic identifier to be allocated in the request end linked list of the target mapping linked list at the address represented by the write identifier; write the target dynamic identifier to be allocated in the dynamic identifier linked list of the target mapping linked list at the address represented by the first dynamic identifier; the first dynamic identifier is the target dynamic identifier of the previous write request of the current write request.

[0194] Here, the first request can also be understood as a write request for performing a write operation to a data write address for the first time, for example, write request 1 in the above embodiment. The specific update process of the second linked list update unit updating the target mapping linked list is as described in the above steps S51 to S52, which will not be described in detail here.

[0195] In one possible implementation, the memory access identifier generation unit is further configured to: after determining the memory access identifier of the data memory access request based on the target dynamic identifier found, store the target address information carried in the data memory access request in a storage location with the target dynamic identifier as the address in the local storage unit; wherein the target address information is used to indicate the storage location of the data memory access result in the requesting end.

[0196] In the embodiment of the present disclosure, the target address information is used to indicate the storage location of the data access result in the requesting end. For example, the target address information may be identification information of a register in the requesting end.

[0197] In an embodiment of the present disclosure, after determining the memory access identifier of the data memory access request based on the found target dynamic identifier, the memory access identifier generation unit can store the target address information carried in the data memory access request in the local storage unit using the target dynamic identifier as the storage address.

[0198] Afterwards, the request execution unit may execute the data memory access request at the response end based on the memory access identifier, obtain the data memory access result, and return the data memory access result to the request end based on the memory access identifier.

[0199] In one possible implementation, the request execution unit includes: an information recovery unit, configured to determine target address information in a local storage unit based on the memory access identifier; the target address information is used to indicate the storage location of the response result in the request end; and a response return unit, configured to return the data memory access result and the target address information to the request end.

[0200] In specific implementation, when the access identifier is a read identifier, the information recovery unit can determine the target dynamic identifier found based on the read identifier. At this time, the information recovery unit can determine the storage information in the storage location with the target dynamic identifier as the address in the local storage unit as the target address information.

[0201] After determining the target address information, the response returning unit may return the data access result and the corresponding target address information to the requesting end.

[0202] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0203] Corresponds to Figure 1 The data access method of the integrated circuit in the present disclosure also provides an electronic device 700, such as Figure 7 FIG. 7 is a schematic diagram of the structure of an electronic device 700 provided in an embodiment of the present disclosure, including:

[0204] Processor 71, memory 72, and bus 73; memory 72 is used to store execution instructions, including internal memory 721 and external memory 722; the internal memory 721 is also called internal memory, which is used to temporarily store the operation data in the processor 71 and the data exchanged with the external memory 722 such as a hard disk. The processor 71 exchanges data with the external memory 722 through the internal memory 721. When the electronic device 700 is running, the processor 71 communicates with the memory 72 through the bus 73, so that the processor 71 executes the following instructions:

[0205] Detecting a data access request sent by a requesting end, and detecting a target dynamic identifier to be allocated; the target dynamic identifier is dynamically generated based on an idle identifier among a plurality of preset identifiers;

[0206] Determine the memory access identifier of the data memory access request based on the found target dynamic identifier;

[0207] The data access request is executed at the responding end based on the access identifier to obtain a data access result, and the data access result is returned to the requesting end based on the access identifier. Or

[0208] An embodiment of the present disclosure further provides a chip, comprising the data access device of the integrated circuit as described in any of the above embodiments.

[0209] The electronic device provided by the embodiments of the present disclosure may also include the above chip.

[0210] The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the integrated circuit data access method described in the above method embodiment are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0211] The present disclosure also provides a computer program product that carries a program code. The program code includes instructions that can be used to execute the steps of the integrated circuit data access method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0212] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0213] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0214] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0215] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0216] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0217] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data access device for an integrated circuit, characterized in that: include: A request detection unit is configured to detect a data access request sent by a request end, and detect a target dynamic identifier to be allocated; The target dynamic identifier is dynamically generated based on idle identifiers among a plurality of preset identifiers; A memory access identifier generating unit, configured to determine a memory access identifier of the data memory access request based on the found target dynamic identifier; a request execution unit, configured to execute the data memory access request at the response end based on the memory access identifier, obtain a data memory access result, and return the data memory access result to the request end based on the memory access identifier; The request detection unit is further configured to: Obtaining a value of a status data bit of an identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification; In the case where it is determined that the value of the status data bit is the target value, determining the preset identifier contained in the identifier register as the target dynamic identifier; In the case where the data access request is a read request and the access identifier is a read identifier; the access identifier generation unit includes: a read identifier generation unit; The read identifier generating unit is configured to determine the found target dynamic identifier as the read identifier of the read request; In the case where the data access request is a write request and the access identifier is a write identifier; the access identifier generation unit further includes: a write identifier generation unit; The write identifier generation unit is configured to determine the data write address corresponding to the write request in the response end when the target dynamic identifier is found; and determine the write identifier based on the values ​​of multiple preset continuous data bits in the data write address.

2. The device according to claim 1, characterized in that In the case where the data memory access request includes at least one write request corresponding to the same data write address, and the memory access identifier is a write identifier; the request execution unit is configured to: Obtaining a target mapping linked list; the target mapping linked list is used to indicate a mapping relationship between the write identifier and a target dynamic identifier of each write request, and the mapping relationship is used to indicate an execution order of the at least one write request; Each write request is executed on the response end based on the target mapping linked list to obtain a corresponding data access result.

3. The device according to claim 2, characterized in that The request execution unit is further configured to: Obtaining a first target dynamic identifier stored at a first address in a response end linked list of the target mapping linked list; the first address is an address determined based on the write identifier; A target write request matching the first target dynamic identifier is determined from a plurality of write requests, and the target write request is executed to obtain a corresponding data access result.

4. The device according to claim 3, characterized in that The request execution unit includes: a first linked list updating unit; The first linked list updating unit is configured to determine a second target dynamic identifier in the dynamic identifier linked list of the target mapping linked list; wherein the second target dynamic identifier is a target dynamic identifier stored in the dynamic identifier linked list with the first target dynamic identifier as an address; and The first target dynamic identifier stored in the response end linked list is updated to the second target dynamic identifier.

5. The device according to claim 1, characterized in that In the case where the data access request includes at least one write request corresponding to the same data write address, the apparatus further comprises: a second linked list updating unit; The second linked list update unit is configured to update the target mapping linked list based on the write identifier of the write request and the target dynamic identifier to be allocated after determining the memory access identifier of the data memory access request based on the target dynamic identifier found; the target mapping linked list is used to indicate the mapping relationship between the write identifier and the target dynamic identifier of each write request, and the mapping relationship is used to indicate the execution order of at least one of the write requests.

6. The device according to claim 5, characterized in that The second linked list updating unit is further configured to: If the write request is not the first request to write data to the data write address, writing the target dynamic identifier to be allocated at the address represented by the write identifier in the request end linked list of the target mapping linked list; Write the target dynamic identifier to be allocated at the address represented by the first dynamic identifier in the dynamic identifier chain list of the target mapping chain list; The first dynamic identifier is a target dynamic identifier of a previous write request of the current write request.

7. The device according to claim 1, characterized in that The memory access identifier generation unit is further configured to: After determining the memory access identifier of the data memory access request based on the target dynamic identifier found, the target address information carried in the data memory access request is stored in a storage location in a local storage unit with the target dynamic identifier as the address; wherein the target address information is used to indicate the storage location of the data memory access result in the request end.

8. The device according to claim 7, characterized in that The request execution unit comprises: An information recovery unit, configured to determine target address information in a local storage unit based on the memory access identifier; the target address information is used to indicate a storage location of a response result in the requesting end; The response returning unit is configured to return the data access result and the target address information to the requesting end.

9. A data access system for an integrated circuit, characterized in that: include: The request side is used to generate and send data access requests; The processing end is used to detect the target dynamic identifier to be allocated after receiving the data access request sent by the requesting end, determine the access identifier of the data access request based on the found target dynamic identifier, and send the data access request carrying the access identifier to the responding end; wherein the target dynamic identifier is dynamically generated based on the idle identifier among multiple preset identifiers; A responding end, configured to execute the data memory access request based on the memory access identifier, obtain a data memory access result, and return the data memory access result to the requesting end through the processing end based on the memory access identifier; The step of detecting the target dynamic identifier to be allocated includes: Obtaining a value of a status data bit of an identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification; In the case where it is determined that the value of the status data bit is the target value, determining the preset identifier contained in the identifier register as the target dynamic identifier; In the case where the data access request is a read request and the access identifier is a read identifier; determining the access identifier of the data access request based on the found target dynamic identifier includes: determining the found target dynamic identifier as the read identifier of the read request; When the data memory access request is a write request and the memory access identifier is a write identifier; determining the memory access identifier of the data memory access request based on the target dynamic identifier found includes: when the target dynamic identifier is found, determining the data write address corresponding to the write request in the response end; and determining the write identifier based on the numerical values ​​of multiple preset consecutive data bits in the data write address.

10. A data access method for an integrated circuit, characterized in that: include: Detecting the data access request sent by the requesting end, and detecting the target dynamic identifier to be allocated; The target dynamic identifier is dynamically generated based on idle identifiers among a plurality of preset identifiers; Determine the memory access identifier of the data memory access request based on the found target dynamic identifier; Executing the data memory access request at the responding end based on the memory access identifier to obtain a data memory access result, and returning the data memory access result to the requesting end based on the memory access identifier; The step of detecting the target dynamic identifier to be allocated includes: Obtaining a value of a status data bit of an identification register; wherein the status data bit is used to indicate whether the identification register contains a preset identification; In the case where it is determined that the value of the status data bit is the target value, determining the preset identifier contained in the identifier register as the target dynamic identifier; In the case where the data access request is a read request and the access identifier is a read identifier; determining the access identifier of the data access request based on the found target dynamic identifier includes: determining the found target dynamic identifier as the read identifier of the read request; When the data memory access request is a write request and the memory access identifier is a write identifier; determining the memory access identifier of the data memory access request based on the target dynamic identifier found includes: when the target dynamic identifier is found, determining the data write address corresponding to the write request in the response end; and determining the write identifier based on the numerical values ​​of multiple preset consecutive data bits in the data write address.

11. A chip, characterized in that: A data access device comprising an integrated circuit as claimed in any one of claims 1 to 8.

12. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the data access method of the integrated circuit as claimed in claim 10 or the chip as claimed in claim 11 are performed.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data access method of the integrated circuit as claimed in claim 10 are executed.

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