A verification method and device of an integrated circuit, a computer device and a storage medium

Abstract

The present disclosure provides a verification method and device of an integrated circuit, wherein the method comprises: based on an automation script, performing the following steps: obtaining register transfer level (RTL) code of an integrated circuit to be tested and a configuration file; configuring a simulator based on configuration information in the configuration file, and generating a target verification environment in the simulator; in the target verification environment, simulating the integrated circuit to be tested based on the RTL code, and obtaining a simulation result of the integrated circuit to be tested; and obtaining a verification result of the integrated circuit to be tested based on the simulation result and a real result corresponding to the integrated circuit to be tested. The embodiments of the present disclosure automatically generate a target verification environment through an automation script, and implement verification of an integrated circuit by using the target verification environment, thereby improving verification efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular, to an integrated circuit verification method and device, a computer device, and a storage medium. BACKGROUND

[0002] The design steps of an integrated circuit usually include: generating a behavior level description, generating a register transfer level (RTL) description, converting the behavior level description or the RTL level description into a gate level netlist, and generating a physical layout (integrated circuit) based on the gate level netlist. Meanwhile, in the process of designing an integrated circuit, in order to ensure the performance of the generated integrated circuit, the integrated circuit usually needs to be verified after the RTL description is generated.

[0003] With the rapid development of the integrated circuit industry, the integrated circuit technology iterates rapidly, and at the same time, more and more verification acceleration requirements are brought to chip design. SUMMARY

[0004] The present disclosure provides at least an integrated circuit verification method and device, a computer device, and a storage medium.

[0005] In a first aspect, the present disclosure provides an integrated circuit verification method, which includes: obtaining a register transfer level (RTL) code of an integrated circuit to be tested and a configuration file; configuring a simulator based on configuration information in the configuration file, and generating a target verification environment in the simulator; in the target verification environment, simulating the integrated circuit to be tested based on the RTL code, and obtaining a simulation result of the integrated circuit to be tested; and obtaining a verification result of the integrated circuit to be tested based on the simulation result and a real result corresponding to the integrated circuit to be tested.

[0006] In this way, by obtaining the RTL code of the integrated circuit to be tested and the configuration file, the simulator is configured based on the configuration file, the target verification environment is generated in the simulator, the RTL code is executed based on the target verification environment, the simulation result of the integrated circuit to be tested is obtained, and then the verification result of the integrated circuit to be tested is obtained based on the simulation result and the real result corresponding to the integrated circuit to be tested, so that the target verification environment is automatically generated, and the verification of the integrated circuit is implemented by using the target verification environment, thereby improving the verification efficiency.

[0007] In an optional implementation, the configuration file includes at least one of the following: a register configuration file, an initialization data file, and an instruction file.

[0008] In an alternative implementation, the obtaining of the configuration file of the integrated circuit to be tested comprises: obtaining an original configuration file of the integrated circuit to be tested; and performing format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator.

[0009] In this way, after the original configuration file is obtained, the original configuration file is converted into a configuration file recognizable by an emulator, so that the configuration file can be used to automatically configure the emulator, and the efficiency of file conversion is improved.

[0010] In an alternative implementation, the configuration file comprises a register configuration file, and the configuration information comprises register values and register addresses; the format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator comprises: sequentially reading each register name in a plurality of register names from an original register configuration file; pairing, for each read register name, a register value corresponding to the register name with a register address corresponding to the register name to generate matching relationship information of the register value and the register address; and generating the register configuration file based on the matching relationship information corresponding to each of the plurality of registers.

[0011] In an alternative implementation, the configuration of the emulator based on the configuration information in the configuration file comprises: backdoor reading and writing of the register configuration file to a preset first storage space; reading, by a microcontroller, the matching relationship information from the first storage space; determining, as an address of a virtual register, a register address in the read matching relationship information, and storing the register value in a storage space corresponding to the virtual register.

[0012] In an alternative implementation, the configuration file comprises initialization data files respectively corresponding to a plurality of functional blocks in the integrated circuit to be tested, and the configuration information comprises excitation data of the corresponding functional blocks; the format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator comprises: performing segmentation on an original initialization data file according to the excitation data of the plurality of functional blocks in the integrated circuit to be tested and an interleaving order of the excitation data in the corresponding functional blocks to obtain the initialization data files respectively corresponding to the plurality of functional blocks.

[0013] In an alternative implementation, the configuring the emulator based on the configuration information in the configuration file comprises: backdoor reading and writing the initialization data files to the second storage spaces corresponding to the respective initialization data files respectively, and parsing the initialization data files to obtain the number of the initialization data files and the first address information of the second storage spaces corresponding to the respective initialization data files respectively; generating a first intermediate file based on the number of the initialization data files and the first address information of the second storage spaces corresponding to the respective initialization data files; and submitting the first intermediate file to the emulator; the first intermediate file is used by the emulator to read the stimulus data in the initialization data files when simulating the integrated circuit to be tested.

[0014] In an alternative implementation, the configuration file comprises instruction files corresponding to the respective functional blocks in the integrated circuit to be tested; the configuration information comprises instructions of the corresponding functional blocks; and the format conversion of the original configuration file to obtain the configuration file recognizable by the preset emulator comprises: cutting the original instruction files according to the instructions of the respective functional blocks in the integrated circuit to be tested and the interleaving order of the instructions in the corresponding functional blocks to obtain the instruction files corresponding to the respective functional blocks.

[0015] In an alternative implementation, the configuring the emulator based on the configuration information in the configuration file comprises: backdoor reading and writing the instruction files to the third storage spaces corresponding to the respective instruction files respectively, and parsing the instruction files to obtain the number of the instructions and the second address information of the third storage spaces corresponding to the respective instruction files respectively; generating a second intermediate file based on the number of the instruction files and the second address information of the third storage spaces corresponding to the respective instruction files; and submitting the second intermediate file to the emulator; the second intermediate file is used by the emulator to read the instructions in the instruction files when simulating the integrated circuit to be tested.

[0016] In a second aspect, the embodiments of the present disclosure further provide a verification device of an integrated circuit, comprising: an acquisition module, a configuration module, a simulation module, and a verification module;

[0017] The acquisition module is configured to: acquire register transfer level (RTL) code of an integrated circuit to be tested and a configuration file.

[0018] The configuration module is configured to: configure an emulator based on configuration information in the configuration file, and generate a target verification environment in the emulator.

[0019] The simulation module is configured to simulate the integrated circuit to be tested based on the RTL code in the target verification environment, and obtain a simulation result of the integrated circuit to be tested.

[0020] The verification module is configured to obtain a verification result of the integrated circuit to be tested based on the simulation result and a real result corresponding to the integrated circuit to be tested.

[0021] In a possible implementation, the configuration file includes at least one of a register configuration file, an initialization data file, and an instruction file.

[0022] In a possible implementation, when the obtaining module obtains the configuration file of the integrated circuit to be tested, the obtaining module is configured to:

[0023] obtain an original configuration file of the integrated circuit to be tested;

[0024] perform format conversion on the original configuration file to obtain the configuration file that can be recognized by the preset simulator.

[0025] In a possible implementation, the configuration file includes a register configuration file, and the configuration information includes register values of registers and register addresses.

[0026] When the obtaining module performs format conversion on the original configuration file to obtain the configuration file that can be recognized by the preset simulator, the obtaining module is configured to:

[0027] read each register name in a plurality of register names from the original register configuration file in sequence;

[0028] for each register name read, pair a register value corresponding to the register name with a register address corresponding to the register name to generate matching relationship information of the register value and the register address;

[0029] generate the register configuration file based on the matching relationship information corresponding to each of the plurality of registers.

[0030] In a possible implementation, when the configuration module configures the simulator based on the configuration information in the configuration file, the configuration module is configured to:

[0031] backdoor read and write of the register configuration file to a preset first storage space;

[0032] control the microcontroller to read the matching relationship information from the first storage space;

[0033] Determine the register address in the read matching relationship information as the address of the virtual register, and store the register value into the storage space corresponding to the virtual register.

[0034] In a possible implementation, the configuration file comprises initialization data files respectively corresponding to a plurality of functional blocks in the integrated circuit to be tested; and the configuration information comprises excitation data of the corresponding functional blocks.

[0035] The obtaining module, when performing format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator, is configured to:

[0036] According to the excitation data of a plurality of the functional blocks in the integrated circuit to be tested respectively and the interleaving order of the excitation data in the corresponding functional blocks, the original initialization data file is split to obtain initialization data files respectively corresponding to the plurality of the functional blocks.

[0037] In a possible implementation, the configuration module, when configuring the emulator based on the configuration information in the configuration file, is configured to:

[0038] read and write the initialization data files to the second storage spaces respectively corresponding to the initialization data files respectively, and

[0039] analyze the initialization data files to obtain the number of the initialization data files and the first address information of the second storage spaces respectively corresponding to the initialization data files respectively;

[0040] generate a first intermediate file based on the number of the initialization data files and the first address information of the second storage spaces respectively corresponding to the initialization data files respectively;

[0041] submit the first intermediate file to the emulator; the first intermediate file is used for the emulator to read the excitation data in the initialization data files when simulating the integrated circuit to be tested.

[0042] In a possible implementation, the configuration file comprises instruction files respectively corresponding to a plurality of functional blocks in the integrated circuit to be tested; and the configuration information comprises instructions of the corresponding functional blocks.

[0043] The obtaining module, when performing format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator, is configured to:

[0044] According to the instructions corresponding to the plurality of functional blocks in the integrated circuit to be tested respectively and the interleaving order of the instructions in the corresponding functional blocks, the original instruction file is split to obtain instruction files corresponding to the plurality of functional blocks respectively.

[0045] In a possible implementation, when the configuration module configures the emulator based on the configuration information in the configuration file, the configuration module is configured to:

[0046] read and write the instruction files to the third storage spaces corresponding to the instruction files respectively, and

[0047] analyze the instruction files to obtain the number of instructions and the second address information of the third storage spaces corresponding to the instruction files respectively;

[0048] generate a second intermediate file based on the number of instructions and the second address information of the third storage spaces corresponding to the instruction files respectively;

[0049] submit the second intermediate file to the emulator; the second intermediate file is used for the emulator to read the instructions in the instruction files when simulating the integrated circuit to be tested.

[0050] In a third aspect, an optional implementation of the present disclosure further provides a computer device, a processor and a memory, the memory stores machine readable instructions executable by the processor, and the processor is configured to execute the machine readable instructions stored in the memory, and the machine readable instructions are executed by the processor to execute the steps of the first aspect or any possible implementation of the first aspect.

[0051] In a fourth aspect, an optional implementation of the present disclosure further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed to execute the steps of the first aspect or any possible implementation of the first aspect.

[0052] The effects of the integrated circuit verification device, the computer device and the computer readable storage medium are described in the description of the integrated circuit verification method, and will not be repeated here.

[0053] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the following preferred embodiments are specifically described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. The drawings incorporated into the specification and form a part of the specification, which show the embodiments consistent with the present disclosure, and are used to explain the technical solutions of the present disclosure together with the specification. It should be understood that the following drawings only show some of the embodiments of the present disclosure, and therefore should not be regarded as a limitation on the scope, and other related drawings can also be obtained by those of ordinary skill in the art without creative labor.

[0055] Figure 1 A flow chart of a verification method of an integrated circuit provided by an embodiment of the present disclosure is shown;

[0056] Figure 2 A schematic diagram of a verification device of an integrated circuit provided by an embodiment of the present disclosure is shown;

[0057] Figure 3 A schematic diagram of a computer device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. The components of the embodiments of the present disclosure described and shown herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of the present disclosure.

[0059] It is found through research that the design and development of integrated circuits requires multi-link cooperation of multiple people, and the development environment required by different design and development links is also different. However, with the rapid development of the integrated circuit industry, it brings rapid iteration of integrated circuit technology, and at the same time, it also brings more and more verification acceleration needs for integrated circuit design. The current verification method using the universal verification methodology (UVM) cannot meet the increasing verification needs; in order to solve this problem, a special simulation accelerator (emulator) is currently used to realize accelerated verification of integrated circuits. However, when verifying integrated circuits, due to the difference in development environment, the verification personnel need to manually build a chip prototype verification system using a special simulation accelerator, and then use the chip prototype verification environment to verify the integrated circuit under test. The current way of manually building a chip prototype verification environment has the problem of low verification efficiency.

[0060] Based on the above research, the present disclosure provides a verification method for integrated circuits, which automatically generates a target verification environment and uses the target verification environment to verify integrated circuits, thereby improving verification efficiency.

[0061] The above-mentioned defects are the result of the inventors' careful research and practice, so the discovery process of the above-mentioned problems and the solutions proposed by the present disclosure to solve the above-mentioned problems should be the contribution of the inventors to the present disclosure.

[0062] It should be noted that similar reference numerals and letters refer to similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0063] In order to facilitate the understanding of the present embodiment, first, a verification method for integrated circuits disclosed by the present embodiment is introduced in detail, the execution subject of the verification method for integrated circuits provided by the present embodiment is generally a computer device with certain computing power, which includes, for example: terminal equipment or a server or other processing equipment, and the terminal equipment can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. In some possible implementation manners, the verification method for integrated circuits can be realized by a processor calling computer readable instructions stored in a memory.

[0064] The verification method for integrated circuits provided by the present embodiment is described below.

[0065] Referring to Figure 1 As shown in a flowchart of a verification method of an integrated circuit provided by an embodiment of the present disclosure, the method comprises steps S101-S104, wherein:

[0066] S101: Obtain register transfer level (RTL) code of an integrated circuit to be tested and a configuration file;

[0067] S102: Configure a simulator based on the configuration file and generate a target verification environment in the simulator;

[0068] S103: Execute the RTL code based on the target verification environment to obtain a simulation result of the integrated circuit to be tested;

[0069] S104: Obtain a verification result of the integrated circuit to be tested based on the simulation result and a real result corresponding to the integrated circuit to be tested.

[0070] Steps S101-S104 of the embodiment of the present disclosure can be executed based on an automatic script. After obtaining the RTL code of the integrated circuit to be tested and the configuration file, the simulator is configured based on the configuration file, the target verification environment is generated in the simulator, the RTL code is executed based on the target verification environment, the simulation result of the integrated circuit to be tested is obtained, and then the verification result of the integrated circuit to be tested is obtained based on the simulation result and the real result corresponding to the integrated circuit to be tested, so as to automatically generate the target verification environment and implement the verification of the integrated circuit by using the target verification environment, thereby improving the verification efficiency.

[0071] The above S101-S104 will be described in detail respectively.

[0072] For S101, the integrated circuit may, for example, comprise a chip; the chip may, for example, comprise an artificial intelligence (AI) chip. For the AI chip, it may, for example, comprise a graphic processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and the like.

[0073] The RTL code of the integrated circuit to be tested is generated by using the behavior level description of the integrated circuit. The behavior level is the description angle most consistent with the human logical thinking mode, and can be described by using a programming language such as C / C++. The RTL level description of the circuit refers to the data flow mode of the circuit described by using the register level description mode. The target of the behavior level description is to realize a specific function without the limitation of synthesis, and the target of the RTL level description is synthesis, that is, the conversion to a gate level circuit. When designing an integrated circuit, a designer first writes the corresponding code of the behavior level description according to the specific requirements of the integrated circuit by using a high-level programming language such as C / C++, and then converts the code of the behavior level description into RTL code. The conversion from the behavior level to the RTL level can be manually translated by the integrated circuit designer, or the behavior level can be converted to the RTL by using a synthesis tool such as the high-level synthesis tool Catapult C Synthesis of Menter Graphics.

[0074] In the verification link of the integrated circuit, the RTL code obtained in the RTL generation link can be directly read.

[0075] The configuration file is a related file required when simulating the integrated circuit to be tested by using the RTL code of the integrated circuit to be tested. In the verification link of the integrated circuit, the original configuration file of the integrated circuit to be tested can be obtained, and then the original configuration file is format-converted to obtain the configuration file that can be recognized by the preset simulator.

[0076] Specifically, when verifying the integrated circuit by using the simulator, there are mainly two verification modes:

[0077] One is to verify the integrated circuit to be tested in combination with the UVM verification side and the simulator verification side. The UVM is a verification platform development framework based on a System Verilog library, and a verification engineer can construct a functional verification environment with a standardized hierarchical structure and interface by using the reusable components.

[0078] In this verification process, the integrated circuit to be tested is first verified by using the UVM, and then simulated and verified by using the simulator. The verification content of the integrated circuit to be tested by using the UVM can be different from the verification content of the integrated circuit to be tested simulated and verified by using the simulator. For example, the code coverage of the integrated circuit to be tested is verified by using the UVM, and the functions of each functional block in the integrated circuit to be tested are verified by using the simulator.

[0079] Thus, the related files of the integrated circuit to be tested need to be converted from the UVM verification side to a format that can be used by the simulator. At this time, the original configuration file, for example, the configuration file used when verifying on the UVM verification side.

[0080] Secondly, the integrated circuit to be tested is verified by using the simulator. In this verification process, the related files of the integrated circuit to be tested need to be converted from the algorithm side to a format that can be used by the simulator. At this time, the original configuration file, for example, the configuration file used when generating the RTL.

[0081] The configuration file includes at least one of the following: a register configuration file, an initialization data file, and an instruction file. Among them:

[0082] A: For the register configuration file: the register configuration file includes the configuration information of the registers included in the integrated circuit to be tested. For example, in the integrated circuit to be tested, at least one register is included; the register configuration information includes at least one of the following, for example, but is not limited to: the name of the register, the offset address, the type, the read-write permission, the signal name of each type domain, the bit segment definition, the default value, the annotation, etc. The original configuration file includes: the original register configuration file.

[0083] In the embodiments of the present disclosure, the original register configuration file can be converted into a register configuration file that can be recognized by the preset simulator in the following manner:

[0084] The format conversion of the original configuration file to obtain the configuration file that can be recognized by the preset simulator includes:

[0085] From the original register configuration file, each register name in a plurality of register names is read in sequence;

[0086] For each register name read, the register value corresponding to the register name is paired with the register address corresponding to the register name to generate matching relationship information of the register value and the register address;

[0087] Based on the matching relationship information corresponding to each of the plurality of registers, the register configuration file is generated.

[0088] In a possible implementation, the register address is not included in the original register configuration file, and the register name and the register value are included; during the integrated circuit design process, a design document corresponding to the integrated circuit is maintained; in the design document, the register name and the register address of each register in the integrated circuit are included. After the register name is read from the original register configuration file, the corresponding register address can be read from the design document based on the register name, and then the register value read from the original register configuration file and the register address read from the design document are paired to generate matching relationship information of the register value and the register address, and then the matching relationship information is written into a file in a preset format to generate a register configuration file. Here, the preset format is, for example, a format that can be recognized by a simulator.

[0089] In another possible implementation, the register address, the register name, and the register value are included in the original register configuration file, each register address can be read in sequence, and the register name and the register value can be read from the original register configuration file based on the register address, and then the matching relationship information of the register value and the register address is generated, and then the matching relationship information is written into a file in a preset format to generate a register configuration file. Here, the preset format is, for example, a format that can be recognized by a simulator.

[0090] B: initialization data file: the initialization data file includes initialization data files corresponding to a plurality of functional blocks in the integrated circuit to be tested respectively; the initialization data file carries the excitation data of the corresponding functional block. The original configuration file includes: an original initialization data file.

[0091] The excitation data includes, for example, external input signals corresponding to each functional block of the integrated circuit to be tested. For some functional blocks, the external input signal can be a signal input externally to the integrated circuit. The integrated circuit is, for example, an artificial intelligence (AI) chip, and its function is to process images. The input signal externally to the integrated circuit is, for example, an enable signal of the AI chip. For another part of the functional blocks, the external input signal can be a signal generated by another functional block, or a signal that needs to be transmitted between functional blocks during use of the integrated circuit.

[0092] For example, in the verification of the integrated circuit, the initialization data needs to be stored in a specified address space in a double data rate synchronous dynamic random access memory (DDR), and the initialization data file obtained from the UVM verification side needs to be converted into a data format that can be used by a simulator and stored in a file. In the simulation stage, the initialization data is read and written into the predetermined DDR address space through a simulator-specific instruction backdoor.

[0093] In the embodiments of the present disclosure, the original initialization data file can be converted into an initialization data file recognizable by the preset emulator in the following manner:

[0094] The original initialization data file is divided according to the excitation data corresponding to each of the functional blocks in the integrated circuit to be tested and the interleaving order of the excitation data in the corresponding functional block, to obtain initialization data files corresponding to the plurality of functional blocks respectively.

[0095] For each functional block, the interleaving order of the excitation data in the corresponding functional block refers to at least one of the mutual conversion logic, transmission logic, processing order, etc. between different excitation data.

[0096] When dividing the original initialization data file, the excitation data corresponding to the plurality of functional blocks is stored in the same original initialization data file. When dividing the original initialization data file, for example, each excitation data in the original initialization data file can be read in sequence. After each excitation data is read, the functional block corresponding to the read excitation data is determined. Then, according to the interleaving order of the read excitation data in the corresponding functional block, the storage position of the excitation data in the initialization data file of the corresponding functional block is determined, and the excitation data is stored in the initialization data file of the corresponding functional block according to the storage position. When all excitation data in the original initialization data file is read and stored in the corresponding storage position, the initialization data files corresponding to the plurality of functional blocks are obtained.

[0097] C: The configuration file includes instruction files corresponding to the plurality of functional blocks in the integrated circuit to be tested respectively, and the instruction files carry instructions of the corresponding functional blocks. The original configuration file includes an original instruction file.

[0098] The instructions include instructions corresponding to each functional block of the integrated circuit to be tested. For some functional blocks, the corresponding instructions can be instructions input from outside the integrated circuit. The integrated circuit is, for example, an artificial intelligence (AI) chip, and its function is to process images. The instructions input from outside the integrated circuit are, for example, task processing instructions. For another part of the functional blocks, the external input signals can be instructions generated by other functional blocks, or instructions that need to be transmitted between functional blocks during use of the integrated circuit.

[0099] The instructions are usually read in a similar way and the excitation data is read in a multi-channel manner at the same time, so the instructions stored in different spaces in the predetermined address segment also need to be interleaved, and the automatic verification process provided in the embodiments of the present disclosure also needs to cut the original instruction file into several parts through a script file and meet the instruction interleaving order of the original design.

[0100] In the embodiments of the present disclosure, the original instruction file can be converted into an instruction file recognizable by the preset emulator in the following manner:

[0101] According to the instructions corresponding to the plurality of functional blocks in the integrated circuit to be tested respectively and the interleaving order of the instructions in the corresponding functional blocks, the original instruction file is cut to obtain instruction files corresponding to the plurality of functional blocks respectively.

[0102] For each functional block, the interleaving order of the instructions in the corresponding functional block refers to at least one of the mutual conversion logic, transmission logic, processing order, etc. between different instructions.

[0103] When cutting the original instruction file, the instructions corresponding to the plurality of functional blocks are stored in the same original instruction file. When cutting the original instruction file, for example, each instruction in the original instruction file can be read in sequence. After each instruction is read, the functional block corresponding to each instruction read is determined. Then, according to the interleaving order of each instruction read in the corresponding functional block, the storage position of the instruction in the instruction file of the corresponding functional block is determined, and the instruction is stored in the instruction file of the corresponding functional block according to the storage position. When all instructions in the original instruction file are read and stored in the corresponding storage position, the instruction files corresponding to the plurality of functional blocks are obtained.

[0104] For S102, after obtaining the configuration file, the emulator can be configured using the configuration file to generate a target verification environment in the emulator.

[0105] D: In the case where the configuration file includes a register configuration file and the configuration information includes a register value and a register address, the emulator can be configured in the following manner:

[0106] The register configuration file is backdoored to a preset first storage space;

[0107] The microcontroller reads the matching relationship information from the first storage space;

[0108] The register address in the read matching relationship information is determined as the address of a virtual register, and the register value is stored in the storage space corresponding to the virtual register.

[0109] In a specific implementation, the simulation process may, for example, be implemented by relying on a simulator; the simulator includes a microcontroller that is capable of implementing the specific simulation process based on the register configuration information, the stimulus data, and the instructions. The microcontroller of the simulator may, for example, include any one of a Field Programmable Gate Array (FPGA) or a Central Processing Unit (CPU) array.

[0110] In the simulation process, since the register configuration information is information that needs to be directly accessed by the microcontroller of the simulator, and the microcontroller cannot directly read the register configuration file, when the microcontroller is controlled to read the matching relationship information from the first storage space, the microcontroller firmware in the microcontroller can be called by using an automated script, and the register address and the register value can be read from the register configuration file in the first storage space by using the microcontroller firmware in a loop reading manner, and the register address in the read matching relationship information is determined as the address of the virtual register, and the register value is stored in the storage space corresponding to the virtual register.

[0111] For example, the size of the register address and the register value does not exceed 32 bits, so the information of one register configuration can be represented by 64 bits of data obtained by splicing two 32 bits together, and after the register configuration file is backdoor read and written to the first storage space by using the automated script, the microcontroller is controlled to read the corresponding configuration information, the first 32 bits represent the register address, and the last 32 bits represent the register value, and the registers to be configured are configured in the preset register address segment one by one by using the loop reading manner in the microcontroller firmware file, so as to realize the automation of the register configuration.

[0112] E: The configuration file includes initialization data files corresponding to a plurality of functional blocks in the integrated circuit to be tested respectively, and the configuration information includes the stimulus data of the corresponding functional blocks. In this case, the simulator can be configured in the following manner:

[0113] The initialization data files are respectively backdoor read and written to the second storage spaces corresponding to the respective initialization data files, and

[0114] The initialization data files are parsed to obtain the number of initialization data files and the first address information of the second storage spaces corresponding to the respective initialization data files.

[0115] generating a first intermediate file based on the number of initialization data files and the first address information of the second storage space corresponding to each initialization data file;

[0116] submitting the first intermediate file to the emulator; the first intermediate file is used by the emulator to read the stimulus data in each initialization data file when simulating the integrated circuit to be tested.

[0117] Through the above process, the initialization data files are first read and written to the corresponding second storage space respectively, and the first intermediate file is generated, and then the first intermediate file is delivered to the emulator, and the configuration of the stimulus data required by the emulator when performing simulation is completed. When simulating the integrated circuit to be tested, the emulator can use the tcl command to parse the first intermediate file, extract the number of initialization data files and the first address information corresponding to each initialization data file from the first intermediate file, and provide the emulator in the form of a variable; the emulator reads the stimulus data from the corresponding second storage space through the number of initialization data files and the first address information corresponding to each initialization data file, and completes the simulation process of the integrated circuit to be tested by using the stimulus data.

[0118] F: The configuration file includes instruction files corresponding to a plurality of functional blocks in the integrated circuit to be tested respectively, and the configuration information includes instructions of the corresponding functional blocks. The emulator can be configured in the following manner:

[0119] reading and writing the instruction files to the third storage space corresponding to each instruction file respectively, and

[0120] parsing the instruction files to obtain the number of instructions and the second address information of the third storage space corresponding to each instruction file respectively;

[0121] generating a second intermediate file based on the number of instruction files and the second address information of the third storage space corresponding to each instruction file;

[0122] submitting the second intermediate file to the emulator; the second intermediate file is used by the emulator to read the instructions in each instruction file when simulating the integrated circuit to be tested.

[0123] Here, the instruction files are read and written to the corresponding third storage space respectively, and a second intermediate file is generated, and then the second intermediate file is delivered to the simulator, and the configuration of the instructions required by the simulator in the simulation is completed. When the simulator simulates the integrated circuit to be tested, the number of instruction files and the second address information corresponding to each instruction file in the second intermediate file can be extracted from the second intermediate file by using the tcl command, and the extracted information is provided to the simulator in the form of a variable; the simulator reads the instructions from the corresponding third storage space according to the number of instruction files and the second address information corresponding to each instruction file, and uses the instructions to complete the simulation process of the integrated circuit to be tested.

[0124] For S103 and S104 described above: after generating the target verification environment in the simulator, the RTL code can be executed in the target verification environment to simulate the integrated circuit to be tested, and the simulation result of the integrated circuit to be tested is obtained.

[0125] After the simulation is completed, the simulator can read the output simulation result from the specified address space of the specified DDR, and download the simulation result into a file by using the simulator-specific command. Then, the file needs to be converted into the data format of the final result file in the integrated circuit to be tested, so as to facilitate the comparison with the real result corresponding to the integrated circuit to be tested.

[0126] Those skilled in the art can understand that in the above method of the specific embodiment, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process, and the specific execution order of each step should be determined according to its function and possible internal logic.

[0127] Based on the same inventive concept, the disclosure embodiments also provide a verification device for an integrated circuit corresponding to the verification method of the integrated circuit. Since the principle of solving problems in the device of the disclosure embodiments is similar to the above-mentioned verification method of the integrated circuit of the disclosure embodiments, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0128] Reference Figure 2 As shown in FIG. 1, a schematic diagram of a verification device for an integrated circuit provided by the disclosure embodiments is shown, and the device comprises an acquisition module 21, a configuration module 22, a simulation module 23, and a verification module 24.

[0129] The acquisition module 21 is configured to acquire the register transfer level (RTL) code of the integrated circuit to be tested and a configuration file.

[0130] The configuration module 22 is configured to configure the simulator based on the configuration information in the configuration file, and generate a target verification environment in the simulator.

[0131] The simulation module 23 is configured to simulate the integrated circuit to be tested based on the RTL code in the target verification environment, and obtain a simulation result of the integrated circuit to be tested.

[0132] The verification module 24 is configured to obtain a verification result of the integrated circuit to be tested based on the simulation result and a real result corresponding to the integrated circuit to be tested.

[0133] In a possible implementation, the configuration file includes at least one of a register configuration file, an initialization data file, and an instruction file.

[0134] In a possible implementation, when the obtaining module 21 obtains the configuration file of the integrated circuit to be tested, the obtaining module 21 is configured to:

[0135] obtain an original configuration file of the integrated circuit to be tested;

[0136] perform format conversion on the original configuration file, and obtain the configuration file that can be recognized by the preset simulator.

[0137] In a possible implementation, the configuration file includes a register configuration file, and the configuration information includes register values of registers and register addresses.

[0138] When the obtaining module 21 performs format conversion on the original configuration file, and obtains the configuration file that can be recognized by the preset simulator, the obtaining module 21 is configured to:

[0139] read each register name in a plurality of register names from an original register configuration file in sequence;

[0140] for each register name read, pair a register value corresponding to the register name with a register address corresponding to the register name, and generate matching relationship information of the register value and the register address;

[0141] generate the register configuration file based on the matching relationship information corresponding to each of the plurality of registers.

[0142] In a possible implementation, when the configuration module 22 configures the simulator based on the configuration information in the configuration file, the configuration module 22 is configured to:

[0143] backdoor read and write of the register configuration file to a preset first storage space;

[0144] control the microcontroller to read the matching relationship information from the first storage space;

[0145] Determine the register address in the read matching relationship information as the address of the virtual register, and store the register value into the storage space corresponding to the virtual register.

[0146] In a possible implementation, the configuration file comprises initialization data files respectively corresponding to a plurality of functional blocks in the integrated circuit to be tested; and the configuration information comprises excitation data of the corresponding functional blocks.

[0147] The obtaining module 21, when performing format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator, is configured to:

[0148] According to the excitation data of a plurality of the functional blocks in the integrated circuit to be tested respectively and the interleaving order of the excitation data in the corresponding functional blocks, the original initialization data file is split to obtain initialization data files respectively corresponding to the plurality of the functional blocks.

[0149] In a possible implementation, the configuration module 22, when configuring the emulator based on the configuration information in the configuration file, is configured to:

[0150] read and write the initialization data files to the second storage spaces respectively corresponding to the initialization data files respectively, and

[0151] analyze the initialization data files to obtain the number of the initialization data files and the first address information of the second storage spaces respectively corresponding to the initialization data files respectively;

[0152] generate a first intermediate file based on the number of the initialization data files and the first address information of the second storage spaces respectively corresponding to the initialization data files respectively;

[0153] submit the first intermediate file to the emulator; the first intermediate file is used for the emulator to read the excitation data in the initialization data files when simulating the integrated circuit to be tested.

[0154] In a possible implementation, the configuration file comprises instruction files respectively corresponding to a plurality of functional blocks in the integrated circuit to be tested; and the configuration information comprises instructions of the corresponding functional blocks.

[0155] The obtaining module 21, when performing format conversion on the original configuration file to obtain the configuration file recognizable by the preset emulator, is configured to:

[0156] According to the instructions corresponding to the plurality of functional blocks in the integrated circuit to be tested respectively and the interleaving order of the instructions in the corresponding functional blocks, the original instruction file is split to obtain instruction files corresponding to the plurality of functional blocks respectively.

[0157] In a possible implementation, the configuration module 22 is configured to, when configuring the emulator based on the configuration information in the configuration file:

[0158] read and write the instruction files to the third storage spaces corresponding to the respective instruction files respectively, and

[0159] analyze the instruction files to obtain the number of instructions and the second address information of the third storage spaces corresponding to the respective instruction files respectively;

[0160] generate a second intermediate file based on the number of instruction files and the second address information of the third storage spaces corresponding to the respective instruction files respectively;

[0161] submit the second intermediate file to the emulator; the second intermediate file is used for the emulator to read the instructions in the respective instruction files when simulating the integrated circuit to be tested.

[0162] The description of the processing flow of each module in the apparatus and the interaction flow between the modules can refer to the related description in the above method embodiments, and will not be described in detail here.

[0163] The embodiments of the present disclosure further provide a computer device, as shown in the accompanying drawings, which includes: Figure 3 The computer device provided by the embodiments of the present disclosure includes:

[0164] a processor 31 and a memory 32; the memory 32 stores machine readable instructions executable by the processor 31, and the processor 31 is configured to execute the machine readable instructions stored in the memory 32, and when the machine readable instructions are executed by the processor 31, the processor 31 performs the following steps:

[0165] obtain register transfer level (RTL) code of an integrated circuit to be tested and a configuration file;

[0166] configure an emulator based on the configuration information in the configuration file, and generate a target verification environment in the emulator;

[0167] in the target verification environment, simulate the integrated circuit to be tested based on the RTL code to obtain a simulation result of the integrated circuit to be tested;

[0168] Based on the simulation result and a real result corresponding to the integrated circuit to be tested, a verification result of the integrated circuit to be tested is obtained.

[0169] The memory 32 includes an internal memory 321 and an external memory 322. The internal memory 321 is also referred to as an internal storage, and is used to temporarily store operation data in the processor 31 and exchange data with the external memory 322 such as a hard disk. The processor 31 exchanges data with the external memory 322 through the internal memory 321.

[0170] The specific execution process of the instructions can refer to the steps of the integrated circuit verification method described in the embodiments of the present disclosure, which will not be described here.

[0171] The embodiments of the present disclosure also provide a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the integrated circuit verification method described in the method embodiments are executed. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0172] The embodiments of the present disclosure also provide a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the integrated circuit verification method described in the method embodiments. For details, refer to the method embodiments, which will not be described here.

[0173] The computer program product can be specifically implemented by hardware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0174] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiments, which will not be described here. In several embodiments provided by the present disclosure, it should be understood that the disclosed system, device and method can be implemented by other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, and can be electrical, mechanical or other forms.

[0175] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0176] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0177] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present disclosure or the part of the prior art that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, and various program code storage media.

[0178] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present disclosure, used to illustrate the technical solutions of the present disclosure, and not to limit them, the protection scope of the present disclosure is not limited thereto, although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: any skilled person in the art within the technical range disclosed by the present disclosure, they can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and all should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of verifying an integrated circuit, characterized by, The method comprises the following steps: obtaining register level conversion circuit (RTL) code of a to-be-tested integrated circuit and an original configuration file of the to-be-tested integrated circuit; format-converting the original configuration file to obtain a configuration file recognizable by a simulator; configuring the simulator based on configuration information in the configuration file, and generating a target verification environment in the simulator; in the target verification environment, simulating the to-be-tested integrated circuit based on the RTL code to obtain a simulation result of the to-be-tested integrated circuit; obtaining a verification result of the to-be-tested integrated circuit based on the simulation result and a real result corresponding to the to-be-tested integrated circuit; the configuration file comprises initialization data files corresponding to a plurality of functional blocks in the to-be-tested integrated circuit respectively; the configuration information comprises excitation data of the corresponding functional blocks; and the format-converting the original configuration file to obtain a configuration file recognizable by a simulator comprises: segmenting original initialization data files based on excitation data of a plurality of the functional blocks in the to-be-tested integrated circuit respectively and interleaving orders of the excitation data in the corresponding functional blocks to obtain initialization data files corresponding to the plurality of the functional blocks respectively; the interleaving orders of the excitation data in the corresponding functional blocks refer to at least one of mutual conversion logic, transmission logic and processing order between different excitation data.

2. The method of claim 1, wherein, the configuration file comprises a register configuration file; and the configuration information comprises register values of registers and register addresses; the format-converting the original configuration file to obtain the configuration file recognizable by the simulator comprises: reading each register name in a plurality of register names from an original register configuration file in sequence; for each read register name, pairing a register value corresponding to the register name with a register address corresponding to the register name to generate matching relationship information of the register value and the register address; generating the register configuration file based on matching relationship information corresponding to a plurality of the registers respectively.

3. The method of claim 2, wherein, the configuring the simulator based on the configuration information in the configuration file comprises: backdoor reading and writing the register configuration file to a preset first storage space; controlling a microcontroller to read the matching relationship information from the first storage space; determining a register address in the read matching relationship information as an address of a virtual register, and storing the register value in a storage space corresponding to the virtual register.

4. The method of claim 1, wherein, the configuring the simulator based on the configuration information in the configuration file comprises: backdoor reading and writing the initialization data files to second storage spaces corresponding to the initialization data files respectively, and analyzing the initialization data files to obtain a number of the initialization data files and first address information of the second storage spaces corresponding to the initialization data files respectively; generating a first intermediate file based on the number of the initialization data files and the first address information of the second storage spaces corresponding to the initialization data files respectively; and submit the first intermediate file to the emulator; the first intermediate file is used for the emulator to read the stimulus data in each of the initialization data files when simulating the integrated circuit to be tested.

5. The method according to any one of claims 1 to 4, characterized in that, The configuration file includes instruction files corresponding to a plurality of functional blocks in the integrated circuit to be tested respectively; the configuration information includes instructions of the corresponding functional blocks. The format conversion of the original configuration file to obtain the configuration file recognizable by the emulator includes: According to the instructions corresponding to a plurality of the functional blocks in the integrated circuit to be tested respectively and the interleaving order of the instructions in the corresponding functional blocks, the original instruction file is divided to obtain instruction files corresponding to a plurality of the functional blocks respectively.

6. The method of claim 5, wherein, The configuration of the emulator based on the configuration information in the configuration file includes: The instruction files are read and written to the third storage space corresponding to each instruction file respectively, and The number of instructions and the second address information of the third storage space corresponding to each instruction file are obtained by analyzing the instruction files; A second intermediate file is generated based on the number of instruction files and the second address information of the third storage space corresponding to each instruction file. The second intermediate file is submitted to the emulator; the second intermediate file is used for the emulator to read the instructions in each of the instruction files when simulating the integrated circuit to be tested.

7. An integrated circuit verification apparatus, characterized by comprising: It includes: An acquisition module, a configuration module, an emulation module, and a verification module; The acquisition module is configured to acquire register transfer level (RTL) code of an integrated circuit to be tested and an original configuration file of the integrated circuit to be tested. The original configuration file is format-converted to obtain a configuration file recognizable by an emulator. The configuration module is configured to configure the emulator based on configuration information in the configuration file, and generate a target verification environment in the emulator. The emulation module is configured to simulate the integrated circuit to be tested based on the RTL code in the target verification environment, and obtain a simulation result of the integrated circuit to be tested. The verification module is configured to obtain a verification result of the integrated circuit to be tested based on the simulation result and an actual result corresponding to the integrated circuit to be tested. The configuration file includes initialization data files corresponding to a plurality of functional blocks in the integrated circuit to be tested respectively; the configuration information includes stimulus data of the corresponding functional blocks; and the acquisition module is specifically configured to: According to the stimulus data corresponding to a plurality of the functional blocks in the integrated circuit to be tested respectively and the interleaving order of the stimulus data in the corresponding functional blocks, the original initialization data file is divided to obtain initialization data files corresponding to a plurality of the functional blocks respectively; the interleaving order of the stimulus data in the corresponding functional blocks refers to at least one of mutual conversion logic, transmission logic, and processing order between different stimulus data.

8. A computer device, comprising: It includes: A processor, a memory, the memory storing machine readable instructions executable by the processor, the processor being configured to execute the machine readable instructions stored in the memory, the machine readable instructions, when executed by the processor, causing the processor to perform the steps of the method for verifying an integrated circuit according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, A computer program is stored in the computer readable storage medium, and when the computer program is run by a computer device, the computer device performs the steps of the method for verifying an integrated circuit according to any one of claims 1 to 6.

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