Integrated Chip and Its Preparation Method

Abstract

The present invention discloses an integrated chip and a preparation method thereof. The integrated chip includes a substrate, a piezoelectric layer, a surface acoustic wave resonator, and a resonant circuit unit. The piezoelectric layer is formed on one side of the substrate layer. An isolation groove is formed on the piezoelectric layer to separate the piezoelectric layer into a first part and a second part that are arranged side by side at intervals. The surface acoustic wave resonator is formed on the piezoelectric layer and corresponds to the first part. The resonant circuit unit is formed on the piezoelectric layer and corresponds to the second part. Wherein, the electrical signal input end of the surface acoustic wave resonator is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator is electrically connected to the resonant circuit unit. By integrating the surface acoustic wave resonator and the resonant circuit unit on the same chip, the bandwidth of the filter can be improved, and at the same time, the device integration degree can be increased, the power consumption can be reduced, the chip area can be decreased, and the manufacturing cost can be lowered.

Description

Technical Field

[0001] The present invention relates to the technical field of communication devices, and in particular to an integrated chip and a preparation method thereof. Background Art

[0002] The 5G communication drives the high-speed development of the radio frequency front-end market. Compared with 4G, various devices in the radio frequency front-end of 5G mobile phones will increase significantly. The deployment of 5G networks is divided into two stages. The first stage is Sub-6GHz, and the second stage is the millimeter wave band. Specifically, in the first stage, four new frequency bands are added, namely n41 (frequency range 2.496 - 2.69 GHz, bandwidth 196 MHz), n77 (frequency range 3.3 - 4.2 GHz, bandwidth 900 MHz), n78 (frequency range 3.3 - 3.8 GHz, bandwidth 500 MHz), and n79 (frequency range 4.4 - 5.0 GHz, bandwidth 600 MHz). The frequencies used in 5G and future communications will be higher and higher to meet the demand for larger bandwidth in mobile communications.

[0003] In communications before 4G and including 4G, the radio frequency filters mainly include SAW filters, that is, surface acoustic wave filters (Surface Acoustic Wave). For existing ordinary surface acoustic wave filters, the applicable frequency bands are relatively low; the manufacturing process of surface acoustic wave filters that can be applied to high frequency bands is complex and the cost is high. Summary of the Invention

[0004] In order to meet the bandwidth requirements of 5G and future communications, existing filters usually mount discrete inductors, capacitors, and resistor components together in the packaging stage to form a matching circuit to increase the bandwidth. As a result, the device area is large, the circuit loss is large, and the manufacturing cost is high.

[0005] The main object of the present invention is to propose an integrated chip and a preparation method thereof, aiming to solve the problems of complex manufacturing process and high cost of existing surface acoustic wave filters applicable to high frequency bands.

[0006] To achieve the above object, the present invention proposes an integrated chip, including:

[0007] A substrate;

[0008] A piezoelectric layer formed on one side of the substrate layer. An isolation groove is formed on the piezoelectric layer to divide the piezoelectric layer into a first part and a second part arranged side by side at intervals;

[0009] A surface acoustic wave resonator formed on the piezoelectric layer and corresponding to the first part; and,

[0010] A resonant circuit unit formed on the piezoelectric layer and corresponding to the second part;

[0011] Among them, the electrical signal input end of the surface acoustic wave resonator is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator is electrically connected to the resonant circuit unit.

[0012] Optionally, the surface acoustic wave resonator includes:

[0013] Interdigital transducers are provided on the piezoelectric layer and include an input transducer and an output transducer arranged side by side. The input transducer is used to convert the input electrical signal into an acoustic wave for output, and the output transducer is used to receive the acoustic wave output by the input transducer and convert it into an electrical signal for output; and,

[0014] Two reflectors are respectively arranged on two sides of the input transducer and the output transducer facing away from each other;

[0015] Among them, the electrical signal input end of the surface acoustic wave resonator includes the input end of the input transducer, and the electrical signal output end of the surface acoustic wave resonator includes the output end of the output transducer.

[0016] Optionally, the resonant circuit unit includes:

[0017] A first dielectric layer is formed on the end face of the piezoelectric layer facing away from the substrate layer; and,

[0018] A component group is formed on the first dielectric layer. The component group includes an inductor, a capacitor, and a resistor that are arranged side by side at intervals and are electrically connected to each other;

[0019] Among them, the electrical signal output end of the surface acoustic wave resonator is electrically connected to one of the inductor, the capacitor, or the inductor.

[0020] Optionally, the resonant circuit unit includes:

[0021] A second dielectric layer is formed on the side of the piezoelectric layer facing away from the substrate layer; and,

[0022] A component layer group includes an inductor layer, a capacitor layer, and a resistor layer that are sequentially stacked. The inductor layer, the capacitor layer, and the resistor layer are electrically connected to each other;

[0023] Among them, the electrical signal output end of the surface acoustic wave resonator is electrically connected to one of the inductor layer, the capacitor layer, or the resistor layer.

[0024] Optionally, an interconnection structure is provided between the resonant circuit unit and the surface acoustic wave resonator to electrically connect the surface acoustic wave resonator to the resonant circuit unit.

[0025] Optionally, the piezoelectric layer is set as an aluminum nitride thin film.

[0026] Based on the above integrated chip, the present invention further provides a method for manufacturing an integrated chip, including:

[0027] Providing a substrate layer;

[0028] Forming a piezoelectric layer on the substrate layer;

[0029] Fabricating isolation grooves in the piezoelectric layer to divide the piezoelectric layer into a first part and a second part arranged side by side;

[0030] Forming a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part;

[0031] Forming a resonant circuit unit on the piezoelectric layer corresponding to the second part;

[0032] Fabricating an interconnection structure to electrically connect at least the surface acoustic wave resonator to the resonant circuit unit.

[0033] Optionally, the step of "forming a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part" includes:

[0034] Forming an input transducer and an output transducer arranged side by side on a side of the piezoelectric layer facing away from the substrate layer, wherein, in a direction from the first part to the second part, the input transducer and the output transducer are spaced apart;

[0035] Forming two reflectors on two sides of the input transducer and the output transducer facing away from each other;

[0036] Forming a first passivation layer on an end face of the piezoelectric layer facing away from the substrate layer, wherein the first passivation layer covers the input transducer, the output transducer, and the two reflectors.

[0037] Optionally, the step of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes:

[0038] Forming a first dielectric layer on the piezoelectric layer;

[0039] Forming an intermetallic dielectric layer on the first dielectric layer;

[0040] Forming an inductive metal wire, a capacitive metal wire, and a resistive metal wire on the intermetallic dielectric layer respectively to form an inductor, a capacitor, and a resistor respectively;

[0041] In the step of "fabricating an interconnection structure": the interconnection structure is also disposed between the inductor, the capacitor, and the resistor.

[0042] Optionally, the step of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes:

[0043] Forming a second dielectric layer on the piezoelectric layer;

[0044] Forming a first intermetal dielectric layer on the second dielectric layer;

[0045] Forming an inductive metal wire in the first intermetal dielectric layer to form an inductor;

[0046] Forming a capacitive dielectric layer on the first intermetal dielectric layer;

[0047] Forming a second intermetal dielectric layer on the capacitive dielectric layer;

[0048] Forming a capacitive metal wire in the second intermetal dielectric layer to form a capacitor;

[0049] A third metal dielectric layer is formed on the second intermetal dielectric layer;

[0050] Forming a resistive metal wire on the third metal dielectric layer to form a resistor;

[0051] Forming a passivation layer on the third metal dielectric layer to cover the resistor;

[0052] In the step of "fabricating the interconnect structure": the interconnect structure is also disposed between the inductor, the capacitor, and the resistor.

[0053] In the technical solution of the present invention, a substrate is provided, a piezoelectric layer is formed on the substrate, and by providing the isolation groove, the piezoelectric layer is separated into a first part and a second part which are arranged side by side at intervals; the surface acoustic wave resonator is arranged corresponding to the first part; the resonant circuit unit is arranged corresponding to the second part; wherein, the electrical signal input end of the surface acoustic wave resonator is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator is electrically connected to the resonant circuit unit; that is, by integrating the resonant circuit unit and the surface acoustic wave resonator on the same chip, the integration degree of the device is improved, the communication bandwidth is increased, the system efficiency is improved, and at the same time, the chip area is reduced and the cost is lowered. Description of the Drawings

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0055] Figure 1 Structural schematic diagram of the first embodiment of the integrated chip provided by the present invention;

[0056] Figure 2 Structural schematic diagram of the second embodiment of the integrated chip provided by the present invention;

[0057] Figure 3 Flowchart of an embodiment of the preparation method of the integrated chip provided by the present invention;

[0058] Figure 4 For Figure 3 Flowchart of an embodiment of step S40 in

[0059] Figure 5 For Figure 3 Flowchart of the first embodiment of step S50 in

[0060] Figure 6 For Figure 3 Flowchart of the second embodiment of step S50 in

[0061] Description of the reference numerals in the embodiments provided by the present invention:

[0062]

[0063]

[0064] The realization of the object, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0066] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0067] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text includes three parallel scenarios. Taking "A and / or B" as an example, it includes Scenario A, or Scenario B, or the scenario where both A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0068] In communications before 4G and including 4G, the radio frequency filters mainly include SAW filters, namely Surface Acoustic Wave filters. However, for existing ordinary surface acoustic wave filters, the applicable frequency bands are relatively low; the manufacturing process of surface acoustic wave filters that can be applied to high frequency bands is complex and the cost is relatively high.

[0069] In view of this, the present invention provides an integrated chip and a preparation method thereof. Figures 1 to 2 This is a specific embodiment of the integrated chip provided by the present invention; Figures 3 to 6 This is a specific embodiment of the preparation method of the integrated chip provided by the present invention.

[0070] Please refer to Figures 1 to 2 , the integrated chip 100 includes a substrate 1, a piezoelectric layer 2, a surface acoustic wave resonator 3, and a resonant circuit unit 4; the piezoelectric layer 2 is formed on one side of the substrate 1 layer, and isolation grooves 21 are formed on the piezoelectric layer 2 to divide the piezoelectric layer 2 into a first part and a second part arranged side by side at intervals; the surface acoustic wave resonator 3 is formed on the piezoelectric layer 2 and corresponds to the first part; the resonant circuit unit 4 is formed on the piezoelectric layer 2 and corresponds to the second part; wherein, the electrical signal input end of the surface acoustic wave resonator 3 is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator 3 is electrically connected to the resonant circuit unit 4.

[0071] In the technical solution of the present invention, a substrate 1 is provided, and a piezoelectric layer 2 is formed on the substrate 1. By providing the isolation groove 21, the piezoelectric layer 2 is separated into a first part and a second part which are arranged side by side at intervals; the surface acoustic wave resonator 3 is arranged corresponding to the first part; the resonant circuit unit 4 is arranged corresponding to the second part; wherein, the electrical signal input end of the surface acoustic wave resonator 3 is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator 3 is electrically connected to the resonant circuit unit 4; that is, by integrating the resonant circuit unit 4 and the surface acoustic wave resonator 3 on the same chip, the integration degree of the device is improved, the communication bandwidth is increased, the system efficiency is improved, and at the same time, the chip area is reduced and the cost is lowered.

[0072] Specifically, the surface acoustic wave resonator 3 includes an interdigital transducer 31 and two reflectors 32. The interdigital transducer 31 is arranged on the piezoelectric layer 2 and includes an input transducer 311 and an output transducer 312 which are arranged side by side. The input transducer 311 is used to convert the input electrical signal into an acoustic wave for output, and the output transducer 312 is used to receive the acoustic wave output by the input transducer 311 and convert it into an electrical signal for output; the two reflectors 32 are respectively arranged on the two sides of the input transducer 311 and the output transducer 312 which are opposite to each other; wherein, the electrical signal input end of the surface acoustic wave resonator 3 includes the input end of the input transducer 311, and the electrical signal output end of the surface acoustic wave resonator 3 includes the output end of the output transducer 312; it should be noted that the surface acoustic wave resonator 3 realizes the conversion between acoustic energy and electrical energy by fabricating the input transducer 311 and the output transducer 312 on the piezoelectric layer 2. The input transducer 311 converts the input electrical signal into an acoustic wave through the inverse piezoelectric effect, and this acoustic wave propagates along the surface of the substrate of the piezoelectric layer 2, and finally the output transducer 312 converts the acoustic wave into an electrical signal for output. That is, the function of the surface acoustic wave resonator 3 is completed by performing various processes on the acoustic wave propagating on the piezoelectric layer 2 and utilizing the characteristics of the acoustic / electrical transducer.

[0073] It should be noted that the material of the substrate 1 can be selected from silicon, silicon-on-insulator (SOI), silicon carbide, sapphire, glass, etc.; so as to have good insulation performance; at the same time, the size of the substrate 1 is generally set to 2-6 inches; when the material of the substrate 1 is silicon (including silicon-on-insulator), the size of the substrate 1 can be set to 4-12 inches, so as to improve the large-scale production capacity of the filter and reduce the cost.

[0074] The present invention does not limit the material of the piezoelectric layer 2. The material of the piezoelectric layer 2 can be selected from one of zinc oxide, lead zirconate titanate (PZT), gallium nitride, lithium tantalate, and lithium niobate. Specifically, in this embodiment, the piezoelectric layer 2 is provided as an aluminum nitride thin film. Further, the aluminum nitride thin film can be doped to serve as the piezoelectric layer 2 to increase the piezoelectric coefficient of the piezoelectric layer 2, thereby improving the electromechanical coupling coefficient of the surface acoustic wave resonator 3 and further enhancing the performance of the filter.

[0075] Further referring to Figure 1 , in the first embodiment, the resonant circuit unit 4 includes a first dielectric layer 41 and a component group. The first dielectric layer 41 is formed on the end face of the piezoelectric layer 2 facing away from the substrate 1; the component group is formed on the first dielectric layer 41, and the component group includes an inductor 42, a capacitor 43, and a resistor 44 that are arranged side by side at intervals and electrically connected to each other; wherein, the electrical signal output end of the surface acoustic wave resonator 3 is electrically connected to the inductor 42; arranging the inductor 42, the capacitor 43, and the resistor 44 on the first dielectric layer 41 in sequence has a simple structure and is easy to manufacture. The order of the inductor 42, the inductor 42, and the capacitor 43 is not limited and depends on the specific design.

[0076] Specifically, in this embodiment, an intermetal dielectric layer 49 is formed on the first dielectric layer 41, and an inductor 42 metal wire, a capacitor 43 metal wire, and a resistor 44 metal wire are respectively formed on the intermetal dielectric layer 49 to respectively form the inductor 42, the capacitor 43, and the resistor 44; in this way, it not only ensures insulation between the inductor 42, the capacitor 43, and the resistor 44 to avoid short circuits, but also simplifies the manufacturing process.

[0077] Further referring to Figure 2, in the second embodiment, the resonant circuit unit 4 includes a second dielectric layer 45 and a component layer group; the second dielectric layer 45 is formed on the side of the piezoelectric layer 2 away from the substrate 1 layer; the component layer group includes an inductor layer 46, a capacitor layer 47, and a resistor layer 48 that are stacked in sequence, and the inductor layer 46, the capacitor layer 47, and the resistor layer 48 are electrically connected; wherein, the electrical signal output end of the surface acoustic wave resonator 3 is electrically connected to the inductor layer 46; it should be noted that when manufacturing the integrated chip 100, if all components are arranged on the same plane, the area of the integrated chip 100 is approximately the sum of the areas of each component. In a complex circuit, a dozen or even dozens of components may be used. In this way, the area of the integrated chip 100 becomes very large, resulting in an increase in product cost; by arranging the capacitor 43, the resistor 44, and the inductor 42 as the inductor layer 46, the capacitor layer 47, and the resistor layer 48 that are stacked in sequence, the area of the integrated chip 100 is significantly reduced, which not only simplifies the manufacturing process but also reduces the production cost.

[0078] It should be noted that the manufacturing sequence among the inductor layer 46, the capacitor layer 47, and the resistor layer 48 is not limited.

[0079] Specifically, in this embodiment, a first intermetal dielectric layer 491 is formed on the second dielectric layer 45; an inductor 42 metal wire is formed in the first intermetal dielectric layer 491 to form the inductor layer 46; a capacitor 43 dielectric layer is formed on the first intermetal dielectric layer 491; a second intermetal dielectric layer 492 is formed on the capacitor 43 dielectric layer; a capacitor 43 metal wire is formed in the second intermetal dielectric layer 492 to form the capacitor layer 47; a third intermetal dielectric layer 493 is formed on the second intermetal dielectric layer 492; a resistor 44 metal wire is formed on the third intermetal dielectric layer 493 to form the resistor layer 48; a passivation layer 5 is formed on the third intermetal dielectric layer 493 to cover the resistor layer 48; in this way, it not only ensures insulation between the inductor layer 46, the capacitor layer 47, and the resistor layer 48 to avoid short circuits, but also simplifies the manufacturing process.

[0080] In the present invention, an interconnection structure 6 is provided between the resonant circuit unit 4 and the surface acoustic wave resonator 3 to electrically connect the surface acoustic wave resonator 3 to the resonant circuit unit 4; using the interconnection structure 6 to replace traditional wiring not only simplifies the manufacturing steps but also simplifies the internal structure of the integrated chip 100.

[0081] In the present invention, the integrated chip 100 further includes an interconnection structure 6; wherein, the inductor 42, the capacitor 43, and the resistor 44 are electrically connected through the interconnection structure 6; the electrical connection between the components inside the resonant circuit unit 4 is realized through the interconnection structure 6.

[0082] Specifically, the interconnection structure 6 is set to be one of a metal interconnection structure 6 or an air bridge structure.

[0083] Based on the above integrated chip, the present invention describes the manufacturing method of the integrated chip.

[0084] Please refer to Figure 3 , which is the first embodiment of the manufacturing method of the integrated chip provided by the present invention.

[0085] The manufacturing method of the integrated chip includes:

[0086] S10: Provide a substrate layer;

[0087] S20: Form a piezoelectric layer on the substrate layer;

[0088] S30: Make isolation grooves in the piezoelectric layer to divide the piezoelectric layer into a first part and a second part arranged side by side;

[0089] S40: Form a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part;

[0090] S50: Form a resonant circuit unit on the piezoelectric layer corresponding to the second part;

[0091] S60: Make an interconnection structure to electrically connect at least the surface acoustic wave resonator to the resonant circuit unit.

[0092] In this embodiment, a piezoelectric layer is formed on the substrate. By setting the isolation grooves, the piezoelectric layer is divided into a first part and a second part arranged side by side at intervals; the surface acoustic wave resonator is arranged corresponding to the first part; the resonant circuit unit is arranged corresponding to the second part; wherein, the electrical signal input end of the surface acoustic wave resonator is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator is electrically connected to the resonant circuit unit; that is, by integrating the resonant circuit unit and the surface acoustic wave resonator on the same chip, the integration degree of the device is improved, the communication bandwidth is increased, the system efficiency is improved, and at the same time, the chip area is reduced and the cost is lowered.

[0093] Specifically, please refer to Figure 4 , the step S40 of "forming a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part" includes:

[0094] S41: Form an input transducer and an output transducer arranged side by side on the side of the piezoelectric layer facing away from the substrate layer. Among them, in the direction from the first part to the second part, the input transducer and the output transducer are arranged at intervals;

[0095] S42: Form two reflectors on the two sides of the input transducer and the output transducer facing away from each other;

[0096] S43: Form a first passivation layer on the end face of the piezoelectric layer facing away from the substrate layer, where the first passivation layer covers the input transducer, the output transducer, and the two reflectors.

[0097] In this embodiment, the surface acoustic wave resonator realizes the conversion between acoustic energy and electrical energy by fabricating the input transducer and the output transducer on the piezoelectric layer. The input transducer converts the input electrical signal into acoustic waves through the inverse piezoelectric effect. These acoustic waves propagate along the surface of the piezoelectric layer substrate and are finally converted into electrical signals by the output transducer and output. That is, the function of the surface acoustic wave resonator is completed by performing various processes on the acoustic waves propagating on the piezoelectric layer and utilizing the characteristics of the acoustic / electric transducers.

[0098] Specifically, please refer to Figure 5 , the step S50 of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes:

[0099] S51: Form a first dielectric layer on the piezoelectric layer;

[0100] S52: Form an intermetallic dielectric layer on the first dielectric layer;

[0101] S53: Form an inductive metal wire, a capacitive metal wire, and a resistive metal wire on the intermetallic dielectric layer respectively to form an inductor, a capacitor, and a resistor respectively;

[0102] Among them, in the step S60 of "fabricating an interconnect structure": the interconnect structure is also disposed between the inductor, the capacitor, and the resistor.

[0103] In this embodiment, the first dielectric layer and the intermetallic dielectric layer are formed on the substrate, and the inductor, the capacitor, and the resistor are arranged on the intermetallic dielectric layer in sequence to realize the setting of the resonant circuit unit on the substrate, with a simple structure and easy fabrication.

[0104] Specifically, please refer to Figure 6 , the step S50 of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes:

[0105] S51': Form a second dielectric layer on the piezoelectric layer;

[0106] S52': Form a first inter-metal dielectric layer on the second dielectric layer;

[0107] S53': Form inductive metal lines in the first inter-metal dielectric layer to form an inductor;

[0108] S54': Form a capacitive dielectric layer on the first inter-metal dielectric layer;

[0109] S55': Form a second inter-metal dielectric layer on the capacitive dielectric layer;

[0110] S56': Form capacitive metal lines in the second inter-metal dielectric layer to form a capacitor;

[0111] S57': A third metal dielectric layer is formed on the second inter-metal dielectric layer;

[0112] S58': Resistance metal lines are formed on the third metal dielectric layer to form a resistor;

[0113] S59': A passivation layer is formed on the third metal dielectric layer to cover the resistor;

[0114] Wherein, in step S60 of the "manufacturing the interconnection structure": The interconnection structure is also disposed between the inductor, the capacitor, and the resistor.

[0115] In this embodiment, by arranging the capacitor, the resistor, and the inductor as an inductor layer, a capacitor layer, and a resistor layer stacked in sequence, the area of the integrated chip is greatly reduced, which not only simplifies the manufacturing process but also reduces the production cost; at the same time, the inter-metal dielectric layer provided not only insulates between the inductor layer, the capacitor layer, and the resistor layer to avoid short circuits, but also simplifies the manufacturing process.

[0116] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made under the concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. An integrated chip, characterized in that, Comprising: A substrate; A piezoelectric layer formed on one side of the substrate layer, with isolation grooves formed on the piezoelectric layer to divide the piezoelectric layer into a first part and a second part arranged side by side at intervals; A surface acoustic wave resonator formed on the piezoelectric layer and corresponding to the first part; And a resonant circuit unit formed on the piezoelectric layer and corresponding to the second part; Wherein, the electrical signal input end of the surface acoustic wave resonator is electrically connected to an external signal source, and the electrical signal output end of the surface acoustic wave resonator is electrically connected to the resonant circuit unit; The surface acoustic wave resonator includes: Interdigital transducers provided on the piezoelectric layer, including an input transducer and an output transducer arranged side by side. The input transducer is used to convert an input electrical signal into an acoustic wave output, and the output transducer is used to receive the acoustic wave output by the input transducer and convert it into an electrical signal output; and, Two reflectors respectively arranged on two sides of the input transducer and the output transducer facing away from each other; Wherein, the electrical signal input end of the surface acoustic wave resonator includes the input end of the input transducer, and the electrical signal output end of the surface acoustic wave resonator includes the output end of the output transducer.

2. The integrated chip according to claim 1, wherein, The resonant circuit unit includes: A first dielectric layer formed on the end face of the piezoelectric layer facing away from the substrate layer; and, A component group formed on the first dielectric layer. The component group includes an inductor, a capacitor, and a resistor arranged side by side at intervals and electrically connected to each other; Wherein, the electrical signal output end of the surface acoustic wave resonator is electrically connected to one of the inductor, the capacitor, or the inductor.

3. The integrated chip according to claim 1, wherein The resonant circuit unit includes: A second dielectric layer formed on one side of the piezoelectric layer facing away from the substrate layer; and, A component layer group including an inductor layer, a capacitor layer, and a resistor layer stacked in sequence. The inductor layer, the capacitor layer, and the resistor layer are electrically connected to each other; Wherein, the electrical signal output end of the surface acoustic wave resonator is electrically connected to one of the inductor layer, the capacitor layer, or the inductor layer.

4. The integrated chip according to claim 1, wherein, An interconnection structure is provided between the resonant circuit unit and the surface acoustic wave resonator to electrically connect the surface acoustic wave resonator to the resonant circuit unit.

5. The integrated chip according to claim 1, wherein The piezoelectric layer is provided as an aluminum nitride thin film.

6. A method for fabricating an integrated chip based on the integrated chip according to any one of claims 1-5, characterized in that, Comprising: Providing a substrate layer; Forming a piezoelectric layer on the substrate layer; Fabricating isolation grooves in the piezoelectric layer to divide the piezoelectric layer into a first part and a second part arranged side by side; Forming a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part; Forming a resonant circuit unit on the piezoelectric layer corresponding to the second part; Fabricating an interconnection structure to electrically connect at least the surface acoustic wave resonator to the resonant circuit unit; The step of "forming a surface acoustic wave resonator on the piezoelectric layer corresponding to the first part" includes: Forming an input transducer and an output transducer arranged side by side on the side of the piezoelectric layer facing away from the substrate layer. Wherein, in the direction from the first part to the second part, the input transducer and the output transducer are arranged at intervals; Two reflectors are respectively formed on two sides of the input transducer and the output transducer facing away from each other; A first passivation layer is formed on an end surface of the piezoelectric layer facing away from the substrate layer, wherein the first passivation layer covers the input transducer, the output transducer, and the two reflectors.

7. The integrated chip manufacturing method according to claim 6, wherein The step of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes: Forming a first dielectric layer on the piezoelectric layer; Forming an inter-metal dielectric layer on the first dielectric layer; Respectively forming an inductor metal wire, a capacitor metal wire, and a resistor metal wire on the inter-metal dielectric layer to respectively form an inductor, a capacitor, and a resistor; In the step of "fabricating an interconnect structure": The interconnect structure is also disposed between the inductor, the capacitor, and the resistor.

8. The integrated chip manufacturing method according to claim 6, characterized in that, The step of "forming a resonant circuit unit on the piezoelectric layer corresponding to the second part" includes: Forming a second dielectric layer on the piezoelectric layer; Forming a first inter-metal dielectric layer on the second dielectric layer; Forming an inductor metal wire in the first inter-metal dielectric layer to form an inductor; Forming a capacitor dielectric layer on the first inter-metal dielectric layer; Forming a second inter-metal dielectric layer on the capacitor dielectric layer; Forming a capacitor metal wire in the second inter-metal dielectric layer to form a capacitor; A third metal dielectric layer is formed on the second inter-metal dielectric layer; A resistor metal wire is formed on the third metal dielectric layer to form a resistor; A passivation layer is formed on the third metal dielectric layer to cover the resistor; In the step of "fabricating an interconnect structure": The interconnect structure is also disposed between the inductor, the capacitor, and the resistor.

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