A voltage comparison device based on TFT

Abstract

The present invention provides a voltage comparison device based on TFT, comprising: a plurality of comparator units and a plurality of latch units; a bias voltage applied to the comparator unit; a reference voltage is divided by a plurality of resistors connected in series to obtain a plurality of reference voltage divisions, and different reference voltage divisions are respectively connected to the first ends of the plurality of comparator units; the second ends of the plurality of comparator units are all connected to the input voltage; the third end of the comparator unit is connected to the first end of the latch unit; the second ends of the plurality of latch units are all connected to the latch control signal. The present invention can change the comparison reference voltage by changing the bias voltage applied to the comparator unit, and the introduction of the memory unit can prevent the output voltage of the entire voltage comparison device from unnecessary oscillation or other interference with the input, and can control the time when the output appears, while achieving a long-term storage effect.

Description

Technical Field

[0001] The invention belongs to the technical field of voltage comparison circuits, and in particular relates to a TFT-based voltage comparison device. Background Art

[0002] In the prior art, voltage comparators include: 1. Voltage comparators based on switched capacitors, which have the following problems: the switching clock frequency is relatively high, which easily introduces too much high-frequency noise; in addition, it takes time to charge and discharge the capacitor, and the clock switching frequency also takes time, so the comparison time is relatively long; 2. Voltage comparators based on differential amplification methods, which have the following disadvantages: The disadvantage is the presence of glitches caused by too much high-frequency noise. Summary of the invention

[0003] In order to overcome the above technical defects, the present invention provides a TFT-based voltage comparison device, which can reduce interference.

[0004] In order to solve the above problems, the present invention is implemented according to the following technical solutions:

[0005] A TFT-based voltage comparison device comprises: a plurality of comparator units and a plurality of latch units;

[0006] A bias voltage is applied to the comparator unit;

[0007] The reference voltage is divided by a plurality of resistors connected in series to obtain a plurality of reference voltage divisions, and different reference voltage divisions are respectively connected to the first ends of the plurality of comparator units;

[0008] The second terminals of the plurality of comparator units are all connected to an input voltage;

[0009] The third terminal of the comparator unit is connected to the first terminal of the latch unit;

[0010] The second terminals of the latch units are all connected to the latch control signal.

[0011] As a further improvement of the present invention, the comparator unit comprises: a first-stage comparison circuit, a second-stage comparison circuit;

[0012] The first end of the first-stage comparison circuit and the first end of the second-stage comparison circuit are connected to a power supply voltage;

[0013] The second end of the first-stage comparison circuit is connected to the input voltage, and the third end of the first-stage comparison circuit is connected to the second end of the second-stage comparison circuit;

[0014] The third terminal of the second-stage comparison circuit is connected to the latch unit;

[0015] The fourth terminal of the first-stage comparison circuit and the fourth terminal of the second-stage comparison circuit are grounded;

[0016] The fifth end of the first-stage comparison circuit and the fifth end of the second-stage comparison circuit are connected to the reference voltage divider.

[0017] As a further improvement of the present invention, the first-stage comparison circuit includes: a first thin film transistor and a second thin film transistor; wherein the first thin film transistor is a single-gate thin film transistor, and the second thin film transistor is a double-gate thin film transistor;

[0018] The drain of the first thin film transistor is connected to the power supply voltage, and the bottom gate of the first thin film transistor is connected to the source of the first thin film transistor and the drain of the second thin film transistor;

[0019] The bottom gate of the second thin film transistor is connected to the input voltage, the source of the second thin film transistor is grounded, the top gate of the second thin film transistor is connected to the reference voltage divider, and the drain of the second thin film transistor is connected to the second end of the second stage comparison circuit.

[0020] As a further improvement of the present invention, the second-stage comparison circuit includes: a third thin film transistor and a fourth thin film transistor; wherein the third thin film transistor is a single-gate thin film transistor, and the fourth thin film transistor is a double-gate thin film transistor;

[0021] The drain of the third thin film transistor is connected to the power supply voltage, and the bottom gate of the third thin film transistor is connected to the source of the third thin film transistor and the drain of the fourth thin film transistor;

[0022] The bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, the source of the fourth thin film transistor is grounded, a bias voltage is applied to the top gate of the fourth thin film transistor, and the drain of the fourth thin film transistor is connected to the latch unit.

[0023] As a further improvement of the present invention, the first-stage comparison circuit includes: a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are both dual-gate thin film transistors;

[0024] The drain, bottom gate and top gate of the first thin film transistor are connected to a power supply voltage, and the source of the first thin film transistor is connected to the drain of the second thin film transistor and the second end of the second-stage comparison circuit;

[0025] The bottom gate of the second thin film transistor is connected to the input voltage, the source of the second thin film transistor is grounded, and the top gate of the second thin film transistor is connected to the reference voltage divider.

[0026] As a further improvement of the present invention, the second-stage comparison circuit includes: a third thin film transistor and a fourth thin film transistor, wherein the third thin film transistor and the fourth thin film transistor are both dual-gate thin film transistors;

[0027] The top gate, the bottom gate and the drain of the third thin film transistor are connected to the power supply voltage, and the source of the third thin film transistor is connected to the first end of the latch unit and the drain of the fourth thin film transistor;

[0028] The bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, the source of the fourth thin film transistor is grounded, and a bias voltage is applied to the top gate of the fourth thin film transistor.

[0029] As a further improvement of the present invention, the first-stage comparison circuit includes: a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are both dual-gate thin film transistors;

[0030] The drain and bottom gate of the first thin film transistor are connected to a power supply voltage, and the source of the first thin film transistor is connected to the drain of the second thin film transistor and the second end of the second-stage comparison circuit;

[0031] The bottom gate of the second thin film transistor is connected to the input voltage, the top gate of the second thin film transistor is connected to the reference voltage divider, and the source of the second thin film transistor is grounded.

[0032] As a further improvement of the present invention, the second-stage comparison circuit includes: the second-stage comparison circuit includes: a third thin film transistor and a fourth thin film transistor, the third thin film transistor and the fourth thin film transistor are both dual-gate thin film transistors;

[0033] The bottom gate and drain of the third thin film transistor are connected to the power supply voltage, and the source of the third thin film transistor is connected to the drain of the fourth thin film transistor and the first end of the latch;

[0034] A bias voltage is applied to the top gate of the fourth thin film transistor, the bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, and the source of the fourth thin film transistor is grounded.

[0035] As a further improvement of the present invention, the latch unit includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, a first capacitor and a second capacitor;

[0036] The bottom gate of the sixth thin film transistor is connected to the third terminal of the comparator unit and the source of the eighth thin film transistor, the drain of the sixth thin film transistor is connected to the top gate, the bottom gate, the source of the fifth thin film transistor and the source of the seventh thin film transistor, and the top gate of the sixth thin film transistor is connected to the latch control signal;

[0037] The drain electrode of the fifth thin film transistor is connected to the drain electrode of the ninth thin film transistor;

[0038] The bottom gate of the seventh thin film transistor is connected to the latch control signal, the top gate of the seventh thin film transistor is connected to the power supply voltage, the drain of the seventh thin film transistor is grounded through the first capacitor, and the drain of the seventh thin film transistor is connected to the bottom gate of the tenth thin film transistor;

[0039] The top gate, source and bottom gate of the ninth thin film transistor are connected to the drain of the tenth thin film transistor;

[0040] The top gate of the tenth thin film transistor is connected to the power supply voltage, the drain is grounded through the second capacitor, the top gate of the tenth thin film transistor is connected to the power supply voltage, and the source of the tenth thin film transistor is grounded;

[0041] A bottom gate of the eighth thin film transistor is connected to the latch control signal, a top gate of the eighth thin film transistor is connected to the power supply voltage, and a drain of the eighth thin film transistor is connected to a drain of the tenth thin film transistor.

[0042] Compared with the prior art, the present invention has the following beneficial effects: the present invention comprises two modules, namely a comparator unit and a latch unit. The comparator unit serves as a voltage comparator and the latch unit serves as a memory of the comparison result. By changing the external bias voltage, the comparison reference voltage can be changed. The introduction of the memory unit can prevent the output voltage of the entire voltage comparison device from unnecessary oscillation or other interference with the input, and can control the time when the output appears, while achieving a long-term storage effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The specific embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings, wherein:

[0044] Figure 1 This is a schematic diagram of the structure of the voltage comparison device described in Example 1;

[0045] Figure 2 is a schematic structural diagram of the comparator unit described in Example 1;

[0046] Figure 3 is a static voltage output curve of a single comparator unit in Example 1;

[0047] Figure 4 is a timing voltage output curve of a single comparator unit in Example 1;

[0048] Figure 5 It is a structural schematic diagram of the latch unit described in Example 1;

[0049] Figure 6 It is a simulation diagram of a single latch unit of Example 1;

[0050] Figure 7 It is a schematic diagram of simulation results of the voltage comparison device described in Example 1;

[0051] Figure 8 is a schematic structural diagram of the comparator unit described in Example 2;

[0052] Fig. 9 A schematic diagram of the structure of the comparator unit described in Example 3.

[0053] Marking description: 1. Comparator unit; 11. First-stage comparison circuit; 12. Second-stage comparison circuit; 2. Latch unit. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0055] Example 1

[0056] This embodiment provides a TFT-based voltage comparison device, such as Figure 1 The system shown includes: a comparator unit 1 with an external bias voltage; a plurality of comparator units 1 and a plurality of latch units; a reference voltage is divided by a plurality of resistors connected in series to obtain a plurality of reference voltage divisions, and different reference voltage divisions are respectively connected to the first ends of the plurality of comparator units 1; the second ends of the plurality of comparator units 1 are all connected to the input voltage; the third ends of the comparator units 1 are connected to the first end of the latch unit; and the second ends of the plurality of latch units are all connected to the latch control signal.

[0057] Exemplarily, three comparator units 1 and three latch units are selected to form the voltage comparison device of this embodiment. The left side is the reference voltage extraction point. The reference voltage is divided by resistors in series and then input into the comparator units 1 respectively. At this time, the comparison potentials of different comparator units 1 are different. The three comparator units 1 output three comparison results (high level or low level). At this time, the latch control signal is input with a high level, the latch switch is turned on to read the output voltage value of the comparator unit 1, and then the latch control signal is input with a low level to latch the signal. At this time, the output signal of the latch unit, that is, the output 1, output 2, and output 3 signals are the output results after voltage comparison.

[0058] Furthermore, the comparator unit 1 includes: a first-stage comparison circuit 11 and a second-stage comparison circuit 12; a first end of the first-stage comparison circuit 11 and a first end of the second-stage comparison circuit 12 are connected to a power supply voltage; a second end of the first-stage comparison circuit 11 is connected to an input voltage, and a third end of the first-stage comparison circuit 11 is connected to a second end of the second-stage comparison circuit 12; a third end of the second-stage comparison circuit 12 is connected to a latch unit; a fourth end of the first-stage comparison circuit 11 and a fourth end of the second-stage comparison circuit 12 are grounded; a fifth end of the first-stage comparison circuit 11 and a fifth end of the second-stage comparison circuit 12 are connected to the reference voltage divider.

[0059] like Figure 2 As shown, the first-stage comparison circuit 11 includes: a first thin-film transistor TFT1 and a second thin-film transistor TFT2; wherein the first thin-film transistor is a single-gate thin-film transistor and the second thin-film transistor is a double-gate thin-film transistor; the drain of the first thin-film transistor TFT1 is connected to the power supply voltage, the bottom gate of the first thin-film transistor TFT1 is connected to the source of the first thin-film transistor TFT1 and the drain of the second thin-film transistor TFT2; the bottom gate of the second thin-film transistor TFT2 is connected to the input voltage, the source of the second thin-film transistor TFT2 is grounded, the top gate of the second thin-film transistor TFT2 is connected to the reference voltage divider, and the drain of the second thin-film transistor TFT2 is connected to the second end of the second-stage comparison circuit 12.

[0060] like Figure 2As shown, the second-stage comparison circuit 12 includes: a third thin-film transistor TFT3 and a fourth thin-film transistor TFT4; wherein the third thin-film transistor is a single-gate thin-film transistor and the fourth thin-film transistor is a double-gate thin-film transistor; the drain of the third thin-film transistor TFT3 is connected to the power supply voltage, the bottom gate of the third thin-film transistor TFT3 is connected to the source of the third thin-film transistor TFT3 and the drain of the fourth thin-film transistor TFT4; the bottom gate of the fourth thin-film transistor TFT4 is connected to the source of the first thin-film transistor TFT1, the source of the fourth thin-film transistor TFT4 is grounded, the top gate of the fourth thin-film transistor TFT4 is externally biased, and the drain of the fourth thin-film transistor TFT4 is connected to the latch unit.

[0061] In this embodiment, the first thin film transistor TFT1 and the second thin film transistor TFT2 form a first stage comparison circuit 11, and the third thin film transistor TFT3 and the fourth thin film transistor TFT4 form a second stage comparison circuit 12. At the same time, the drain of the second thin film transistor TFT2, i.e., the third terminal A of the first stage comparison circuit 11, is connected to the bottom gate of the fourth thin film transistor TFT4, i.e., the second terminal of the second stage comparison circuit 12, so that the first stage is connected to the second stage. The bottom gate and source of the first thin film transistor TFT1 and the third thin film transistor TFT3 are short-circuited, so that the first thin film transistor TFT1 and the third thin film transistor TFT3 each play the role of a load transistor. At the same time, the first thin film transistor TFT1 and the third thin film transistor TFT3 will select a smaller width-to-length ratio, so that the amplification factor of the comparison circuit is increased, thereby improving the comparison accuracy of the comparator. In addition, short-circuiting the bottom gate with the source can feed back the output to the first thin film transistor TFT1 and the third thin film transistor TFT3. Looking at the first-stage comparison circuit 11 composed of the first thin film transistor TFT1 and the second thin film transistor TFT2, when the output voltage point A is high, a high voltage will be given to the bottom gate of the first thin film transistor TFT1, so that the first thin film transistor TFT1 is turned on and the current of the first thin film transistor TFT1 is increased, so that the voltage of the output voltage point A is higher; when the output voltage point A is low, a low voltage will be given to the bottom gate of the first thin film transistor TFT1, so that the first thin film transistor TFT1 is turned off and the current flowing through the first thin film transistor TFT1 is reduced, so that the voltage of the output voltage point A is lower. The bottom gate of the second thin film transistor TFT2 is connected to the input voltage, and the top gate is connected to the reference voltage voltage divider. In fact, the voltage that the input voltage needs to be compared with at this time is not the reference voltage voltage divider, but the threshold voltage of the second thin film transistor TFT2 under the action of the reference voltage voltage divider. Assuming that at this time, under the action of the reference voltage divided by -1V, the threshold voltage of the second thin film transistor TFT2 shifts from the original 0V to 0.5V. When the input voltage is less than 0.5V, the second thin film transistor TFT2 is in the cut-off state, and the current will flow through the first thin film transistor TFT1 to pull up the voltage at point A, and point A is a high level; when the input voltage is greater than 0.5V, the second thin film transistor TFT2 is in the on state, and the current will flow through the second thin film transistor TFT2 to pull down the voltage at point A, and point A is a low level. After introducing the first-level comparison circuit 11, the second-level comparison circuit 12 is added to improve the sensitivity of the comparator. After the first-level comparison, the voltage amplitude output at point A is approximately in the range of 0V to the power supply voltage. At this time, by adjusting the external bias voltage of the top gate of the fourth thin film transistor TFT4, the threshold voltage of the fourth thin film transistor TFT4 is adjusted to half of the power supply voltage, and the final comparison effect will be better.Because, in the previous comparison, there is a possibility that the input voltage is close to the threshold voltage of the third thin film transistor TFT3, resulting in the output voltage at point A not reaching the lowest level or the highest level. Therefore, an additional comparison circuit is provided to further distinguish the voltages between these levels, thereby improving the sensitivity of the comparator.

[0062] The error of the comparator unit 1 in this embodiment mainly comes from the fact that when the second thin film transistor TFT2 is turned on, the current must be greater than the first thin film transistor TFT1 to truly pull down the voltage at point A, and when the second thin film transistor TFT2 is turned off, the current must be less than the first thin film transistor TFT1 to truly pull up the voltage at point A, so there is a problem of comparison sensitivity. In order to improve the sensitivity of the comparator, the width-to-length ratio of the second thin film transistor TFT2 and the fourth thin film transistor TFT4 can be increased, and the minimum interval of comparison can be further reduced, thereby reducing the error.

[0063] from Figure 3 and Figure 4 It can be seen that when the reference voltage is changed from -2.3V to 1.7V, the comparison voltage is always changing, from -2V to 2V. Therefore, it is proved that the basic function of the comparator unit 1 of this embodiment is realized, and the size of the threshold voltage can be compared when the input voltage comes in. There is a linear relationship between the threshold voltage and the reference voltage, and the adjustment method of the comparison voltage can be obtained by testing and calculation. From the simulation results, it can be concluded that the minimum distinguishable voltage value of the comparator unit 1 is about 0.15V, and the delay time is about 20us.

[0064] like Figure 5As shown, the latch unit includes: a fifth thin film transistor TFT5, a sixth thin film transistor TFT6, a seventh thin film transistor TFT7, an eighth thin film transistor TFT8, a ninth thin film transistor TFT9, a tenth thin film transistor TFT10, a first capacitor C1 and a second capacitor C2; the bottom gate of the sixth thin film transistor TFT6 is connected to the third end of the comparator unit 1 and the source of the eighth thin film transistor, the drain of the sixth thin film transistor TFT6 is connected to the top gate, the bottom gate, the source of the fifth thin film transistor TFT5 and the source of the seventh thin film transistor TFT7, the top gate of the sixth thin film transistor TFT6 is connected to the latch control signal; the drain of the fifth thin film transistor TFT5 is connected to the drain of the ninth thin film transistor TFT9; the bottom gate of the seventh thin film transistor TFT7 is connected to the latch control signal, The top gate of the seventh thin film transistor TFT7 is connected to the power supply voltage, the drain of the seventh thin film transistor TFT7 is grounded through the first capacitor C1, and the drain of the seventh thin film transistor TFT7 is connected to the bottom gate of the tenth thin film transistor TFT10; the top gate, source and bottom gate of the ninth thin film transistor TFT9 are connected to the drain of the tenth thin film transistor TFT10; the top gate of the tenth thin film transistor TFT10 is connected to the power supply voltage and the drain is grounded through the second capacitor C2, the top gate of the tenth thin film transistor TFT10 is connected to the power supply voltage, and the source of the tenth thin film transistor TFT10 is grounded; the bottom gate of the eighth thin film transistor TFT8 is connected to the latch control signal, the top gate of the eighth thin film transistor TFT8 is connected to the power supply voltage, and the drain of the eighth thin film transistor TFT8 is connected to the drain of the tenth thin film transistor TFT10.

[0065] The key point of the working principle is that when the gate of the TFT receives a high level, it will transmit the high level signal of the drain to the source, and when it receives a low level, it will be turned off, similar to a large resistor. At this time, the drain can be as low as 1e-14A (assuming that IGZO-TFT is used, the leakage current is 1e-14A~1e-12A in the source and drain cut-off state), thereby achieving the effect of transmitting the input signal at a high level and maintaining the low level for a longer time.

[0066] The fifth thin film transistor TFT5 and the sixth thin film transistor TFT6 form a first-stage inverter, while the ninth thin film transistor TFT9 and the tenth thin film transistor TFT10 form a second-stage inverter. The two inverters are connected in the same way, and the second stage is represented by explaining the first stage. Here, the top gate and bottom gate of the fifth thin film transistor TFT5 are connected to the source in a Zero-VGS connection, so that the output of the inverter is fed back to the fifth thin film transistor TFT5. When the bottom gate input of the sixth thin film transistor TFT6 is high at this time, the sixth thin film transistor TFT6 will be turned on, which is equivalent to the resistance of the sixth thin film transistor TFT6 decreasing, and the drain voltage of the sixth thin film transistor TFT6 will be lowered. The low voltage acts on the fifth thin film transistor TFT5 through the top gate and bottom gate of the fifth thin film transistor TFT5, and the fifth thin film transistor TFT5 is turned off, so that the output of the inverter is lowered. When the bottom gate input of the sixth thin film transistor TFT6 is low, the sixth thin film transistor TFT6 will be turned off, which is equivalent to the resistance of the sixth thin film transistor TFT6 increasing. At this time, the current passing through is extremely low, and the voltage division is small, so that the output of the inverter is set high and close to the power supply voltage. At this time, the high-level inverter output voltage acts on the fifth thin film transistor TFT5 through the top gate and bottom gate of the fifth thin film transistor TFT5, so that the fifth thin film transistor TFT5 is turned on, thereby continuing to increase the output voltage. In summary, it can be seen that the Zero-VGS connection method can effectively increase the output voltage range of the inverter, thereby improving the inverting ability of the inverter.

[0067] Depend on Figure 6 It can be seen that the zeroing signal RST is not, when it is high level, the circuit starts to use, and when it is low level, it cannot output high level. CTRL is the latch control signal, STEP_IN is the input signal, and S_OUT is the output signal. It can be seen from the data that the function of the latch is completed.

[0068] Figure 7 This is the simulation result of the entire voltage comparison device (including comparator unit 1 and latch unit). It can be seen that when the input changes, the output of comparator unit 1 also changes. When the latch unit control signal is high, the latch unit output will change with the output of comparator unit 1. When the latch control signal is low, the output voltage signal will stabilize at a fixed value. Therefore, after adding the latch unit, the entire comparator device can reduce the occurrence of output oscillation and also improve the convenience of timing control.

[0069] The voltage comparison device provided in this embodiment has the advantages of strong anti-interference ability, adjustable comparison voltage, integration, simple production process and low price cost. The comparator unit 1 is used as a voltage comparator, and the latch unit is used as a memory for the comparison result.

[0070] The comparator unit 1 uses two inverters and a total of four thin-film transistors. Changing the external voltage of the top gate (TG) of the dual-gate thin-film transistor (DG TFT) can change the comparison reference voltage. The introduction of another module - the latch unit can prevent the output voltage of the comparator unit 1 from unnecessary oscillation or other interference with the input, and can control the time when the output appears, while achieving the effect of long-term storage. The comparator unit 1 composed of dual-gate thin-film transistors can use the top gate to regulate the bottom threshold voltage to adjust the size of the comparison voltage, making the voltage comparison device more flexible and practical.

[0071] Example 2

[0072] This embodiment provides another TFT-based voltage comparison device, such as Figure 8 As shown, the difference between it and embodiment 1 is that the structures of the comparator units 1 used in the two are different, specifically: the first-level comparison circuit 11 includes: a first thin film transistor TFT1 and a second thin film transistor TFT2, the first thin film transistor and the second thin film transistor are both double-gate thin film transistors; the drain, bottom gate and top gate of the first thin film transistor TFT1 are connected to the power supply voltage, the source of the first thin film transistor TFT1 is connected to the drain of the second thin film transistor TFT2 and the second end of the second-level comparison circuit 12; the bottom gate of the second thin film transistor TFT2 is connected to the input voltage, the source of the second thin film transistor TFT2 is grounded, and the top gate of the second thin film transistor TFT2 is connected to the reference voltage divider.

[0073] The second-stage comparison circuit 12 includes: a third thin-film transistor TFT3 and a fourth thin-film transistor TFT4, both of which are dual-gate thin-film transistors; the top gate, bottom gate and drain of the third thin-film transistor TFT are connected to the power supply voltage, the source of the third thin-film transistor TFT3 is connected to the first end of the latch unit and the drain of the fourth thin-film transistor TFT4; the bottom gate of the fourth thin-film transistor TFT4 is connected to the source of the first thin-film transistor TFT2, the source of the fourth thin-film transistor TFT4 is grounded, and a bias voltage is applied to the top gate of the fourth thin-film transistor TFT4.

[0074] The first thin film transistor TFT1 , the second thin film transistor TFT2 , the third thin film transistor TFT3 , and the fourth thin film transistor TFT4 are all double-gate thin film transistors.

[0075] For the specific implementation process of this embodiment, please refer to Embodiment 1, which will not be described in detail here.

[0076] Example 3

[0077] This embodiment provides another TFT-based voltage comparison device, such as Fig. 9 As shown, the difference between it and Example 1 is that the comparator unit structures adopted by the two are different, specifically: the first-level comparison circuit includes: a first thin film transistor TFT1 and a second thin film transistor TFT2, the first thin film transistor and the second thin film transistor are both double-gate thin film transistors; the drain and the bottom gate of the first thin film transistor TFT1 are connected to the power supply voltage, the source of the first thin film transistor TFT1 is connected to the drain of the second thin film transistor TFT2 and the second end of the second-level comparison circuit; the bottom gate of the second thin film transistor TFT2 is connected to the input voltage, the top gate of the second thin film transistor TFT2 is connected to the reference voltage divider, and the source of the second thin film transistor TFT2 is grounded.

[0078] The second-stage comparison circuit 12 includes: the second-stage comparison circuit 12 includes: a third thin-film transistor TFT3 and a fourth thin-film transistor TFT4, both of which are dual-gate thin-film transistors; the bottom gate and drain of the third thin-film transistor TFT3 are connected to the power supply voltage, the source of the third thin-film transistor TFT3 is connected to the drain of the fourth thin-film transistor TFT4 and the first end of the latch; a bias voltage is applied to the top gate of the fourth thin-film transistor TFT4, the bottom gate of the fourth thin-film transistor TFT4 is connected to the source of the first thin-film transistor TFT1, and the source of the fourth thin-film transistor TFT4 is grounded.

[0079] The first thin film transistor TFT1 and the third thin film transistor TFT3 are single-gate thin film transistors, and the second thin film transistor TFT2 and the fourth thin film transistor TFT4 are double-gate thin film transistors.

[0080] For the specific implementation process of this embodiment, please refer to Embodiment 1, which will not be described in detail here.

[0081] It can be seen from Examples 1 to 3 that the present invention has the following beneficial effects:

[0082] 1. The voltage comparison circuit composed of thin film transistors is used, and the preparation process is fully compatible with the mature TFT LCD process, which reduces the production cost and improves the integration.

[0083] 2. The combination of voltage comparator circuit and latch circuit is used to reduce the possibility of output voltage oscillation and improve the accuracy of output.

[0084] 3. By adjusting the threshold voltage of the thin film transistor through reference voltage division, the comparison voltage of the voltage comparison circuit is adjusted to reduce excessive external bias voltage, and the relationship between the reference voltage and the comparison voltage is quantified.

[0085] 4. The thin film transistor structure can be single-gate or double-gate. The thin film transistor material can be amorphous silicon, polycrystalline silicon, amorphous indium gallium zinc oxide (IGZO) and other materials. The channel shape of the double-gate thin film transistor can be a planar channel, a π-type channel, a 3D fin-type channel and other shapes.

[0086] 5. There are differences in the width-to-length ratios used by thin film transistors. The thin film transistors that act as load transistors use a smaller width-to-length ratio, while the driving thin film transistors that mainly receive signals use a larger width-to-length ratio.

[0087] 6. By increasing the width-to-length ratio of the driving thin film transistor in the comparator circuit, a smaller comparison accuracy can be obtained.

[0088] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A TFT-based voltage comparison device, characterized in that: include: A plurality of comparator units and a plurality of latch units; A bias voltage is applied to the comparator unit; The reference voltage is divided by a plurality of resistors connected in series to obtain a plurality of reference voltage divisions, and different reference voltage divisions are respectively connected to the first ends of the plurality of comparator units; The second terminals of the plurality of comparator units are all connected to an input voltage; The third terminal of the comparator unit is connected to the first terminal of the latch unit; The second terminals of the latch units are all connected to the latch control signal.

2. The voltage comparison device according to claim 1, characterized in that: The comparator unit comprises: a first-stage comparison circuit and a second-stage comparison circuit; The first end of the first-stage comparison circuit and the first end of the second-stage comparison circuit are connected to a power supply voltage; The second end of the first-stage comparison circuit is connected to the input voltage, and the third end of the first-stage comparison circuit is connected to the second end of the second-stage comparison circuit; The third terminal of the second-stage comparison circuit is connected to the latch unit; The fourth terminal of the first-stage comparison circuit and the fourth terminal of the second-stage comparison circuit are grounded; The fifth end of the first-stage comparison circuit and the fifth end of the second-stage comparison circuit are connected to the reference voltage divider.

3. The voltage comparison device according to claim 2, characterized in that: The first-stage comparison circuit comprises: a first thin film transistor and a second thin film transistor; wherein the first thin film transistor is a single-gate thin film transistor and the second thin film transistor is a double-gate thin film transistor; The drain of the first thin film transistor is connected to the power supply voltage, and the bottom gate of the first thin film transistor is connected to the source of the first thin film transistor and the drain of the second thin film transistor; The bottom gate of the second thin film transistor is connected to the input voltage, the source of the second thin film transistor is grounded, the top gate of the second thin film transistor is connected to the reference voltage divider, and the drain of the second thin film transistor is connected to the second end of the second stage comparison circuit.

4. The voltage comparison device according to claim 3, characterized in that: The second-stage comparison circuit comprises: a third thin film transistor and a fourth thin film transistor; wherein the third thin film transistor is a single-gate thin film transistor, and the fourth thin film transistor is a double-gate thin film transistor; The drain of the third thin film transistor is connected to the power supply voltage, and the bottom gate of the third thin film transistor is connected to the source of the third thin film transistor and the drain of the fourth thin film transistor; The bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, the source of the fourth thin film transistor is grounded, a bias voltage is applied to the top gate of the fourth thin film transistor, and the drain of the fourth thin film transistor is connected to the latch unit.

5. The voltage comparison device according to claim 2, characterized in that: The first-stage comparison circuit includes: a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are both dual-gate thin film transistors; The drain, bottom gate and top gate of the first thin film transistor are connected to a power supply voltage, and the source of the first thin film transistor is connected to the drain of the second thin film transistor and the second end of the second-stage comparison circuit; The bottom gate of the second thin film transistor is connected to the input voltage, the source of the second thin film transistor is grounded, and the top gate of the second thin film transistor is connected to the reference voltage divider.

6. The voltage comparison device according to claim 3, characterized in that: The second-stage comparison circuit comprises: a third thin film transistor and a fourth thin film transistor, wherein the third thin film transistor and the fourth thin film transistor are both dual-gate thin film transistors; The top gate, the bottom gate and the drain of the third thin film transistor are connected to the power supply voltage, and the source of the third thin film transistor is connected to the first end of the latch unit and the drain of the fourth thin film transistor; The bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, the source of the fourth thin film transistor is grounded, and a bias voltage is applied to the top gate of the fourth thin film transistor.

7. The voltage comparison device according to claim 2, characterized in that: The first-stage comparison circuit includes: a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are both dual-gate thin film transistors; The drain and bottom gate of the first thin film transistor are connected to a power supply voltage, and the source of the first thin film transistor is connected to the drain of the second thin film transistor and the second end of the second-stage comparison circuit; The bottom gate of the second thin film transistor is connected to the input voltage, the top gate of the second thin film transistor is connected to the reference voltage divider, and the source of the second thin film transistor is grounded.

8. The voltage comparison device according to claim 3, characterized in that: The second-stage comparison circuit comprises: the second-stage comparison circuit comprises: a third thin film transistor and a fourth thin film transistor, wherein the third thin film transistor and the fourth thin film transistor are both dual-gate thin film transistors; The bottom gate and drain of the third thin film transistor are connected to the power supply voltage, and the source of the third thin film transistor is connected to the drain of the fourth thin film transistor and the first end of the latch; A bias voltage is applied to the top gate of the fourth thin film transistor, the bottom gate of the fourth thin film transistor is connected to the source of the first thin film transistor, and the source of the fourth thin film transistor is grounded.

9. The voltage comparison device according to any one of claims 1 to 8, characterized in that: The latch unit includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, a first capacitor and a second capacitor; The bottom gate of the sixth thin film transistor is connected to the third terminal of the comparator unit and the source of the eighth thin film transistor, the drain of the sixth thin film transistor is connected to the top gate, the bottom gate, the source of the fifth thin film transistor and the source of the seventh thin film transistor, and the top gate of the sixth thin film transistor is connected to the latch control signal; The drain electrode of the fifth thin film transistor is connected to the drain electrode of the ninth thin film transistor; The bottom gate of the seventh thin film transistor is connected to the latch control signal, the top gate of the seventh thin film transistor is connected to the power supply voltage, the drain of the seventh thin film transistor is grounded through the first capacitor, and the drain of the seventh thin film transistor is connected to the bottom gate of the tenth thin film transistor; The top gate, source and bottom gate of the ninth thin film transistor are connected to the drain of the tenth thin film transistor; The top gate of the tenth thin film transistor is connected to the power supply voltage, the drain is grounded through the second capacitor, the top gate of the tenth thin film transistor is connected to the power supply voltage, and the source of the tenth thin film transistor is grounded; A bottom gate of the eighth thin film transistor is connected to the latch control signal, a top gate of the eighth thin film transistor is connected to the power supply voltage, and a drain of the eighth thin film transistor is connected to a drain of the tenth thin film transistor.

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