Manufacturing active bridge coupled gpulets

Abstract

Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, the method of manufacturing includes a face-to-face process in which a first GPU dielet and a second GPU dielet are bonded to a temporary carrier wafer. A front side of an active bridge dielet is bonded to a front side of the first and second GPU dielets prior to mounting the GPU dielets to a carrier substrate. In other embodiments, the method of manufacturing includes a face-to-back process in which a front side of an active bridge dielet is bonded to a back side of the first and second GPU dielets.

Description

BACKGROUND

[0001] Computing devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, games, and other devices require more performance and features to be integrated into smaller and smaller spaces. As a result, the density of processor dies and the number of dies integrated within a single integrated circuit (IC) package has increased. Some conventional multi-chip modules include two or more semiconductor chips that are mounted side-by-side on a carrier substrate or, in some cases, on an interposer (a so-called "2.5D") that in turn is mounted on a carrier substrate. BRIEF DESCRIPTION OF DRAWINGS

[0002] The disclosure can be better understood, and its numerous features and advantages can become apparent to those skilled in the art by reading the following specification in conjunction with the following figures. Like reference numerals are used throughout the figures to designate similar or identical items.

[0003] Figure 1 is a block diagram illustrating a processing system employing an active bridge chiplet for coupling GPU chiplets according to some embodiments.

[0004] Figure 2 is a block diagram illustrating a cross-sectional view of a GPU chiplet and an active bridge chiplet according to some embodiments.

[0005] Figure 3 is a block diagram illustrating another cross-sectional view of a GPU chiplet and an active bridge chiplet according to some embodiments.

[0006] Figures 4A to 4G is a block diagram illustrating a face-to-face process flow for fabricating an active bridge coupled GPU chiplet according to some embodiments.

[0007] Figures 5A to 5D is a block diagram illustrating a face-to-back process flow for fabricating an active bridge coupled GPU chiplet according to some embodiments. DETAILED DESCRIPTION

[0008] Manufacturing costs of conventional monolithic die designs are increasing. Small chips have been successfully used in CPU architectures to reduce manufacturing costs and increase yield, as the heterogeneous computing nature of CPUs more naturally lends itself to splitting CPU cores into different units that do not need to communicate much with each other. In contrast, GPU work inherently includes parallel work. However, the geometry of GPU processing includes not only fully parallel working parts, but also work that needs to be synchronized in order between different parts. Thus, the GPU programming model of distributing work parts across different threads is generally inefficient, as parallelism is difficult to distribute across multiple different work groups and small chips. In particular, synchronizing the memory contents of shared resources across the entire system to provide a consistent memory view to applications is computationally difficult and expensive. Furthermore, from a logical perspective, applications are written with the assumption that there is only a single GPU in the system. That is, even though conventional GPUs include many GPU cores, applications are programmed to address a single device. For at least these reasons, introducing a small chip design approach into GPU architectures has historically been challenging.

[0009] To improve system performance through the use of GPU small chips without changing the relatively simple programming model, Figures 1 to 5D Systems and methods of manufacturing active bridge coupled GPU small chips are shown. Currently, various architectures already have at least one level of cache (e.g., L3 or other last level cache (LLC)) that is consistent across the entire conventional GPU die. Here, a small chip based GPU architecture positions those physical resources (e.g., LLC) on different dies and communicatively couples those physical resources, thereby unifying the LLC level and maintaining cache coherency across all GPU small chips. Thus, the L3 cache level is consistent despite running in a massively parallel environment. During operation, a memory address request from a CPU is transmitted to only a single GPU small chip, which then communicates with the active bridge small chip to locate the requested data. From the perspective of the CPU, it appears to be addressing a single chip, monolithic GPU. This allows for the use of large capacity, multi-small chip GPUs that appear as a single device in an application.

[0010] As discussed herein, in various embodiments, the manufacturing method includes a face-to-face process in which a first GPU small chip and a second GPU small chip are bonded to a temporary carrier wafer. Prior to mounting the GPU small chips to the carrier substrate, a front side of an active bridge small chip is bonded to a front side of the first and second GPU small chips. In other embodiments, the manufacturing method includes a face-to-back process in which a front side of an active bridge small chip is bonded to a back side of the first and second GPU small chips.

[0011] Figure 1is a block diagram illustrating a processing system 100 employing active bridgelets for coupling GPUlets according to some embodiments. In the depicted example, system 100 includes a central processing unit (CPU) 102 for executing instructions and an array 104 of one or more GPUlets, such as three shown GPUlets 106-1, 106-2, and 106-N (collectively, GPUlets 106). In various embodiments, and as used herein, the term "let" refers to any device including, but not limited to, the following characteristics: 1) the let includes an active silicon die that contains at least a portion of the computational logic for solving a complete problem (i.e., the computational workload is distributed across multiple of these active silicon dies); 2) the lets are packaged together as a monolithic unit on the same substrate; 3) the programming model preserves the notion that the combination of these individual computational dies (i.e., GPUlets) is a single monolithic unit (i.e., each let is not exposed to an application program using the lets to process a computational workload as a separate device).

[0012] In various embodiments, CPU 102 is connected to a system memory 110, such as a dynamic random access memory (DRAM), via a bus 108. In various embodiments, system memory 110 can also be implemented using other types of memory including static random access memory (SRAM), non-volatile RAM, and the like. In the illustrated embodiment, CPU 102 communicates with system memory 110 and GPUlets 106-1 over bus 108, which is implemented as a peripheral component interconnect (PCI) bus, a PCI-E bus, or other type of bus. However, some embodiments of system 100 include GPUlets 106-1 in communication with CPU 102 through a direct connection or via a dedicated bus, bridge, switch, router, or the like.

[0013] As shown, CPU 102 includes a number of processes, such as one or more application programs 112 to generate graphics commands and a user mode driver 116 (and / or other drivers, such as a kernel mode driver). In various embodiments, one or more application programs 112 include an application program that utilizes the functionality of GPUlets 106, such as an application program that generates work in system 100 or an operating system (OS). In some implementations, application programs 112 include one or more graphics instructions that instruct GPUlets 106 to render a graphical user interface (GUI) and / or a graphics scene. For example, in some implementations, the graphics instructions include instructions that define a set of one or more graphics primitives to be rendered by GPUlets 106.

[0014] In some embodiments, the application 112 utilizes a graphics application programming interface (API) 114 to invoke a user-mode driver 116 (or similar GPU driver). The user-mode driver 116 issues one or more commands to the array of one or more GPUlets 104 for rendering one or more graphics primitives into a displayable graphics image. Based on the graphics instructions issued by the application 112 to the user-mode driver 116, the user-mode driver 116 formulates one or more graphics commands that specify one or more operations for the GPUlets to perform for rendering the graphics. In some embodiments, the user-mode driver 116 is part of the application 112 running on the CPU 102. For example, in some embodiments, the user-mode driver 116 is part of a gaming application running on the CPU 102. Similarly, in some implementations, a kernel-mode driver (not shown) formulates the one or more graphics commands as part of an operating system running on the CPU 102, either alone or in combination with the user-mode driver 116.

[0015] In Figure 1 the depicted embodiment, the active bridgelet 118 communicatively couples the GPUlets 106 (i.e., GPUlets 106-1 through 106-N) to one another. Although three GPUlets 106 are shown in Figure 1 , the number of GPUlets in the array of GPUlets 104 is a matter of design choice and varies in other embodiments, such as described in more detail below. In various embodiments, such as discussed in more detail below with respect to Figure 2 , the active bridgelet 118 includes an active silicon bridge as a high-bandwidth die-to-die interconnect between the GPUlet dies. Further, the active bridgelet 118 operates as a memory crossbar with a shared, unified last level cache (LLC) to provide inter-GPUlet communication as well as to route cross-GPUlet synchronization signals. The caches are naturally active components (i.e., operation requires power), so the memory crossbar (e.g., the active bridgelet 118) is active to keep those cache memories active. Thus, the cache size can be configured according to the physical size of the active bridgelet 118 for different applications and different GPUlet configurations, and the one or more underlying GPUlets (e.g., the GPUlets 106) that the active bridgelet 118 is communicatively coupled to do not bear the cost (e.g., cost related to physical space, power limitations, etc.) of that external cache on the active bridgelet 118.

[0016] As an overview of general operation, CPU 102 is communicatively coupled to a single GPU chiplet (i.e., GPU chiplet 106-1) through bus 108. CPU-to-GPU transactions or communications from CPU 102 to array 104 of chiplets 106 are received at GPU chiplet 106-1. Subsequently, any inter-chiplet communications are routed as appropriate through active bridge chiplet 118 to access memory channels on other GPU chiplets 106. In this way, GPU chiplet-based system 100 includes GPU chiplets 106 that can be addressed as a single monolithic GPU from the perspective of software developers, thus avoiding any need for programmers or developers to consider chiplet-specific considerations (e.g., CPU 102 and any associated applications / drivers are unaware of the chiplet-based architecture). As described in greater detail below, in some embodiments, semiconductor chip including array 104 of GPU chiplets 106 is constructed using a face-to-face process flow or a face-to-back process flow. Figure 1

[0017] It will be appreciated that in different embodiments, GPU chiplets 106 are placed in different arrangements such that active bridge 118 supports more than two GPU chiplets. One example is shown in Figure 1 as layout 111. In particular, layout 111 illustrates a top view of an arrangement of active bridges 118 providing interconnection for four or more GPU chiplets, according to some embodiments. In the depicted example of layout 111, GPU chiplets are arranged in pairs to form two“columns” of GPU chiplets, with active bridges 118 placed between the columns. Thus, GPU chiplet 106-2 is placed to the side of GPU chiplet 106-1, GPU 106-3 is placed below GPU chiplet 106-1, and GPU 106-4 is placed to the side of GPU chiplet 106-3 and below GPU chiplet 106-4. Active bridges 118 are placed between the lateral pairs of GPU chiplets.

[0018] Reference is made to Figure 2 Additional details of the chiplet-based architecture can be appreciated, which is a block diagram illustrating a cross-sectional view of an active bridge-coupled GPU chiplet 200, according to some embodiments. This view provides a perspective of GPU chiplets 106-1, 106-2 and active bridge chiplet 118 along the direction of the Figure 1 Figure 1 ​​A cross-sectional view of the line shown (e.g., line "A"). In various embodiments, each GPU chiplet 106 is configured without any through-silicon vias (TSVs). The GPU chiplets 106 are communicatively coupled via active bridge chiplets 118. In various embodiments, the active bridge chiplets 118 are interconnect chips made of silicon, germanium, or other semiconductor materials, and are bulk semiconductor, semiconductor-on-insulator, or other designs.

[0019] The active bridge chiplet 118 includes multiple internal conductor traces (not shown), which, in different embodiments, may be located on a single layer or multiple layers as needed. The traces are connected via conductive paths to conductor structures, such as those in the PHY region of the GPU chiplet 106 (e.g., ...). Figure 2 The memory PHY 212 is electrically connected. In this way, the active bridge chiplet 118 is an active bridge die that communicatively couples to and routes communication between GPU chiplets 106, thereby forming an active routing network.

[0020] like Figure 2 As shown, carrier wafer 202 is bonded to GPU chiplets 106-1 and 106-2. In this embodiment configuration, TSV 204 reaches GPU chiplet 106 via an active bridge chiplet, but one or more graphics core dies themselves do not have any TSVs constructed. Instead, for transmitting signal data, dielectric vias (TDVs) 206 tunnel through gap-filled dielectric layer 208. Gap-filled dielectric layer 208 (or other gap-filling material) occupies areas where there are no bridge chiplet dies and one or more graphics core dies (e.g., areas with a vertical difference between GPU chiplet 106 and active bridge chiplet 118). As shown, TDV 206 connects the input / output (I / O) power of GPU chiplet 106 downward to solder interconnects 210, which in different embodiments are solder bumps, microbumps, etc. In this way, the gap-filling dielectric layer 208 makes the two planes of the bumps (e.g., bump 212) on both the GPU chiplet 106 and the active bridge chiplet 118 become the same plane.

[0021] As described in greater detail below with respect to FIG. 4, the actively bridge coupled GPU chiplet 200 is constructed using a face-to-face process flow. That is, the actively bridge coupled GPU chiplet 200 is oriented such that the front face F of the GPU chiplet 106 faces the front face F of the active bridge chiplet. Those skilled in the art will recognize that the front face F (also referred to and interchangeably as the “active surface” or “front surface”) refers to the first surface of the semiconductor die on which active circuitry 214 (e.g., functional elements, wiring, etc.) is located. Similarly, the back face B (also referred to and interchangeably as the “bottom surface”) refers to the second surface opposite the front face F on the semiconductor die.

[0022] In various embodiments, as shown in FIG. 3, the components are electrically interfaced with other electrical structures (such as a circuit board or other structure) through interconnect structures 210 and 212 (e.g., solder balls, etc.). For example, as shown in FIG. 3, the actively bridge coupled GPU chiplet 200 is mounted on another device, such as a circuit board 216. However, those skilled in the art will understand that in other embodiments, various types of interconnect structures are used, such as pins, a land grid array structure, other interconnects, etc., without departing from the scope of the present disclosure. Figure 2 Figure 2

[0023] Figure 3 is a block diagram illustrating another cross-sectional view of an actively bridge coupled GPU chiplet 300, in accordance with some embodiments. This view provides a cross-sectional view of the GPU chiplets 106-1, 106-2 and the active bridge chiplet 118 along line A. Figure 1 As previously described, the GPU chiplets 106 are communicatively coupled through the active bridge chiplet 118. In various embodiments, the active bridge chiplet 118 is an interconnect chip composed of silicon, germanium, or other semiconductor material, and is a bulk semiconductor, a semiconductor-on-insulator, or other design.

[0024] The active bridge chiplet 118 includes a plurality of internal conductor traces (not shown) that, in different embodiments, are located on a single layer or multiple layers as needed. The traces are electrically interfaced with conductor structures (e.g., memory PHY 212 of the GPU chiplet 106) of, for example, the PHY region of the GPU chiplet 106 through conductive vias. In this manner, the active bridge chiplet 118 is an active bridge die that communicatively couples the GPU chiplets 106 and routes communications between the GPU chiplets 106, thereby forming an active routing network. Figure 2

[0025] As shown in FIG. 3 and in a manner similar to the components of FIG. 2, the carrier wafer 302 is bonded to the GPU chiplets 106-1 and 106-2. However, unlike FIG. 2, the active bridge chiplet 118 is not bonded to the carrier wafer 302. Figure 3 Figure 2 Figure 2 ​​​​​In contrast to this embodiment, each GPU chiplet 106 includes a through-silicon via (TSV) 304. In this embodiment configuration, the TSV 304 passes through the GPU chiplet 106, but the active bridge chiplet 118 itself does not have any TSVs. Furthermore, the actively bridge-coupled GPU chiplets also do not include any TSVs because the TSV 304 connects the input / output (I / O) power of the active bridge chiplet downwards to the solder interconnect 306, which in various embodiments is a solder bump, microbump, etc. An interconnect structure 308 is electrically coupled to the GPU chiplet 106. In various embodiments, a dummy silicon layer 310 (or other gap-filling material) occupies the area where there are no bridge chiplet dies and one or more graphics core dies (e.g., the area with a vertical difference between the GPU chiplet 106 and the active bridge chiplet 118). In this way, the dummy silicon layer 310 makes the interconnect bumps associated with the communication ground and electrically coupled GPU chiplet 106 and active bridge chiplet 118 both on the same plane and forms a monolithic chip.

[0026] As described in more detail below with reference to FIG5, the actively bridge-coupled GPU chiplet 300 is constructed using a face-to-back process. In particular, the actively bridge-coupled GPU chiplet 200 is oriented such that the front face F of the active bridge 118 faces the back face B of the GPU chiplet 106. Those skilled in the art will recognize that the front face F (also referred to and interchangeably referred to as the “active surface” or “front surface”) refers to the first surface of the semiconductor die on which active circuitry 312 and 314 (e.g., functional elements, wiring, etc.) is positioned. Similarly, the back face B (also referred to and interchangeably referred to as the “bottom surface”) refers to the second surface opposite the front face F on the semiconductor die.

[0027] In various implementation schemes, such as Figure 3 The components shown are electrically connected to other electrical structures (such as circuit boards, substrates, or other structures) via interconnect structures 306 and 308 (e.g., solder balls). For example, as Figure 3 As shown, the actively bridge-coupled GPU chiplet 300 is mounted on another device, such as circuit board 316. However, those skilled in the art will understand that in other embodiments, various types of interconnect structures, such as pins, planar mesh array structures, other interconnects, etc., are used without departing from the scope of this disclosure.

[0028] Active bridge chip 118, such as the one mentioned above. Figures 1 to 3As described, this provides communication between routing structures of two or more dies and provides consistent L3 memory access with uniform memory access behavior (or substantially uniform memory access behavior). Those skilled in the art will recognize that the performance of a processing system typically scales linearly based on the number of GPU chiplets utilized by the physical replication nature (e.g., as the number of GPU chiplets increases, so does the number of memory PHYs, workgroup processors (WGPs) 202, etc.).

[0029] Now for reference Figures 4A to 4G This illustrates a GPU chiplet used for fabricating an actively bridge-coupled circuit (e.g., Figure 2 A block diagram of the face-to-face process flow for an actively bridge-coupled GPU chiplet 200. Those skilled in the art will recognize that in some embodiments, the actively bridge-coupled GPU chiplet described herein is fabricated as a single unit, while in other embodiments it is fabricated together in a wafer-like structure (e.g., a reconstituted wafer) equivalent to a wafer-level process.

[0030] exist Figure 4A A cross-sectional view depicting a temporary carrier wafer 402 is shown. In various embodiments, the temporary carrier wafer 402 is made of glass, silicon, other types of carrier wafer materials, etc. A graphics core die (GCD) 404 (e.g., as previously described...) Figures 1 to 3 Multiple known good dies (KGDs) of the described GPU chiplet 106 are bonded to a temporary carrier wafer 402. In various embodiments, each graphics core die 404 (e.g., GPU chiplet 106) is configured without any through-silicon vias (TSVs) and is also interchangeably referred to herein as a "TSV-free GCD" or a "TSV-free GPU chiplet". Figure 4A The bonding involves temporarily bonding the front side of the graphics core die 404 to the temporary carrier wafer 402. In various embodiments, temporarily bonding the graphics core die 404 includes using adhesives, such as light- or heat-activated adhesives, double-sided tape, or other types of bonding techniques that can be subsequently detached.

[0031] exist Figure 4B place, Figure 4A The graphics core die 404 is thinned and one or more gap-filling dielectric layers 406 are deposited on top of the temporary carrier wafer 402. In various embodiments, Figure 4B The gap filling includes applying one or more gap-filling dielectric layers 406 using spin-coating and baking techniques, other dielectric layer deposition techniques, etc. Furthermore, in various embodiments, Figure 4BThe gap filling of 406 includes applying one or more gap fill dielectric layers 406, such as by filling areas having vertical disparities between the temporary carrier wafer 402 and the backside B of the graphics core die 404 to form a planar surface. In some embodiments, when the application of the one or more gap fill dielectric layers 406 covers the backside B of the graphics core die 404, the surface of the one or more gap fill dielectric layers 406 is subjected to a lapping process to expose the substrate portion of the backside B of the graphics core die 404. At this point, the combination of the graphics core die 404 and the one or more gap fill dielectric layers 406 constitutes a reconstituted unit (or wafer, if performed on a wafer level basis) that can be separated from the temporary carrier wafer 402.

[0032] At Figure 4C , a carrier flip is applied and the temporary carrier wafer 402 is separated from the combination of the graphics core die 404 and the one or more gap fill dielectric layers 406. In various embodiments, Figure 4C The separation of 402 includes applying a process that is suitable for the technique originally used to bond the temporary carrier wafer 402 to the graphics core die 404. For example, in various embodiments, Figure 4C The separation of 402 includes a thermal release of tape or adhesive, a light or heat activated adhesive release, etc. Additionally, the combination of the graphics core die 404 and the one or more gap fill dielectric layers 406 is bonded to a second carrier wafer 408, where the backside B of the graphics core die 404 is bonded to the second carrier wafer 408 for mechanical support. In this manner, the frontside F of the graphics core die 404 is exposed.

[0033] At Figure 4D , a known good die of the active bridge die 410 (e.g., an active bridge dielet 118 as previously described with respect to Figures 1 to 3 is bonded to the second carrier wafer 408. The active bridge die 410 includes TSVs 204, as previously described with respect to Figure 2 . In various embodiments, Figure 4D The operation of 410 includes bonding the frontside F of the active bridge die 410 to the frontside F of the graphics core die 404 (hence the "face-to-face process" terminology referred to herein).

[0034] At Figure 4E , the active bridge die 410 is thinned to expose the TSVs 204, and an additional one or more gap fill dielectric layers 406 are deposited on the existing gap fill dielectric layers 406 of the graphics core die 404 and Figures 4A to 4D . In various embodiments, Figure 4E The gap filling of 406 includes applying one or more gap fill dielectric layers 406 using spin-on and bake techniques, other dielectric layer deposition techniques, etc. Further, in various embodiments, Figure 4BThe gap filling includes applying one or more gap-fill dielectric layers 406, such as by filling regions with vertical differences between the back faces B of the patterned core die 404 and the active bridge die 410 to form a flat surface. In some embodiments, when the application of one or more gap-fill dielectric layers 406 covers the back face B of the active bridge die 410, the surface of the one or more gap-fill dielectric layers 406 undergoes a polishing process to expose the substrate portion of the back face B of the active bridge die 410. Furthermore, one or more dielectric vias 412 (such as those previously mentioned) are etched in the one or more gap-fill dielectric layers 406. Figure 2 Described as TDV 206, the one or more dielectric vias tunnel downwards through one or more gap-filled dielectric layers 406 to reach the pattern core die 404. For example, in some embodiments, the one or more gap-filled dielectric layers 406 are appropriately masked and photolithographically patterned, such as by optical lithography to create voids / openings leading to the pattern core die 404. In various embodiments, the one or more voids created by etching through the one or more gap-filled dielectric layers 406 are filled with copper or other materials with high thermal conductivity and / or electrical conductivity to form conductive pillars communicatively coupled to the pattern core die 404 (e.g., TDV 412).

[0035] exist Figure 4F At the bottom surface of the active bridge die 410 and one or more gap-filling dielectric layers 406, a redistribution layer (RDL) structure 414 is fabricated. In various embodiments, the RDL structure 414 includes one or more conductor structures 416 coupled to the TDV 412 via the gap-filling dielectric layer 406 and one or more conductor structures 418 coupled to the TSV 204 of the active bridge die 410. It should be understood that in various embodiments, the RDL structure 414 is fabricated using design rules for small spaces associated with the I / O mapping of the graphics core die 404. In some embodiments, one or more conductor structures 416 and 418 are formed by masking and electroplating processes to create laterally extending conductors.

[0036] exist Figure 4G The bumping process is completed by applying conductor bumps 420 to one or more conductor structures 416 and 418 (e.g., bump pads) using known solder plating, pick-and-place, or printing and reflow techniques. At this stage, the actively bridge-coupled GPU chiplet is completed and ready to be mounted onto a substrate, such as... Figure 2 The circuit board 216 shown is shown.

[0037] Now for reference Figures 5A to 5D This illustrates a GPU chiplet used for fabricating an actively bridge-coupled circuit (e.g., Figure 3FIG. 1 illustrates a block diagram of a face-to-back process flow of an active bridge coupled GPU chiplet 300. Those skilled in the art will recognize that the active bridge coupled GPU chiplets described herein are fabricated as a single unit in some embodiments, while in other embodiments are fabricated together in a wafer-like structure (e.g., a reconstituted wafer) equivalent to a wafer-level process.

[0038] At Figure 5A , a cross-sectional view depicting a temporary carrier wafer 502 is shown. In various embodiments, the temporary carrier wafer 502 is composed of glass, silicon, other types of carrier wafer materials, and the like. A plurality of known good dies (KGDs) of graphics core dies (GCDs) 504 (e.g., GPU chiplets 106 as previously described with respect to FIG. 1) are bonded to the temporary carrier wafer 502. In various embodiments, the bonding of the GCDs 504 to the temporary carrier wafer 502 includes a temporary bonding of the front face F of the GCDs 504 to the temporary carrier wafer 502. Figures 1 to 3 Figure 2 In contrast to embodiments of the GPU chiplet 106 and Figures 4A to 4G , each GPU chiplet 106 includes through-silicon vias (TSVs) 506. Figure 5A The bonding of the GCDs 504 to the temporary carrier wafer 502 includes a temporary bonding of the front face F of the GCDs 504 to the temporary carrier wafer 502. In various embodiments, the temporary bonding of the GCDs 504 includes the use of an adhesive, such as a light or heat activated adhesive, double-sided tape, or other type of bonding technique that can be subsequently released.

[0039] At Figure 5B , the GCDs 504 are thinned to expose the TSVs 506 such that the TSVs 506 pass through the GPU chiplet 106 from the front face F to the back face B. In addition, one or more gap fill dielectric layers 508 are deposited on top of the temporary carrier wafer 502. In various embodiments, the gap filling of the GCDs 504 includes the use of a spin-on and bake technique, other dielectric layer deposition techniques, and the like to apply the one or more gap fill dielectric layers 508. Figure 5A Figure 5B In contrast to embodiments of the GPU chiplet 106 and Figure 5B , the gap filling of the GCDs 504 includes the application of the one or more gap fill dielectric layers 508, such as by filling areas having a vertical disparity between the temporary carrier wafer 502 and the back face B of the GCDs 504 to form a planar surface. In some embodiments, when the application of the one or more gap fill dielectric layers 508 covers the back face B of the GCDs 504, the surface of the one or more gap fill dielectric layers 508 is subjected to a lapping process to expose a substrate portion of the back face B of the GCDs 504. At this point, the combination of the GCDs 504 and the one or more gap fill dielectric layers 508 constitute a reconstituted unit (or wafer, if performed on a wafer-level basis) that can be separated from the temporary carrier wafer 502.

[0040] At Figure 5C ​​At that point, a known good die for the active bridge die 510 (e.g., as previously mentioned) Figures 1 to 3 The described active bridge chip 118 is bonded to the graphics core die 504. In various implementations, such as those previously discussed... Figure 3 The described active bridge die 510 is configured to have no TSVs and is interchangeably referred to herein as a "TSV-free active bridge die" or a "TSV-free active bridge chiplet." In various embodiments, Figure 5C The operation involves bonding the front side F of the active bridge die 510 to the back side B of the graphics core die 504 (hence the term "face-to-back process" as used herein).

[0041] In addition, in some implementation schemes... Figure 5C The operation involves depositing one or more dummy silicon layers 512 on top of the patterned core die 504 and one or more existing gap-filled dielectric layers 508. See below. Figure 5D One or more dummy silicon layers 512 provide structural integrity for the reconfiguration unit after bonding to the second carrier wafer 514. The one or more dummy silicon layers 512 improve thermal performance by carrying away heat from the graphics core die 504 during operation. In other embodiments, instead of one or more dummy silicon layers 512, additional gap-filling dielectric layers are deposited.

[0042] exist Figure 5D At this point, the carrier is flipped and the temporary carrier wafer 502 is separated from the combination of the graphics core die 504, one or more gap-filling dielectric layers 508, and one or more dummy silicon layers 512. In various embodiments, Figure 5D The separation involves applying a process suitable for the technology originally used to bond the temporary carrier wafer 502 to the graphics core die 504. For example, in various embodiments, Figure 5D The separation includes thermally peeling off tape or adhesive, photo- or thermally activated adhesive peeling, etc. Additionally, a combination of the graphics core die 504, one or more gap-filling dielectric layers 508, and one or more dummy silicon layers 512 is bonded to the second carrier wafer 514, wherein the back side B of the active bridge die 510 is bonded to the second carrier wafer 514 for mechanical support. In this way, the front side F of the graphics core die 504 is exposed. Furthermore, a bumping process is completed by applying conductor bumps 516 to the front side F of the graphics core die 504 using known solder plating, pick-and-place, or printing and reflow techniques. At this stage, the actively bridge-coupled GPU chiplet is completed and ready to be mounted onto a substrate, such as... Figure 3 The circuit board 316 shown is shown.

[0043] Those skilled in the art will recognize that, despite Figures 1 to 5DDescribed herein in the specific context of a rectangular active-bridge die 118 spanning between two or three GPU dies, but various other configurations, die shapes, and different geometries in other implementations are utilized without departing from the scope of the disclosure. For example, in some implementations, the GPU dies are fabricated to include an active-bridge die at one or more corners of a square GPU die, such that multiple GPU dies are tiled together in a small-die array. Similarly, in other implementations, the GPU dies are fabricated to include an active-bridge die spanning an entire side of the GPU die, such that multiple GPU dies are strung together with intervening active-bridge dies in a long row / column configuration.

[0044] Accordingly, as discussed herein, the active-bridge die deploys single-die GPU functionality using a set of interconnected GPU dies in a manner that makes the GPU die implementation appear to the programmer model / developer as a traditional, monolithic GPU. The extensible data structure of one GPU die has access to one or more low-level caches on the active-bridge die, and nearly simultaneously to the low-level cache on its same die, thus allowing the GPU dies to maintain cache coherency without requiring an additional inter-die coherency protocol. This low-latency, inter-die cache coherency in turn enables the small-die based system to operate as a monolithic GPU from the perspective of the software developer, thus avoiding programmer or developer small-die specific considerations.

[0045] As disclosed herein, in some implementations, a method includes: bonding a first GPU die and a second GPU die to a temporary carrier wafer; bonding a front side of an active-bridge die to front sides of the first GPU die and the second GPU die, wherein the active-bridge die includes a cache memory level shared by the first GPU die and the second GPU die; and mounting the first GPU die and the second GPU die to a carrier substrate. In one aspect, bonding the first GPU die and the second GPU die to the temporary carrier wafer includes bonding the front sides of the first GPU die and the second GPU die to the temporary carrier wafer. In another aspect, the method includes: depositing one or more gap fill dielectric layers on top of the temporary carrier wafer. In another aspect, depositing one or more gap fill dielectric layers on top of the temporary carrier wafer includes forming a planar surface by filling areas having a vertical disparity between a surface of the temporary carrier wafer and back sides of the first GPU die and the second GPU die.

[0046] In one aspect, the method includes: performing a carrier flip by separating the front side of the first and second GPU dies from the temporary carrier wafer; and bonding the back side of the first and second GPU dies to a second carrier wafer. In another aspect, the method includes: etching one or more voids through the one or more gap fill dielectric layers; and filling the one or more voids with a conductive material to form a set of conductive pillars communicatively coupled to at least one of the first and second GPU dies. In yet another aspect, the set of conductive pillars includes a dielectric via. In still another aspect, the method includes: fabricating a redistribution layer structure at the back side of the active bridge die.

[0047] In one aspect, fabricating the redistribution layer structure further includes positioning a conductor structure on top of each of the set of conductive pillars. In another aspect, the method includes, after bonding the front side of the active bridge die to the front side of the first and second GPU dies, thinning the active bridge die to expose a set of through-silicon vias (TSVs) extending from the front side of the active bridge die to a back side opposite the front side of the active bridge die. In yet another aspect, mounting the first and second GPU dies includes mounting the active bridge coupled GPU die including the first and second GPU dies on a circuit board.

[0048] In some embodiments, a method of forming an active bridge coupled GPU die unit includes: bonding a first GPU die and a second GPU die to a temporary carrier wafer; bonding a front side of an active bridge die to a back side of the first and second GPU dies, wherein the active bridge die includes a cache memory level shared by the first and second GPU dies; and mounting the active bridge coupled GPU die unit including the first and second GPU dies to a carrier substrate. In one aspect, the method includes: thinning the first and second GPU dies to expose a set of through-silicon vias (TSVs) extending from a front side of the first and second GPU dies to a back side opposite the front side. In another aspect, the bonding of the first and second GPU dies to the temporary carrier wafer includes bonding front sides of the first and second GPU dies to the temporary carrier wafer.

[0049] In one aspect, the method includes depositing one or more gap fill dielectric layers on top of the temporary carrier wafer to form a planar surface by filling areas having vertical disparities between surfaces of the temporary carrier wafer and back surfaces of the first and second GPUlets. In another aspect, the method includes performing a carrier flip by separating the front surfaces of the first and second GPUlets from the temporary carrier wafer, and bonding back surfaces of the active bridgelet to a second carrier wafer. In yet another aspect, the method includes attaching one or more dummy silicon layers between the second carrier wafer and back surfaces of the first and second GPUlets. In yet another aspect, the method includes coupling one or more conductor structures to front surfaces of the first and second GPUlets.

[0050] In some embodiments, a processor is formed by a method of forming an actively bridged coupled GPUlet, the method including bonding a first GPUlet and a second GPUlet to a temporary carrier wafer, bonding a front surface of an active bridgelet to front surfaces of the first and second GPUlets, wherein the active bridgelet includes a cache memory level shared by the first and second GPUlets, and mounting the first and second GPUlets to a carrier substrate. In one aspect, bonding the first and second GPUlets to the temporary carrier wafer includes bonding the front surfaces of the first and second GPUlets to the temporary carrier wafer.

[0051] A computer readable storage medium can include any non-transitory storage medium, or combination of non-transitory storage media, accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but is not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-Ray disc), magnetic media (e.g., floppy disc, magnetic tape, or magnetic hard drive), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or Flash memory), or microelectromechanical systems (MEMS)-based storage media. The computer readable storage medium can be embedded in the computing system (e.g., system RAM or ROM), fixedly attached to the computing system (e.g., a magnetic hard drive), removably attached to the computing system (e.g., an optical disc or Universal Serial Bus (USB)-based Flash memory), or coupled to the computer system via a wired or wireless network (e.g., network accessible storage).

[0052] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of instructions stored or otherwise tangibly embodied on a non-transitory computer- readable storage medium. The software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium can include, for example, a magnetic or optical disk storage such as a compact disk or digital versatile disk, solid state storage such as a flash memory device, cache memory, random access memory (RAM) or other non-volatile storage device, or any suitable combination thereof. The executable instructions stored on the non-transitory computer-readable storage medium can be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

[0053] It should be noted that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device can not be required, and that one or more further activities can be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. Also, the concepts have been described with reference to particular embodiments. It will be apparent to one of ordinary skill in the art that a variety of modifications and changes can be made without departing from the scope of the present disclosure as set forth in the following claims. The specification and drawings should be considered in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure.

[0054] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems and any feature(s) that can cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims. Furthermore, the particular embodiments disclosed above are illustrative only as the disclosed subject matter can be modified and practiced in different but equivalent manners that are apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above can be altered or modified and all such variations are considered within the scope of the disclosed subject matter. Accordingly, the protection sought is as set forth in the following claims.

Claims

1. A method for forming an actively bridge-coupled GPU chiplet, comprising: The first GPU chiplet and the second GPU chiplet are bonded to a temporary carrier wafer; The active surface of an active bridge chiplet is bonded to the active surfaces of the first GPU chiplet and the second GPU chiplet, wherein the active bridge chiplet includes a cache memory level shared by the first GPU chiplet and the second GPU chiplet, and wherein the active surface of the active bridge chiplet is bonded to the active surfaces of the first and second GPU chiplets such that, during operation, the first and second GPU chiplets can be addressed as a single die; and The first GPU chiplet and the second GPU chiplet are mounted onto the carrier substrate.

2. The method of claim 1, wherein bonding the first GPU chiplet and the second GPU chiplet to the temporary carrier wafer comprises bonding the active surfaces of the first GPU chiplet and the second GPU chiplet to the temporary carrier wafer.

3. The method as described in any one of claims 1 or 2, further comprising: One or more gap-filling dielectric layers are deposited on top of the temporary carrier wafer.

4. The method of claim 3, wherein depositing one or more gap-filling dielectric layers on top of the temporary carrier wafer comprises forming a flat surface by filling a region having a vertical difference between the surface of the temporary carrier wafer and the surfaces of the first GPU chiplet and the second GPU chiplet opposite to the active surface.

5. The method of claim 3, further comprising: Carrier flipping is performed by separating the active surfaces of the first GPU chiplet and the second GPU chiplet from the temporary carrier wafer; as well as The surfaces of the first GPU chiplet and the second GPU chiplet opposite to the active surface are bonded to the second carrier wafer.

6. The method of claim 5, further comprising: One or more additional gap-filled dielectric layers are deposited on the second carrier wafer and the existing gap-filled dielectric layer.

7. The method of claim 6, further comprising: One or more voids are etched into the dielectric layer by filling the one or more additional gaps; as well as The one or more gaps are filled with a conductive material to form a set of conductive pillars communicatively coupled to at least one of the first GPU chiplet and the second GPU chiplet.

8. The method of claim 7, wherein the set of conductive pillars includes dielectric vias.

9. The method of claim 7, further comprising: A redistribution layer structure is fabricated on the side of the active bridge chip opposite to the active surface.

10. The method of claim 9, wherein manufacturing the redistribution layer structure further comprises positioning the conductor structure on top of each of the set of conductive pillars.

11. The method of claim 1, further comprising: After bonding the active surface of the active bridge chiplet to the active surfaces of the first GPU chiplet and the second GPU chiplet, the active bridge chiplet is thinned to expose a set of through-silicon vias (TSVs) extending from the active surface of the active bridge chiplet to a surface opposite to the active surface of the active bridge chiplet.

12. The method of claim 1, wherein mounting the first GPU chiplet and the second GPU chiplet comprises mounting the GPU chiplet, which includes the first GPU chiplet and the second GPU chiplet, onto a circuit board via an active bridge coupling.

13. A processor comprising: First GPU chiplet and second GPU chiplet; An active bridge chiplet includes an active surface bonded to an active surface of a first GPU chiplet and a second GPU chiplet, wherein the active bridge chiplet includes a cache memory level shared by the first GPU chiplet and the second GPU chiplet, and wherein the active surface of the active bridge chiplet is bonded to the active surface of the first and second GPU chipslet such that, during operation, the first and second GPU chipslet can be addressed as a single die.

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