Using charged particle multibeam lithography to create unique chips

Abstract

A method for manufacturing electronic devices using a maskless lithography exposure system, the maskless lithography exposure system using a maskless pattern writer, wherein beam steering data is generated for controlling the maskless pattern writer to expose a wafer for creating electronic devices. The beam steering data is generated based on design layout data and selection data, the design layout data defining a plurality of structures (e.g., vias) applicable to electronic devices to be manufactured from the wafer, the selection data defining which structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, and the selection data defining different sets of structures for different subsets of electronic devices. Exposure of the wafer according to the beam steering data results in exposing patterns having different sets of structures for different subsets of electronic devices.

Description

[0001] This application is a divisional application of a patent application with an international application date of September 8, 2017, an international application number of PCT / JP2017 / 033371, a national application number of 201780068908.8, and an invention name of “Manufacturing unique chips using a charged particle multi-beam lithography system”. Technical Field

[0002] The present invention relates to a manufacturing method, i.e. a method for manufacturing electronic devices such as semiconductor chips. More specifically, the present invention relates to the use of a charged particle multi-beam lithography machine to manufacture unique chips, wherein the uniqueness of the chip is defined by structures on the chip (such as via structures). Therefore, the present invention also relates to unique chips produced using this new manufacturing method, as well as so-called "foundries", i.e. manufacturing facilities that apply this new method, and maskless lithography exposure systems suitable for performing the improved manufacturing method. The present invention further relates to a computer-implemented method for generating beam control data, which is used to control a maskless pattern writer to expose wafers for creating electronic devices. The present invention also relates to a computer-implemented method for generating selection data used in the generation of beam control data. The present invention further relates to a data processing system, a computer program product and a computer-readable storage medium related to the computer-implemented method. Background Art

[0003] In the semiconductor industry, photolithography systems are used to create, i.e., manufacture, such electronic devices, typically in the form of integrated circuits formed on silicon wafers, commonly referred to as semiconductor chips. As part of the manufacturing process, photolithography utilizes a reusable optical mask to project an image of a pattern representing a desired circuit structure onto a silicon wafer. The mask is reused to image the same circuit structure on different portions of the silicon wafer and on subsequent wafers, resulting in a series of identical chips manufactured using each wafer, each chip having the same circuit design.

[0004] Nowadays, various technologies related to data security, traceability and anti-counterfeiting have created a growing demand for unique chips with unique circuits or codes or other unique hardware features for chip diversification. Such unique chips are known and often implement security-related operations in an obscure way that requires the chip to be truly unique. Known unique chips are usually implemented after the manufacture of the chip, for example by manufacturing a series of identical chips using mask-based lithography and then destroying certain connections in the chip after manufacturing, or by evaluating the uniqueness of the chip after checking and controlling certain features. The masks used in this process are expensive to produce, and it is obviously too expensive to manufacture unique masks for each single chip, so mask-based lithography is considered unsuitable for manufacturing unique chips.

[0005] Therefore, it has been proposed to create unique chips using maskless lithography. For maskless lithography, no mask is used, but the desired pattern representing the circuit design is input to the maskless lithography system in the form of a data file (e.g., a GDSII or OASIS file containing a circuit design layout to be transferred to a target (e.g., a wafer)) to be exposed by the maskless lithography system.

[0006] In WO 2010 / 134026, a maskless lithography and data input system is disclosed in the name of the applicant of the present invention. WO 2010 / 134026 is incorporated herein by reference in its entirety. The disclosed maskless system uses a charged particle beam wave such as an electron beam wave to directly write a pattern onto a wafer. Because the desired pattern for exposing each chip is represented as data rather than a mask, such a system can be used to manufacture unique chips. By using a different GDSII input file for each unique electronic device to be created, the pattern data (representing the unique electronic device or chip to be created) input to the exposure system can be made unique.

[0007] WO 2011 / 117253 and WO 2011 / 051301 (both assigned to the applicant of the present invention and incorporated herein by reference in their entirety) disclose various examples of electronic devices or chips that may be created using a charged particle lithography system.

[0008] However, a direct method of creating a secure (at least unique) device (i.e., using a known maskless exposure system) may not be optimal but is at least suitable for securely producing unique electronic devices. Disadvantageously, the processing of the GDSII or OASIS files associated therewith is typically performed outside the operation of the operator of the lithography system. In addition, the processed GSDII / OASIS files can be used and stored for longer periods of time. According to the insights of the basic and practical parts of the present invention, for security reasons, it is desirable to minimize the exposure and exposure time of unique via design data used to create a unique electronic device or chip, because the uniqueness of the electronic device or chip is typically used for data security, traceability and anti-counterfeiting applications. Summary of the invention

[0009] The present invention provides a solution for manufacturing unique electronic circuits by implementing different structures in different chips, where the common exposure of specific structures used in creating the chip can be minimized. Non-limiting examples of such structures are connections between metal layers (also called vias), connections between metal layers and gates (e.g., in contact layers), connections in local interconnect layers, and P or N injections of certain parts of transistors or diodes. One way to make a chip unique is by implementing different structures in different chips. For example, the number of vias and the location of the vias can be different for each chip. The different paths generated by the vias cause the same data input to be presented to the chip, thereby generating different data outputs for each chip. At this point, for a specific portion of the layout of an electronic device, selection data can be provided to define which vias are enabled in the chip, thereby generating personalized areas in the chip.

[0010] All possible structures from which to select to personalize a chip or a batch of chips can be part of a generic design layout data (e.g., a GDSII or OASIS file). The locations of selectable structures can be provided as location metadata. Specific portions can be personalized by implementing different sets of structures for different subsets of electronic devices based on the location metadata and selection data. The selection of structures can be performed at a post-processing stage close to or within a maskless lithography exposure system, thereby minimizing the shared exposure of specific structures used to personalize electronic devices.

[0011] Where maskless lithography processes are used to form non-shared structures such as connections between metal layers, these may be formed by merging two conductive vias to form a double via.

[0012] According to one aspect of the present invention, a method for manufacturing electronic devices using a maskless lithography exposure system is provided. The maskless lithography exposure system may use a maskless pattern writer. The method may include generating beam control data for controlling the maskless pattern writer to expose a wafer for creating an electronic device. The beam control data may be generated based on design layout data, which defines multiple structures for electronic devices to be manufactured from the wafer. The beam control data may be further generated based on selection data, which defines which structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, and the selection data defines different sets of structures for different subsets of electronic devices. Exposure of the wafer according to the beam control data may result in exposing patterns having different sets of structures for different subsets of electronic devices.

[0013] According to one aspect of the present invention, a computer-implemented method for generating beam steering data is provided. The beam steering data can be used to control a maskless pattern writer to expose a wafer for creating electronic devices using a maskless lithography exposure system, and the maskless lithography exposure system uses a maskless pattern writer so that exposure of the wafer according to the beam steering data results in exposing patterns with different sets of structures for different subsets of electronic devices. The method may include receiving design layout data, the design layout data defining a plurality of structures for electronic devices to be manufactured from the wafer. The method may further include receiving selection data, the selection data defining which structures of the design layout data are applicable to each electronic device to be manufactured from the wafer. The selection data may define different sets of structures for different subsets of electronic devices. The method may further include generating beam steering data based on the received design layout data and the received selection data.

[0014] The maskless pattern writer may be a raster scan based maskless pattern writer, in which case the beam steering data may be in the form of pattern bitmap data. The maskless pattern writer may be a vector scan based maskless pattern writer, in which case the beam steering data may be formatted in a manner suitable for vector scanning.

[0015] Electronic devices can be personalized or made unique by enabling different sets of structures, such as by creating different vias in each electronic device.

[0016] Advantageously, the method enables the creation of personalized regions of electronic devices to be kept within the operation of a maskless lithography exposure system and the shared exposure time of the design data for the personalized regions to be minimized. A favorable side effect is that the required processing power and memory may be kept low because the design layout data may be reused to create multiple chips, where known methods of creating unique chips require design layout data for each unique chip and therefore require capacity and processing time for each unique chip design to be manufactured.

[0017] In an embodiment, the design layout data may include common design layout data, which defines structures applicable to all electronic devices. The design layout data may further include non-common design layout data, which defines structures applicable to certain electronic devices, and the different sets of structures can be selected from the structures applicable to certain electronic devices according to the selection data. Therefore, the structures can be located in the common part and the personalized area of ​​the electronic device.

[0018] In an embodiment, the selection data may specify, for each electronic device, whether the beam steering data includes or excludes data defining one or more structures defined in the design layout data.

[0019] The selection data may use a single bit to specify that individual ones of the structures defined in the design layout data are to be included or excluded from the beam steering data. Advantageously, this minimizes the size of the selection data.

[0020] The beam steering data may include bitmap data representing a selected subset of structures defined in the design layout data, and may not include bitmap data representing non-selected ones of the structures defined in the design layout data.

[0021] The selected subset of structures may include structures indicated for selection in the selection data, and non-selected ones of the structures may include structures not indicated for selection in the selection data.

[0022] Each region may generate beam steering data once.

[0023] In an embodiment, the design layout data only includes design layout data defining structures that can be selected according to the selection data. In this case, optical lithography can be applied in combination with maskless lithography, where the common parts of the electronic device are created using lithography. The personalized areas of the electronic device are then created as described above.

[0024] In an embodiment, the method may further include receiving the design layout data via a first network path, and receiving the selection data via a second network path separate from the first network path. This enables the design layout data and the selection data to be provided from different sources. Typically, the selection data will be received from a source external to the maskless lithography exposure system (e.g., from a black box device within a manufacturing portion of a foundry).

[0025] As the design layout data (e.g., in the form of a GDSII or OASIS data file) generally involves a large amount of data, while the selection data may be in the form of a relatively small file, the first network path may have a higher data transmission bandwidth than the second network path. For example, the first network path is based on a fiber optic network connection. For example, the second network path is based on a cat 6 Ethernet network connection.

[0026] In an embodiment, the step of generating beam steering data may also be based on position metadata. The position metadata may specify the location of structures defined in the design layout data. Thus, the position metadata identifies the location of structures in the design layout, while the selection data identifies which structures are to be included in the beam steering data used to create the electronic device. Advantageously, the selection data and position metadata are typically smaller in size than the design layout data, enabling the position metadata and selection data to be provided to the maskless lithography exposure system using a relatively low bandwidth and low cost network connection (e.g., based on cat 6 Ethernet).

[0027] In an embodiment, one or more structures defined in the design layout data may be selected to be included in the beam steering data based on both the position metadata and the selection data.

[0028] The design layout data may include position metadata. Thus, the position metadata may be received in a maskless lithography exposure system together with the design layout data. The position metadata may be embedded with the design layout data or received as a separate file.

[0029] Alternatively, the position metadata may be received separately from the design layout data. Thus, the position metadata may be received via different network routes and / or addressed to different subsystems of the maskless lithography exposure system. The position metadata may be received together with the selection data.

[0030] The selection data may be received in an encrypted form to provide additional data security within the foundry during the creation of a unique electronic device.

[0031] Beam steering data can be encrypted to provide additional data security within the foundry during the creation of unique electronic devices.

[0032] In an embodiment, the method may further include generating erase mask data based on the position metadata and the selection data. The generation of the beam steering data may include merging the erase mask data with the design layout data or a derivative of the design layout data to delete non-selected structures from the design layout data.

[0033] In an embodiment, the electronic device may be a semiconductor chip.The maskless pattern writer may be a charged particle multibeam lithography machine or an electron beam machine.

[0034] According to one aspect of the present invention, an electronic device such as a semiconductor chip created using one or more of the above methods is provided.

[0035] In embodiments, the electronic device may be a truly unique semiconductor chip that is different (eg, functionally different) from any other semiconductor chip using the method of the present invention.

[0036] In an embodiment, the structure comprises at least one of: a connection between metal layers, also called a via; a connection between a metal layer and a gate in a contact layer; a connection in a local interconnect layer; a P or N implantation of parts of a transistor or a diode.

[0037] According to one aspect of the present invention, a maskless lithography exposure system configured to perform one or more of the above methods is provided.

[0038] In an embodiment, a maskless lithography exposure system may include a black box device configured to generate selection data defining which structures of the design layout data are applicable to each electronic device to be fabricated from the wafer, the selection data defining different sets of structures for different subsets of the electronic devices.

[0039] The black box may be owned by a third party, such as the owner of the IP block or the owner of the manufactured chip, or the key management infrastructure owner. Advantageously, the black box may be located within the foundry close to the lithography machine operations, thereby minimizing public exposure of the selected data. This contrasts with known chip manufacturing solutions, where the black box for personalized chips is typically located outside the foundry and is used to personalize the chip after creation.

[0040] According to one aspect of the present invention, there is provided a semiconductor manufacturing apparatus including the maskless lithography exposure system as described above.

[0041] According to one aspect of the present invention, a lithography subsystem is proposed that includes a rasterizer and uses a maskless pattern writer (such as a charged particle multibeam lithography machine or an electron beam machine). The rasterizer can be configured to generate beam control data for controlling the maskless pattern writer to expose a wafer for creating electronic devices. The beam control data can be generated based on design layout data, which defines multiple via structures for electronic devices to be manufactured from the wafer. The beam control data can be further generated based on selection data, which defines which structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, and the selection data defines different sets of structures for different subsets of electronic devices. Exposure of the wafer according to the beam control data can result in exposing patterns with different sets of via structures for different subsets of electronic devices.

[0042] In an embodiment, the rasterizer may be configured to receive pattern vector data in a lithography subsystem specific format (e.g., based on an OASIS file format) generated from design layout data. The rasterizer may be further configured to receive selection data. The rasterizer may be further configured to receive position metadata that specifies the position of each of the structures defined in the design layout data and selectable according to the selection data. The rasterizer may be further configured to process the pattern vector data, the common via metadata, and the unique via metadata to obtain beam steering data.

[0043] According to one aspect of the present invention, an electronic device is provided that can be created using the above-described lithography subsystem.

[0044] In embodiments, the electronic device may be a truly unique semiconductor chip that is different from any other semiconductor chip created.

[0045] According to one aspect of the present invention, an electronic device that may include a semiconductor chip is provided. The semiconductor chip may include a plurality of structures formed in three or more layers of the semiconductor chip. The semiconductor chip may be a member of a set of semiconductor chips, each semiconductor chip in the set of semiconductor chips having a set of common structures and a set of non-common structures, the set of common structures being present in all semiconductor chips in the set of semiconductor chips, and the set of non-common structures being present only in a subset of the semiconductor set. The non-common structures may be formed at least on a first layer of a layer having a second layer of a layer above the first layer and having a third layer of a layer below the first layer.

[0046] According to one aspect of the present invention, an electronic device that may include a semiconductor chip is proposed. The semiconductor chip may include multiple structures formed in multiple layers of the semiconductor chip. The semiconductor chip may be a component of a collection of semiconductor chips, each semiconductor chip in the collection of semiconductor chips having a set of common structures and a set of non-common structures, the set of common structures being present in all of the semiconductor chips in the collection, and the set of non-common structures being present only in a subset of the semiconductor chips in the collection. The non-common structures may include at least one of the following items: connections between metal layers of multiple layers; connections between metal layers of multiple layers and gates in contact layers; connections in local interconnect layers of multiple layers; and P or N doped diffusion regions of transistors or diodes in one of the multiple layers.

[0047] In an embodiment, shared structures and non-shared structures of a semiconductor chip may be interconnected to form an electronic circuit.

[0048] In an embodiment, the electronic device may include at least one input terminal for receiving a stimulus and at least one output terminal for outputting a response. The electronic circuit may form a stimulus-response circuit connected to the at least one input terminal and the at least one output terminal. The stimulus-response circuit may be adapted to generate a response at the at least one output terminal based on a stimulus applied to the at least one input terminal, the stimulus and the response having a predetermined relationship.

[0049] According to one aspect of the present invention, a data processing system is provided, comprising a processor, wherein the processor is configured to execute a method for generating beam steering data of one or more of the above embodiments.

[0050] According to one aspect of the present invention, a computer program product implemented on a computer-readable non-volatile storage medium is proposed, comprising instructions. When the computer program product is executed by a computer, the instructions cause the computer to execute a method for generating beam steering data of one or more of the above-mentioned embodiments.

[0051] According to one aspect of the present invention, a computer-readable non-transitory storage medium is provided, comprising instructions, which, when executed by a computer, enable the computer to execute a method for generating beam steering data of one or more of the above-mentioned embodiments.

[0052] According to one aspect of the present invention, a computer-implemented method for generating selection data is provided. The selection data may define structures of design layout data applicable to electronic devices to be manufactured from a wafer. The method may include generating the selection data by defining which structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, such that the selection data defines different sets of structures for different subsets of the electronic devices.

[0053] In an embodiment, the generating of the selection data may further include defining a location of each of the structures within a design layout of the electronic device defined by the design layout data.

[0054] In an embodiment, the method may further comprise encrypting the selection data.

[0055] According to one aspect of the present invention, a data processing system is provided, comprising a processor, wherein the processor is configured to execute a method for generating selection data of one or more of the above embodiments.

[0056] According to one aspect of the present invention, a computer program product implemented on a computer-readable non-volatile storage medium is proposed, comprising instructions. When the computer program product is executed by a computer, the instructions cause the computer to execute a method for generating selection data of one or more of the above-mentioned embodiments.

[0057] According to one aspect of the present invention, a computer-readable non-transitory storage medium is provided, comprising instructions, which, when executed by a computer, cause the computer to execute a method for generating selection data of one or more of the above-mentioned embodiments.

[0058] Various aspects and embodiments of the invention are further defined in the following description and claims.

[0059] Hereinafter, embodiments of the present invention will be described in more detail. However, it should be understood that these embodiments should not be construed as limiting the scope of protection of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference numerals indicate corresponding parts, and in which:

[0061] Figure 1 A simplified unique chip and a wafer having multiple unique chips of an exemplary embodiment of the present invention are shown;

[0062] Figure 2 A schematic diagram showing a system involved in the manufacture of an electronic device according to an exemplary embodiment of the present invention;

[0063] Figure 3 A functional flow chart illustrating the creation of pattern bitmap data of an exemplary embodiment of the present invention;

[0064] Figure 4 represents a region defined by design layout data and via location metadata according to an exemplary embodiment of the present invention;

[0065] Figure 5 represents selection data according to an exemplary embodiment of the present invention;

[0066] Figure 6 A functional flow chart showing the creation of pattern bitmap data using an erase bitmap according to an exemplary embodiment of the present invention is shown;

[0067] Figure 7 shows a process of creating a via according to an exemplary embodiment of the present invention;

[0068] Figure 8 A simplified schematic diagram showing an exemplary embodiment of a charged particle multibeam lithography system;

[0069] Fig. 9 is a conceptual diagram illustrating an exemplary maskless lithography system;

[0070] Fig. 10A shows a side view of two merged vias between metal layers of an exemplary embodiment of the present invention;

[0071] Fig. 10B A top view of two merged vias between metal layers of an exemplary embodiment of the present invention is shown;

[0072] Fig.11A A side view showing two vias between metal layers; and

[0073] Fig. 11B A top view of two vias between metal layers is shown.

[0074] The drawings are for illustration purposes only and are not intended to be limiting of the scope or protection provided by the claims. DETAILED DESCRIPTION

[0075] Reference is made to semiconductor chips in the following examples, but it should be understood that the present invention is not limited to chips and applies more generally to the creation of electronic devices with personalized (e.g., unique) features. The electronic device may be a read-only memory (ROM). For example, batches of chips with personalized ROM loads may be created using the present invention. These batches are typically small batches (e.g., created from one or less than one wafer).

[0076] The process performed by charged particle multi-beam lithography is also called electron beam exposure. The electron beam exposure method is a maskless exposure method. The electron beam used to write to a target such as a wafer during electron beam exposure is also called a beam wave.

[0077] The unique chip is designed to be unique relative to other chips. This does not exclude the possibility that more than one unique chip can be manufactured using the present invention, for example, to create a spare unique chip to be used in the event that the original unique chip is damaged, or to create batches of identical chips for any other reason. A unique semiconductor chip that is functionally different from any other semiconductor chip can be referred to as a truly unique chip. Creating a visually readable unique ID on the chip can also be considered as creating a unique chip. Copies of a unique chip can be made by repeatedly creating the chip on different wafers, or a single wafer can include one or more copies of a unique chip.

[0078] Figure 1 An exemplary simplified unique chip 100 is shown that includes a common portion 101 and a personalized region 102. The common portion 101 can be replicated in other chips created on the wafer 24, resulting in multiple chips having the same identical portion. The personalized region 102 can be different from other chips created on the wafer 24. This Figure 1 1 , wherein the wafer 24 shown contains a unique chip 100 and 39 other unique chips, each having a different personalized area. The combined common portion 101 and the personalized area 102 can form the unique chip 100.

[0079] The personalization area 102 can be implemented by selecting and writing a specific structure, such as in Figure 1 Other unique chips may have different structures, such as vias leading to the realization of different interconnections within or between layers of the electronic circuit.

[0080] As an alternative or in addition to specific vias, other connections between metal layers, connections between metal layers and gates (e.g., in contact layers), connections in local interconnect layers, and / or the presence or absence or structure of diffusion regions (e.g., P or N doped regions) of transistors or diodes may be selected and written to implement personalized region 102.

[0081] The common portion 101 may be created using photolithography, but preferably charged particle multibeam lithography is used to create the common portion 101. The personalization areas are typically created using charged particle multibeam lithography.

[0082] Figure 2 A semiconductor manufacturing apparatus 1000 of an exemplary embodiment of the present invention is shown, which includes systems and processes involved in manufacturing a unique semiconductor chip. Figure 2 If reference numerals used in the figure refer to a process or operation, then these reference numerals may also refer to the computing unit that performs the process or operation. Each process and operation shown may be performed by a dedicated unit. Alternatively, a computing unit may perform Figure 2 For example, a computing unit is a computer system including one or more processors and memory for running dedicated tasks or for running programs under an operating system.

[0083] The semiconductor manufacturing equipment 1000 may include a production setup section 1002 and a manufacturing section 1003. The two sections 1002 and 1003 may not be divided or another division may be made. The manufacturing section 1003 may include one or more lithography subsystems 1070, each of which uses a maskless pattern writer 1073. In this example, the maskless lithography exposure system is a charged particle multi-beam lithography system, and the maskless pattern writer 1073 is a charged particle multi-beam lithography machine or an electron beam machine.

[0084] exist Figure 2 2, a standard IC design flow 1001 is shown, which typically results in the creation of mask order data, design layout data, and / or wafer order data, collectively depicted as output 2000. The design layout data is typically generated in a GDSII or OASIS data format. The standard IC design flow is known in the art and typically includes a system / full IC design phase 1010, a circuit design VHL / Verilog phase 1011, a logic verification phase 1012, a placement and routing (P&R) phase 1013, a physical simulation phase 1014, and / or a design rule check (DRC) phase 1015.

[0085] The process design kit 1030 including additional components and IP libraries may provide building blocks in the form of reusable units of logic, cells, or chip layout design from a functional IP block storage 1031 to various steps in the standard IC design flow 1001, as indicated by arrows from the functional IP block storage 1031 to steps 1011, 1012, 1013, 1014, and 1015 of the standard IC design flow 1001. The process design kit 1030 is typically located within the production setup portion 1002 of the foundry 1000, as it may involve licensing functional IP blocks from an IP block designer 1005 to a chip manufacturer.

[0086] The created design layout data typically includes a common design layout portion defining layout structures, which may include via structures applicable to all chips to be created. In addition, the design layout data may include a non-common design layout portion, which defines structures such as via structures applicable to certain electronic devices, from which different sets of structures can be selected to make the chip unique. The distinction between observing the design layout data, the common design layout portion and the non-common design layout portion is preferably not obvious. In order to enable the selection of a set of structures from the non-common design layout portion, position metadata can be generated together with the design layout data.

[0087] In the following examples, the selectable structure is a via structure, and the location metadata is referred to as via location metadata.

[0088] The via location metadata may provide the location within the design layout for each selectable via. The via location metadata may be stored within the design layout data, but is preferably provided as a separate data file.

[0089] The output 2000 of the design flow 1001 may be provided to a charged particle multibeam lithography system via a tape-out and sign-off process 1016. More specifically, the output 2000 may be input to a preparation portion 1020 of a production setup 1002, where optical proximity correction (OPC) operations 1021, data preparation (PEC, fracturing) operations 1022, recipe / processor (PP) generation operations 1023, and / or order and production planning operations 1024 may be performed. The output of each of these operations may be transferred to a manufacturing portion 1003 via a verification step 1040.

[0090] If lithography exposure is to be performed on the wafer prior to maskless lithography exposure, optical proximity correction (OPC) 1021 may be applied to the GDSII design layout data, resulting in corrected GDSII data 2010, which may be input into the mask shop 1081 together with the mask order data. This may result in a mask set 2011 being input into a reticle stacker 1082, from which a reticle (mask) 2012 may be input into a CMOS wafer flow 1080. The wafer order data may be used to cause a wafer 1083 to be input into a CMOS wafer flow 1080 when required. The lithography exposure itself is not performed in the CMOS wafer flow 1080. Figure 2 The resulting exposed wafer is shown as wafer 2013. Note that if photolithography exposure is not performed, wafer 2013 may be an unexposed wafer.

[0091] The data preparation unit 1022 may pre-process the GDSII design layout data depicted as 2007 into pre-processed design layout data 2008. The pre-processed design layout data 2008 may include data specific to the lithography subsystem 1070. This off-line pre-processing of the GDSII data 2007 may include steps such as planarization, proximity correction, resist heating correction, and / or drawing of smart boundaries. The pattern vector data 2008 may be stored in a mask storage device 1051 of a manufacturing execution system (MES) 1050.

[0092] The recipe / PP generation 1023 may generate instructions for creating a process job (PJ). The PP and associated programs may be stored in a recipe / PP database 1052 of the MES 1050. The PP 2005 may be sent from the MES 1050 to the machine control 1072 of the lithography subsystem 1070 to instruct the machine control 1072 to create a PJ based on the PP. Additional commands may include terminate and cancel instructions.

[0093] For example, via the order and production plan 1024, a manufacturing database 1053 of the MES 1050 may be provided with manufacturing specific information. From here the information may be fed to a PJ input generator 1054. The PJ input generator 1054 may provide the PJ input to the machine control 1072, where a PJ 2006 may be generated for controlling portions of the lithography subsystem 1070, particularly the rasterizer 1071 and the pattern streamer (maskless pattern writer) 1073.

[0094] The PP can be used to control the operation of the lithography subsystem 1070, which can include a series of actions to be performed. The machine control 1072 can load the PP, and can schedule and execute the PP as requested by the option / PP generation 1023. The PP can play the role of an option (e.g., as defined in the SEMI E40 standard). Although the SEMI standards specify many requirements on how to handle options, the standards can be contradictory, so it is preferred to avoid options. Instead, editable and unformatted PPs can be used in the form of so-called binary large objects (BLOBs).

[0095] A PP may be a pre-planned and reusable portion of a set of instructions, settings and / or parameters that may determine the processing environment for a wafer and may undergo changes between runs or processing cycles. A PP may be designed by a lithography tool designer or may be generated by the tool.

[0096] A PP may be uploaded to the lithography system by a user. A PP may be used to create a PJ. A PJ may specify the processing applied to a wafer or set of wafers by the lithography subsystem 1070. A PJ may define which PP to use when processing a specified set of wafers, and may include parameters from the PP (and optionally from the user). A PJ may be a system activity initiated by a user or a host system.

[0097] The PP can be used not only to control the processing of wafers, but also for service actions, calibration functions, lithography component testing, modifying component settings, updating and / or upgrading software. Preferably, no subsystem behavior occurs other than that specified in the PP, except for certain allowed additional categories, such as automatic initialization during module or subsystem power-up, periodic and unconditional behavior of subsystems, as long as those do not affect PJ execution and response to unexpected power failure, emergency or EMO activation.

[0098] A PP can be divided into several steps. Most steps usually include commands and identify the subsystems to execute the commands. Steps can also include parameters to be used when executing the commands and parameter constraints. A PP can also include scheduling parameters to indicate when the steps are to be executed, for example, in parallel, sequentially, or synchronously.

[0099] To execute the command steps of the PJ, the machine control 1072 may send the commands indicated in the PJ to the subsystems indicated in the associated steps of the PJ. The machine control 1072 may monitor the timing and may receive results from the subsystems.

[0100] The pre-processed design layout data 2008 is typically stored in a reticle storage device 1051 in a tool input data format, which is a vector format and includes dose information. The pre-processed design layout data 2008 can be provided from the reticle storage device 1051 to the rasterizer 1071 of the lithography subsystem 1070, where it can be processed into beam control data (such as pattern bitmap data 2009) for controlling the maskless pattern writer 1073 to expose the wafer for creating the chip. The pre-processed design layout data 2008 can include all possible structures (via structures in this example) from which to select for creating a unique chip. The selection can be based on input from a secure foundry black box device 1060, which can generate selection data, the selection data defining which via structures in the layout data are applicable to each wafer to be manufactured from the wafer, and the selection data defining different sets of via structures for different subsets of chips.

[0101] You can Figure 2 The selection data shown as 2004 in FIG. 1 is provided from the black box device 1060 to the PJ input generator 1054. Preferably, the selection data 2004 is encrypted. The PJ input generator 1054 can send the selection data 2004 to the machine control 1072, where the machine control 1072 can generate a PJ 2006 instructing the rasterizer 1071 to generate pattern bitmap data 2009 based on the selection data 2004.

[0102] Alternatively, the black box apparatus 1060 may be configured to provide the selection data 2004 directly to the lithography subsystem 1070 for providing the selection data 2004 to the rasterizer 1071 without involving the PJ input generator 1054 .

[0103] When the pre-processed design layout data 2008 does not include via location metadata, and thus the locations of selectable vias cannot be derived from the pre-processed design layout data 2008, the rasterizer may also receive via location metadata 2003, typically with the selection data but possibly as a separate file.

[0104] The via location metadata 2003 may be received along with the GDSII design layout data in the preparation section 1020. From there the via location metadata 2003 may be provided to the black box device 1060 (e.g., via the recipe / PP generator 1023 or via the order and production plan 1024). Figure 2 , where via location metadata 2003 follows a path from order and production plan 1024 to black box device 1060 via manufacturing database 2003 .

[0105] The black box 1060 may provide the via location metadata 2003 to the lithography subsystem 1070 following the same path as the selection data described above (eg, via the PJ input generator 1054 or directly to the lithography subsystem 1070 ).

[0106] The black box device 1060 may be configured to provide only a subset of the via location metadata 2003 (eg, including only location information of vias to be enabled according to the provided selection data 2004 ) to the lithography subsystem 1070 .

[0107] The black box device 1060 may include an ID / key manager 1061 and a selection data generator 1062, which cooperate in creating the selection data 2004. The ID / key manager 1061 may receive product ID / serial number information 2001 from the manufacturing database 1053, and may receive batch ID / key pairs 2002 from a key manager service 1006 that may be located outside the maskless lithography exposure system. The product ID / serial number information 2001 and the batch ID / key pairs 2002 may be used to control the generation of the selection data 2004. In addition, the product ID / serial number information 2001 may be used to track the chip through the creation process so that the chip can be matched with its ID / serial number after creation. Alternatively or additionally, the product ID / serial number information 2001 may be used to include an ID / serial number in or on the chip by a process not shown but known per se.

[0108] Exposing the wafer 2013 according to the pattern bitmap data 2009 may result in exposing patterns having different sets of via structures for different subsets of chips. Figure 2 , this is depicted as exposed wafer 2014. The exposed wafer 2014 can be further processed according to a standard CMOS wafer flow 1080, typically including inspection, etching, deposition CMP and / or slicing steps. The resulting sliced ​​chip 1007 can be a unique chip used for data security, traceability and / or anti-counterfeiting applications (e.g., in an end-user device 1008). Arrow 215 depicts providing the unique chip to the end-user device 1008.

[0109] Process procedures (PP) and process jobs (PJ) can be based on SEMI standards, such as SEMI E30: "Generic Model (GEM) for Manufacturing Equipment Communication and Control"; SEMI E40: "Process Management Standard"; SEMI E42: "Option Management Standard: Concepts, Behaviors, and Message Services"; and / or SEMI E139: "Specification for Option and Parameter Management (RaP)".

[0110] Figure 3An exemplary functional flow diagram illustrating a data path using solid line rasterization that may be followed when generating pattern bitmap data 2009 from GDSII design layout data 2007 is shown. Figure 3 The functional flow can be used in Figure 2 In the maskless lithography exposure system. Figure 3 , the functional flow chart is divided into four parts: 3010 is used to indicate the data format of the basic data output / input; 3020 shows the processing flow including data output / input (parallelogram) and functional elements (rectangles); 3030 is used to indicate the processing steps performed on the overlying functional elements; and 3040 is used to indicate the frequency at which the processing steps are typically performed (for example, once per design 3041, once per wafer 3042, or once per area 3043); Roman numerals I, II, and III indicate when via location metadata and / or selection data can be provided to the data path.

[0111] The input to the process may be GDSII design layout data 2007, or a design layout in any other suitable format (eg, OASIS data format). The GDSII design layout data 2007 may include structures (eg, via structures) from which a set of via structures are selected to make the chip unique.

[0112] The data preparation unit 1022 may pre-process the GDSII file 2007, typically as an off-line pre-processing operation. The pre-processing operation typically includes one or more of planarization, proximity correction, resist heating correction, and / or drawing of smart boundary operations, collectively depicted as 3031. The output of the data preparation 1022 may be pre-processed design layout data 2008, typically in a vector format including dose information (depicted as 3011). The format of the pre-processed design layout data 2008 is also referred to as a tool input data format. The data preparation 1022 is typically performed once per design depicted by arrow 3041, but may be performed once per wafer or once per region.

[0113] Pre-processing at the data preparation unit 1022 preferably does not expose specific or unique chip designs, i.e., the selection data 2004 is preferably not available at this stage in the data path, advantageously allowing the data preparation unit 1022 and the production setup portion 1002 of the foundry to be located in a less secure environment.

[0114] As described above, for security reasons, it is desirable to minimize the exposure and exposure time of specific or unique chip design portions. The security aspect is important because the uniqueness of the chip is often used for data security, traceability, and / or anti-counterfeiting applications. The processes within the dashed block (i.e., from software processing 1071A to hardware processing at pattern writer 1073) are typically performed within the lithography subsystem 1070, which enables a safer operating environment. In addition, by providing selection data 2004 only at or after software processing 1071A, the amount of time that the unique features of the chip are used within the manufacturing portion 1003 of the foundry can be minimized.

[0115] Typically the selection data 2004 is provided and used once per region. The Roman numeral III indicates that the selection data 2004 is provided to the data path at this stage. Alternatively, but less preferably, the selection data 2004 may be provided and used once per wafer. The Roman numeral II indicates that the selection data 2004 is provided to the data path at this stage.

[0116] The position metadata 2003 may be provided to the lithography subsystem 1070 along with the selection data 2004, such as Figure 2 Alternatively, as indicated by Roman numeral I, if the selection data is embedded with GDSII design layout data, the location metadata may be provided once per design.

[0117] The pre-processed GDSII design layout data 2008 may be input to a rasterizer 1071, which may include, for example, Figure 3 The software processing portion 1071A and the streaming portion 1071B are shown. Depending on whether the selection data 2004 is used once per wafer as depicted by Roman numeral II or once per region as depicted by Roman numeral III, the software processing portion 1071A or the streaming portion 1071B can use the selection data 2004 with the via location metadata 2003 so that a specific set of via structures is defined by the selection data 2004 in the pre-processed design layout data, thereby preparing to create a unique chip.

[0118] Inline processing of the pre-processed design layout data 2008 may be performed at the software processing portion 1071A to rasterize vector data to generate pattern system stream (PSS) data 3021. The PSS data 3021 may be formatted as 4-bit grayscale bitmap data depicted as 3012.

[0119] Rasterization can be performed. A unique chip design portion can be implemented at this stage, as indicated by Roman numeral II. The streaming portion 1071B can then process the PSS data 3021 to generate pattern bitmap data 2009. The processes performed by the streaming portion 1071B can include corrections involving all or part of the pixel shift in the X and / or Y directions for beam position calibration, region size adjustment and / or region position adjustment on the bitmap data. These processes are collectively described as 3032. As an alternative to entry point II, a unique design portion can be implemented at this stage, as indicated by Roman numeral III. The pattern bitmap data 2009 can be streamed to a pattern writer 1073 for exposure of the wafer. This streaming of the pattern bitmap data 2009 is depicted as 3022.

[0120] Rasterization may be performed in the streaming stage 1071B, which may involve real-time processing performed in hardware. Corrections for beam position calibration, region size adjustment, and / or region position adjustment (depicted collectively as 3032) may be performed on the vector format PSS format data 3021, which rasterization may then convert into pattern bitmap data. When corrections are performed on the vector data, full pixel shifts, partial pixel shifts in the X and Y directions, and / or sub-pixel shifts may be performed.

[0121] The control of the maskless pattern writer 1073 typically involves a blanker controlled by pattern bitmap data. The pattern bitmap data 2009 may also be referred to as blanking format data.

[0122] Figure 4 and Figure 5 Concerning an exemplary scenario, beam steering data (such as image bitmap data) is generated once per region. Figure 4 An exemplary embodiment of a region 103 defined by design layout data and location metadata 2003 (eg, via location metadata) is shown. Figure 4 , Figure 5 2004. In this example, the design layout data defines four unique chips within the region, each chip having a common portion 101, which may be the same in all four chips, and a region 102 to be personalized, which may be different in each chip after selecting a set of different structures (e.g., vias) from the selectable structures defined in the design layout data.

[0123] In this example, the Roman numerals I, II, and III indicate when the corresponding data can be provided to Figure 3 data path.

[0124] The via location metadata 2003 may contain a list of selectable vias and the coordinates of each selectable via within the design layout. In this example, the vias are numbered Via1 to ViaN, where N is any positive index number. It will be appreciated that any other identification of the vias may be used instead, or the location of the X,Y coordinates within the file (e.g., counting the line number) may be used as the identification of the vias and the identification of the vias may be omitted entirely. In this example, the coordinates of each via are expressed as an X,Y location. It will be appreciated that any other coordination system or indication of location within the design layout may be used instead. Similar to Figure 4 For example, any other structure that replaces the via structure can be identified using the position metadata.

[0125] In addition to the location of the structure, the location metadata may also include additional information about the structure (such as the width and / or height of the structure). For example, the location metadata may be optimized by only including metadata common to multiple structures once.

[0126] The selection data 2004 may include a list of regions, and for each region n bits indicating whether each via in vias Via1...ViaN is to be enabled (bit value "1") or disabled (bit value "0"). Here, the bit position corresponds to the index of the via in the via position metadata 2003. Multiple bits may be used instead of a single bit to indicate selected and / or non-selected vias in the selection data. In this example, the regions are numbered from Field1 to FieldM, with M being any positive index number. It should be understood that any other identification of the region may be used instead, or the identification of the region may be omitted entirely by using the position of each set of region bits within the file (e.g., counting the line number) as the identification of the region.

[0127] The rasterizer 1071 may receive the selection data 2004 or a subset of the selection data related to the areas to be exposed on the wafer. The selection data 2004 may be used to enable and disable corresponding vias at locations within the design layout defined by the via location metadata 2003 .

[0128] Figure 6 Presenting the data flow in a portion of a data path involved in the creation of pattern bitmap data 2009 according to an exemplary embodiment of the present invention. The data is displayed as parallelograms and the processing steps are shown as rectangular boxes.

[0129] At the beginning of the data flow on the left, the pre-processed design layout data 2008 may have been processed by the rasterizer 1071 (e.g. Figure 23021A or any other processing unit that is preferably part of the lithography subsystem 1070) into an intermediate 4-bit per pixel grayscale bitmap 3021B or any other suitable bitmap format. This intermediate 4bpp grayscale bitmap 3021B may include all structures (e.g., vias) from which to select to create a unique chip. Optionally, the intermediate 4bpp grayscale bitmap is in a compressed format 3021A and is decompressed in a decompression step 3035. ZIP compression or any other suitable compression format may be used as the compression format.

[0130] The position metadata 2003 (e.g., via position metadata) and the selection data 2004 on the upper right corner may be input to an erase bitmap creation process 3033 for creation of an erase bitmap 3023A. The erase bitmap is typically in a form that allows it to be used as a mask to erase vias in the intermediate 4bpp grayscale bitmap. The erase bitmap 3023A may be stored intermediately in a compressed format and may be decompressed, possibly in real time, prior to use in the merge operation 3034.

[0131] In a merge operation 3034, the intermediate 4bpp grayscale bitmap and the erase bitmap may be merged (e.g., using an OR operation), resulting in non-selected vias defined in the selection data and reflected in the erase bitmap to be deleted from the intermediate 4bpp grayscale bitmap. To this end, for example, bits defining vias in the intermediate 4bpp grayscale bitmap are assigned a binary zero value for non-selected vias.

[0132] As shown in processing step 3032A, the resulting 4bpp grayscale bitmap 3021C may be processed for pattern streamer correction and a B / W dithering operation may be performed. Processing step 3032A may be similar to Figure 3 Operation 3032. This may result in a method for controlling a maskless pattern writer such as, Figure 3 Pattern bitmap data 2009 of the maskless pattern writer 1073).

[0133] Processes 3033, 3034, 3035, and 3032A may be performed by rasterizer 1071 or any other processing unit (preferably part of lithography subsystem 1070). Processes 3032A, 3034, and / or 3035 may be performed in real time. Typically, Figure 6 One or more of the processing steps shown in are performed in the RAM memory and the erase bitmap 3023A, the intermediate 4bpp grayscale bitmap 3021B and / or the 4bpp grayscale bitmap 3021C or parts thereof are stored in the RAM memory only during the processing of the data into the pattern bitmap data 2009. In order to improve the processing performance, preferably, the merging operation 3034 and possibly also the decompression operation 3035 are implemented in hardware (for example, in an FPGA or an ASIC).

[0134] In an exemplary embodiment, the intermediate 4bpp grayscale bitmap 3021B can define a strip of an area of ​​the wafer (e.g., covering an area of ​​2μm by 33mm of the wafer). Each 4-bit pixel of the intermediate 4bpp grayscale bitmap 3021B can cover an area of ​​5.4nm by 5.4nm. The erase bitmap 3023A can be a 1bpp bitmap covering a strip or scan line on the wafer (e.g., covering an area of ​​2μm by 330mm). In this example, each 1-bit pixel of the erase bitmap 3023A can cover an area of ​​43.2nm by 43.2nm. Therefore, the erase bitmap can have a lower resolution than the intermediate 4bpp grayscale bitmap, resulting in the merge operation 3034 erasing a larger area in the intermediate 4bpp grayscale bitmap.

[0135] In another exemplary embodiment, an intermediate multi-level grayscale bitmap (such as a 4bpp grayscale bitmap 3021B) can define a strip of an area of ​​a wafer (e.g., covering an area of ​​2 μm by 33 mm of the wafer). Each 4-bit pixel of the intermediate 4bpp grayscale bitmap 3021B can cover an area of ​​5.4 nm by 5.4 nm. The erase bitmap 3023A can be a 4bpp sparse bitmap covering a strip on the wafer (e.g., covering an area of ​​2 μm by 330 mm). In this example, each 4-bit pixel of the erase bitmap 3023A can cover an area of ​​5.4 nm by 5.4 nm. Therefore, the erase bitmap can have the same resolution as the intermediate 4bpp grayscale bitmap, so that the merge operation 3034 erases pixels at the precise location defined by the erase bitmap 3023A.

[0136] Optionally, especially when in a sparse bitmap format, the erase bitmap data 3023A can be stored in RAM in a compressed format and decompressed on the fly when the merge operation 3034 is performed.

[0137] exist Figure 6 In the example of , an erase bitmap 3023A indicating vias to be deleted is merged with an intermediate bitmap 3021B producing a bitmap 3021C in which the vias are deleted. A similar erase operation can be performed on a vector format data file instead of operating on data in a bitmap format. Instead of an intermediate 4bpp grayscale bitmap 3021B, a vector-based data file includes all selectable structures (e.g., vias), which can then be merged with the vector-based erase data file defining the structures to be deleted or disabled. In this alternative example, the result of the merge operation will typically be in a vector-based data format, which can be converted into pattern bitmap data 2009 in one or more steps for controlling a maskless pattern writer.

[0138] The erase bitmap and the erase vector data may be collectively referred to as erase mask data.

[0139] Figure 7 A process of creating a unique chip according to an exemplary embodiment of the present invention is shown. A cross-sectional side view of a wafer is shown at six stages (A)-(F) of creating a unique chip. At each stage, the wafer shown includes multiple layers 201-206. Between stages (A)-(F), the same pattern indicates the same layer. In this example, charged particle multibeam lithography is used to create the common portion 101 of the chip and the personalized area 102 of the chip.

[0140] At the beginning of process (A), the wafer may include five layers: bottom metal layer 201, isolation layer 202 (eg, SiO2), bottom layers 203 and 204 (eg, SOC+SiARC HM), and top e-beam resist layer 206 (eg, KrF resist).

[0141] The top layer 206 can be exposed using electron beam exposure under the control of the pattern bitmap data 2009 depicted by the top arrow, followed by a development step in which the structure defined by the electron beam is removed from the resist layer 206. The result of the development step is shown in stage (B). In the etching and stripping steps, these structures can be etched to the SOC bottom layer 204 and the SiARC bottom layer 203, and the resist can be removed. The result is shown in stage (C). The structure can then be etched into the isolation layer 202, and the bottom layer 203, 204 can be stripped, and the result is shown in stage (D).

[0142] Next, a conductive layer 207 may be applied to the etched and stripped isolation layer for both the same and unique portions of the chip, the result of which is shown as stage (E). For example, chemical vapor deposition with tungsten (CVD-W) may be used. Chemical mechanical planarization (CMP) may remove the excess conductive material resulting in stage (F), where the wafer may have a bottom metal layer 201 and include isolation material and conductive material on top. Vias may be created through this conductive material.

[0143] exist Figure 7 In the example of , vias can be created in a single layer (i.e., the second layer from the bottom). The process can be changed to create conductive material at different layers, for creating vias at different layers and / or multiple layers, conductive material can be created for vias at multiple layers. The process can be changed to create connections between metal layers and gates (e.g., in contact layers) to create connections in local interconnect layers. The process can also or additionally change the formation or structure of diffusion regions (e.g., P or N doped regions), or enable or disable P or N implants for certain portions of transistors or diodes.

[0144] An example of using the personalization part of the chip describes the above Figure 7 In an embodiment of the present invention, the chip includes a unique arrangement of conductive vias formed using maskless lithography. The structure of the unique chip can be further improved by merging adjacent conductive vias produced using a maskless lithography process to effectively form a larger single via, such as Fig. 10A (side view) and 10B (top view). Fig.11A As shown in 11A (side view) and 11B (top view), in conventional methods using mask-based lithography, multiple circular vias 217d, 217e can be used to form an electrical connection between two metal layers 211c, 211d. Due to the limitations of the optical system used in conventional lithography, it is difficult to merge these vias into a single larger elliptical via in implementation. Using a maskless charged particle lithography system does not have these constraints, and a larger elliptical single via 217c connecting metal layers 211a, 211b can be produced (for example, by exposing two vias 217a, 217b together to merge them). This enables a more reliable connection between the two metal layers, which can conduct more current and produce further improvements in unique chips.

[0145] Figure 8 A simplified schematic diagram of an exemplary embodiment of a charged particle multi-beam lithography machine 1 is shown, which can be used to implement a maskless pattern writer 1073. Such a lithography machine suitably includes: a beam generator that generates multiple beams; a beam modulator that patterns the beams into modulated beams; and a beam projector for projecting the beams onto the surface of a target. For example, the target is a wafer. The beam generator typically includes a source and at least one aperture array. The beam modulator is typically a beam blanker having a blanking deflector array and a beam stop array. The beam projector typically includes a scanning deflector and a projection lens system.

[0146] The lithography machine 1 may include an electron source 3 for generating a uniform, expanded electron beam 4. The beam energy is preferably maintained in a relatively low range of about 1 to 10 keV. To achieve this, the acceleration voltage is preferably low and the electron source is preferably maintained at a target of about -1 to -10 kV relative to ground potential, but other settings may also be used.

[0147] The electron beam 4 from the electron source 3 can pass through a double octupole and then through a collimating lens 5 for collimating the electron beam 4. It will be appreciated that the collimating lens 5 can be any type of collimating optical system. Subsequently, the electron beam 4 can be irradiated on a beam splitter, which in a suitable embodiment is an aperture array 6A. The aperture array 6A can block part of the beam and can allow a plurality of sub-beams 20 to pass through the aperture array 6A. The aperture array preferably comprises a plate with through holes. Therefore, a plurality of parallel electron sub-beams 20 can be generated.

[0148] The second aperture array 6B can generate multiple beamlets 7 from each sub-beam. A beamlet is also called an electron beam. The system can generate a large number of beamlets 7, preferably about 10,000 to 1,000,000 beamlets, but of course more or fewer beamlets can be used. Note that other known ways to generate collimated beamlets can also be used. This allows manipulation of the sub-beams, which proves to be beneficial to the operation of the system, especially when the number of beamlets increases to 5,000 or more. For example, such manipulation is performed by a focusing lens, a collimator, or a lens structure that converges the sub-beams to the optical axis (for example, in the plane of the projection lens).

[0149] A condenser lens array 21 (or a collection of condenser lens arrays) may be included behind the sub-beam creating aperture array 6A for focusing the sub-beams 20 toward corresponding openings in the beam stop array 10. A second aperture array 6B may generate beams 7 from the sub-beams 20. Preferably, the beam creating aperture array 6B is combined with a beam blanker array 9. For example, the two may be assembled together to form a subassembly. Figure 8 , the aperture array 6B generates three beams 7 from each beamlet 20, which hit the beam stop array 10 at the corresponding openings, so that the three beams pass through the projection lens system in the end module 22 and are projected onto the target. In practice, a larger number of beams can be generated by the aperture array 6B for each projection lens system in the end module 22. In one embodiment, although the number of beams per sub-beam can be increased to 200 or more, 49 beams (arranged in a 7x7 array) can be generated from each sub-beam and directed through a single projection lens system.

[0150] The stepwise generation of the beam 7 from the intermediate stages of the beam 4 through the sub-beams 20 has the following advantages: the main optical operations can be performed with a relatively limited number of sub-beams 20 and at locations relatively far from the target. One such operation is the convergence of the sub-beams to a point corresponding to one of the projection lens systems. Preferably, the distance between the operation and the convergence point is greater than the distance between the convergence point and the target. Most preferably, it is used in combination with an electrostatic projection lens. This convergence operation enables the system to meet the requirements of reduced spot size, increased current and reduced spot spread, thereby performing reliable charged particle beam lithography at advanced nodes, especially at nodes with critical dimensions less than 90nm.

[0151] Next, the beam 7 may pass through a modulator array 9. This modulator array 9 may include a beam blanker array having a plurality of blankers, each of which is capable of deflecting one or more electron beams 7. More specifically, the blanker may be an electrostatic deflector provided with a first and a second electrode, the second electrode being a ground electrode or a common electrode. The beam blanker array 9 constitutes a modulation device having a beam stop array 10. Based on the beam control data, the modulation device 8 may add a pattern to the electron beam 7. The pattern may be projected onto the target 24 by components present in the end module 22.

[0152] In this embodiment, the beam stop array 10 comprises an array of apertures for allowing the beam to pass through. In its basic form, the beam stop array may comprise a substrate provided with vias, typically circular, although other shapes may be used. In one embodiment, the substrate of the beam stop array 8 may be formed from a silicon wafer having an array of regularly spaced vias, and may be coated with a metal surface layer to prevent surface charging. In one embodiment, the metal may be of a type that does not form a native oxide skin (such as CrMo).

[0153] In one embodiment, the channels of the beam stop array 10 may be aligned with the holes in the beam blanker array 9. The beam blanker array 9 and the beam stop array 10 generally operate together to block the beam 7 or to let the beam 7 pass through. If the beam blanker array 9 deflects the beam, it will not pass through the corresponding aperture in the beam stop array 10, but will be blocked by the substrate of the beam blanker array 10. But if the beam blanker array 9 does not deflect the beam, then it will pass through the corresponding aperture in the beam stop array 10, and then be projected as a spot on the target surface 13 of the target 24.

[0154] The lithography machine 1 may also include a data path for providing beam control data (e.g., in the form of pattern bitmap data 2009) to the beam blanker array 9. The beam control data may be transmitted using optical fiber. A modulated light beam from each optical fiber end may be projected onto a photosensitive element on the beam blanker array 9. Each light beam may hold a portion of the pattern data for controlling one or more modulators coupled to the photosensitive element.

[0155] Subsequently, the electron beam 7 may enter the end module. In the following, the term "beam" refers to the modulated beam. Such a modulated beam effectively comprises time-sequential portions. Some of these sequential portions may have a lower intensity and preferably have zero intensity - i.e., portions that stop at a beam stop. Some portions may have zero intensity in order to allow the beam to be positioned to a starting position for a subsequent scan cycle.

[0156] The end module 22 is preferably constructed as an insertable, replaceable unit that includes various components. In this embodiment, the end module may include: a beam stop array 10, a scanning deflector array 11, and a projection lens arrangement 12, but not all of these need to be included in the end module and they may be arranged differently.

[0157] After passing through the beam stop array 10, the modulated beams 7 may pass through a scanning deflector array 11, which provides a deflection of each beam 7 in the X and / or Y direction, substantially perpendicular to the direction of the undeflected beam 7. In this embodiment, the deflector array 11 may be a scanning electrostatic deflector, enabling a relatively small drive voltage to be applied.

[0158] Next, the beam can pass through the projection lens arrangement 12 and can be projected onto a target surface 24 of a target (usually a wafer) in a target plane. For photolithography applications, the target typically includes a wafer having a charged particle sensitive layer or a resist layer. For example, the projection lens arrangement 12 can focus the beam, resulting in a geometric spot size of approximately 10 to 30 nanometers in diameter. For example, the projection lens arrangement 12 in this design provides a reduction ratio of approximately 100 to 500 times. In this preferred embodiment, the projection lens arrangement 12 is advantageously positioned close to the target surface.

[0159] In some embodiments, a beam protector may be located between the target surface 24 and the focusing projection lens arrangement 12. The beam protector may be a foil or plate with the required aperture to absorb resist particles released from the wafer before they can reach any sensitive components in the lithography machine. Alternatively or additionally, a scanning deflection array 9 may be disposed between the projection lens arrangement 12 and the target surface 24.

[0160] Roughly speaking, the projection lens arrangement 12 focuses the beam 7 onto the target surface 24. Thereby, it further ensures that the spot size of the individual pixels is correct. The scanning deflector 11 may deflect the beam 7 over the target surface 23. Thereby, it is necessary to ensure that the position of the pixels on the target surface 24 is correct on a microscopic scale. In particular, the operation of the scanning deflector 11 needs to ensure that the pixels fit well into the grid of pixels that ultimately constitute the pattern on the target surface 24. It will be appreciated that the macroscopic scale positioning of the pixels on the target surface is appropriately enabled by a wafer positioning system located below the target 24.

[0161] Such high-quality projection may be related to obtaining a photolithography machine that provides reproducible results. Typically, the target surface 24 includes a resist film located on top of the substrate. The portion of the resist film can be chemically modified by applying a beam of charged particles (i.e., electrons). As a result, the irradiated portion of the film can be more or less dissolved in the developer, thereby producing a resist pattern on the wafer. The resist pattern on the wafer can then be transferred to the layer below (i.e., by realization, etching and / or deposition steps known in the semiconductor manufacturing field). Obviously, if the irradiation is uneven, the resist may not be developed in a uniform manner, resulting in errors in the pattern. Moreover, many such photolithography machines use multiple beams. The irradiation difference should not be caused by the deflection step.

[0162] Fig. 9 A conceptual diagram of an exemplary charged particle lithography system 1A is shown, which is divided into three high-level subsystems: a wafer positioning system 25, an electron optical column 20, and a data path 30. The wafer positioning system 25 moves the wafer 24 under the electron optical column 20 in the x-direction. The wafer positioning system 25 may have a synchronization signal from the data path subsystem 30 to align the wafer with the electron beam wave generated by the electron optical column 20. The electron optical column 20 may include, for example, Figure 8 The charged particle multi-beam lithography machine 1 shown in FIG. The pattern bitmap data 2009 can also be used to control the switching of the beam blanker array 9 via the data path subsystem 30. Figure 3 To implement the data path subsystem 30.

[0163] As shown in the above examples, a maskless pattern writer can apply a raster scan to a wafer under the control of the pattern bitmap data. Alternatively, a maskless pattern writer can apply a vector scan to a wafer. Vector scanning generally differs from raster scanning in that it does not sequentially traverse every location of the wafer; instead, it finishes exposing one local area and flies to the next area. With vector scanning, a beam build-up time is generally required before subsequent exposures can resume. This build-up time is generally not required with raster scanning. The pattern bitmap data and control data used for vector scanning may generally be referred to as beam steering data.

[0164] One or more embodiments of the present invention may implement a computer program product for use with a computer system. The program of the program product may define the functionality of the embodiments (including the methods described herein) and may be contained on various computer-readable storage media. The computer-readable storage medium may be a non-transient storage medium. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., a read-only memory device within a computer, such as a CD-ROM disk readable by a CD-ROM drive, a ROM chip, or any type of solid-state non-volatile semiconductor memory), on which information may be permanently stored; and (ii) writable storage media (e.g., a hard drive or any type of solid-state random access semiconductor memory, flash memory), on which variable information may be stored.

Claims

1. A method for manufacturing an electronic device using a maskless lithography exposure system, wherein the maskless lithography exposure system uses a maskless pattern writer, the method comprising: generating beam control data for controlling the maskless pattern writer to expose a wafer for creating the electronic device, wherein the beam control data is generated based on: designing layout data defining a plurality of structures for said electronic device to be fabricated from said wafer, wherein said structures include connections between metal layers; as well as selection data defining which of the structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, the selection data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selectable from the structures applicable to the certain electronic devices according to the selection data to make the electronic devices unique, Wherein exposing the wafer according to the beam steering data results in exposing patterns having different sets of the structures for different subsets of the electronic devices.

2. The method according to claim 1, wherein the design layout data comprises: Common design layout data defines a structure applicable to all of the electronic devices.

3. The method of claim 1 or 2, wherein the selection data specifies, for each of the electronic devices, whether the beam steering data includes or does not include data defining one or more of the structures defined in the design layout data. 4 . The method according to claim 1 , wherein the design layout data only includes design layout data defining the structure that can be selected according to the selection data.

5. The method according to any one of claims 1 to 4, further comprising: Receiving the design layout data in the maskless lithography exposure system via a first network path; as well as The selection data is received in the maskless lithography exposure system via a second network path separate from the first network path.

6. The method according to any one of claims 1 to 5, further comprising: Position metadata specifying a location of the structure defined in the design layout data is received.

7. The method of any one of claims 1-6, wherein the step of generating the beam steering data is additionally based on position metadata, wherein the position metadata specifies the position of the structure defined in the design layout data.

8. The method according to claim 6, further comprising: Erasure mask data is generated based on the position metadata and the selection data.

9. The method according to claim 8, wherein the generating of the beam steering data comprises: The erase mask data is merged with the design layout data or a derivative of the design layout data to delete non-selected structures from the design layout data.

10. The method according to claim 8 or 9, wherein the erase mask data is in a bitmap format.

11. The method of claim 10, wherein the design layout data or a derivative of the design layout data merged with the erase mask data is a multi-level grayscale bitmap.

12. The method of claim 11, wherein the multi-level grayscale bitmap is a 4bpp grayscale bitmap.

13. The method of claim 11 or 12, wherein the merging of the erase mask data with the design layout data or a derivative of the design layout data produces erase vias in the multi-level greyscale bitmap.

14. The method of claim 13, wherein the merging of the multi-level grayscale bitmap with the erase mask data in the bitmap format is performed using an OR operation, resulting in non-selected vias defined in the selection data and reflected in the erase mask data being deleted from the multi-level grayscale bitmap.

15. The method of any one of claims 11 to 14, wherein the erase mask data has a lower resolution than the multi-level grayscale bitmap, resulting in the merging erasing a larger area in the multi-level grayscale bitmap.

16. The method of any one of claims 10 to 15, wherein the erase mask data is a 1 bpp bitmap.

17. The method of claim 16, wherein the erase mask data covers a stripe or scan line on the wafer.

18. The method of any one of claims 11 to 14, wherein the multi-level grayscale bitmap is a 4bpp grayscale bitmap, and wherein the erase mask data is a 4bpp sparse bitmap, resulting in the merged erasing pixels at exact locations defined by the erase bitmap.

19. The method of claim 18, wherein the multi-level grayscale bitmap defines a stripe of an area of ​​a wafer, and wherein the 4bpp sparse bitmap covers a stripe on the wafer.

20. The method according to any one of claims 1 to 19, wherein the electronic device is a semiconductor chip, and wherein the maskless pattern writer is a charged particle multibeam lithography machine.

21. The method according to any one of claims 1 to 20, wherein the structure further comprises at least one of the following: The connection between the metal layer and the gate in the contact layer; connections in the local interconnect layer; P or N implantation of certain parts of a transistor or diode.

22. An electronic device created using a method of manufacturing an electronic device using a maskless lithography exposure system using a maskless pattern writer, the method comprising: generating beam control data for controlling the maskless pattern writer to expose a wafer for creating the electronic device, wherein the beam control data is generated based on: designing layout data defining a plurality of structures for said electronic device to be fabricated from said wafer, wherein said structures include connections between metal layers; as well as selecting data defining which of the structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, the selecting data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selected from the structures applicable to the certain electronic devices according to the selecting data to make the electronic devices unique, Wherein exposing the wafer according to the beam steering data results in exposing patterns having different sets of the structures for different subsets of the electronic devices.

23. The electronic device of claim 22, wherein the electronic device is a truly unique semiconductor chip that is different from any other semiconductor chip created.

24. An electronic device according to claim 22 or 23, comprising a metal layer and an adjacent layer, wherein the structure defined by the non-shared design layout data comprises a connection between the metal layer and the adjacent layer.

25. A maskless lithography exposure system configured to perform a method of manufacturing an electronic device using the maskless lithography exposure system, the maskless lithography exposure system using a maskless pattern writer, the method comprising: generating beam control data for controlling the maskless pattern writer to expose a wafer for creating the electronic device, wherein the beam control data is generated based on: designing layout data defining a plurality of structures for said electronic device to be fabricated from said wafer, wherein said structures include connections between metal layers; as well as selecting data defining which of the structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, the selecting data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selected from the structures applicable to the certain electronic devices according to the selecting data to make the electronic devices unique, Wherein exposing the wafer according to the beam steering data results in exposing patterns having different sets of the structures for different subsets of the electronic devices.

26. The maskless lithography exposure system according to claim 25 comprises a black box device configured to generate the selection data, wherein the selection data defines which structures of the structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, and the selection data defines different sets of the structures for different subsets of the electronic devices.

27. A semiconductor manufacturing equipment comprising the maskless lithography exposure system according to claim 25 or 26.

28. A lithography subsystem comprising a rasterizer and a maskless pattern writer, wherein the rasterizer is configured to generate beam steering data for controlling the maskless pattern writer to expose a wafer for creating an electronic device, wherein the beam steering data is generated based on: designing layout data defining a plurality of structures for the electronic device to be fabricated from the wafer, wherein the structures include connections between metal layers; and selection data defining which of the structures of the design layout data are applicable to each electronic device to be manufactured from the wafer, the selection data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selectable from the structures applicable to the certain electronic devices according to the selection data to make the electronic devices unique, Wherein exposing the wafer according to the beam steering data results in exposing patterns having different sets of the structures for different subsets of the electronic devices.

29. The lithography subsystem of claim 28, wherein the rasterizer is configured to: receiving pattern vector data in a lithography subsystem specific format generated from the design layout data; receiving the selection data; receiving position metadata specifying a location of each of the structures defined in the design layout data and selectable according to the selection data; as well as The pattern vector data, the position metadata, and the selection data are processed to obtain the beam steering data.

30. A computer-implemented method for generating beam steering data for controlling a maskless pattern writer to expose a wafer for creating electronic devices using a maskless lithography exposure system, the maskless lithography exposure system using a maskless pattern writer, such that exposure of the wafer according to the beam steering data results in exposing patterns having different sets of structures for different subsets of the electronic devices, the method comprising: receiving design layout data defining a plurality of structures for the electronic device to be fabricated from the wafer, wherein the structures include connections between metal layers; receiving selection data defining which of the structures of the design layout data are applicable to each electronic device to be fabricated from the wafer, the selection data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selectable from the structures applicable to the certain electronic devices according to the selection data to render the electronic devices unique; as well as The beam steering data is generated based on the received design layout data and the received selection data.

31. The method of claim 30, wherein the step of generating the beam steering data is additionally based on position metadata, wherein the position metadata specifies the location of the structure defined in the design layout data.

32. The method of claim 31 , further comprising generating erase mask data based on the position metadata and the selection data, and wherein the generating of the beam steering data comprises merging the erase mask data with the design layout data or a derivative of the design layout data to delete non-selected structures from the design layout data.

33. A data processing system comprising a processor configured to perform a computer-implemented method for generating beam steering data for controlling a maskless pattern writer to expose a wafer for creating electronic devices using a maskless lithography exposure system, the maskless lithography exposure system using a maskless pattern writer such that exposure of the wafer according to the beam steering data results in exposure of patterns having different sets of structures for different subsets of the electronic devices, the method comprising: receiving design layout data defining a plurality of structures for the electronic device to be fabricated from the wafer, wherein the structures include connections between metal layers; receiving selection data defining which of the structures of the design layout data are applicable to each electronic device to be fabricated from the wafer, the selection data defining different sets of the structures for different subsets of the electronic devices, wherein the design layout data includes non-common design layout data defining structures applicable to certain electronic devices of the electronic devices, the different sets of structures being selectable from the structures applicable to the certain electronic devices according to the selection data to render the electronic devices unique; as well as The beam steering data is generated based on the received design layout data and the received selection data.

34. A computer-implemented method for generating selection data defining a structure of design layout data suitable for an electronic device to be fabricated from a wafer, the method comprising: The selection data is generated by defining which of the structures in the design layout data are applicable to each electronic device to be manufactured from the chip, so that the selection data defines different sets of the structures for different subsets of electronic devices, wherein the structures include connections between metal layers, and wherein the design layout data includes non-shared design layout data, which defines structures applicable to certain electronic devices of the electronic devices, and different sets of the structures can be selected from the structures applicable to the certain electronic devices according to the selection data to make the electronic device unique.

35. The method of claim 34, wherein the generating of the selection data further comprises defining a location of each of the structures within a design layout of the electronic device defined by the design layout data.

36. A data processing system comprising a processor configured to perform a computer-implemented method for generating selection data defining a structure of design layout data suitable for an electronic device to be manufactured from a wafer, the method comprising: The selection data is generated by defining which of the structures in the design layout data are applicable to each electronic device to be manufactured from the chip, so that the selection data defines different sets of the structures for different subsets of electronic devices, wherein the structures include connections between metal layers, and wherein the design layout data includes non-shared design layout data, which defines structures applicable to certain electronic devices of the electronic devices, and different sets of the structures can be selected from the structures applicable to the certain electronic devices according to the selection data to make the electronic device unique.

37. A computer program product implemented on a computer-readable non-transitory storage medium, comprising instructions which, when executed by a computer, cause the computer to perform a computer-implemented method for generating selection data defining a structure of design layout data suitable for an electronic device to be manufactured from a wafer, the method comprising: The selection data is generated by defining which of the structures in the design layout data are applicable to each electronic device to be manufactured from the chip, so that the selection data defines different sets of the structures for different subsets of electronic devices, wherein the structures include connections between metal layers, and wherein the design layout data includes non-shared design layout data, which defines structures applicable to certain electronic devices of the electronic devices, and different sets of the structures can be selected from the structures applicable to the certain electronic devices according to the selection data to make the electronic device unique.

38. A computer-readable non-transitory storage medium comprising instructions which, when executed by a computer, cause the computer to perform a computer-implemented method for generating selection data defining a structure of design layout data suitable for an electronic device to be manufactured from a wafer, the method comprising: The selection data is generated by defining which of the structures in the design layout data are applicable to each electronic device to be manufactured from the chip, so that the selection data defines different sets of the structures for different subsets of electronic devices, wherein the structures include connections between metal layers, and wherein the design layout data includes non-shared design layout data, which defines structures applicable to certain electronic devices of the electronic devices, and different sets of the structures can be selected from the structures applicable to the certain electronic devices according to the selection data to make the electronic device unique.

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