An approximate squarer and an approximate circuit feature recognition method

Abstract

The present invention discloses an approximate squarer, which includes an accurate Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an accurate partial product compression circuit, an approximate partial product compression circuit, and a carry-ripple adder circuit; the accurate Booth folding encoder and decoder divide the high n-k bits of the input operand into groups of three bits, generate the accurate partial products of part P and the accurate partial products of part C, and output them to the accurate partial product compression circuit; the approximate Booth folding encoder and decoder divide the low k bits of the input operand into groups of three bits, generate the approximate partial products of part P and the approximate partial products of part C, and output them to the approximate partial product compression circuit. The present invention can achieve lower power consumption and area, lower cost; and has a faster calculation speed, which is more advantageous for communication and machine learning applications.

Description

Technical Field

[0001] The present invention relates to the technical field of approximate arithmetic operation circuit design, and in particular to an approximate squarer and an approximate circuit feature recognition method. Background Art

[0002] With the development of embedded and mobile computing systems, computing tasks involve more and more applications. An important feature of these applications is a high error tolerance for calculation results, and there are a large number of data processing processes, which brings more resource consumption. Therefore, applying approximate computing technology to fault-tolerant applications can reduce the power consumption of hardware circuits as much as possible while meeting the performance requirements of the application system.

[0003] Squarers are widely used in the fields of communication and artificial intelligence, such as the square-law detector for demodulating signals and minimizing the Euclidean distance in machine learning algorithms. The data in these applications will be superimposed with noise during transmission, and high performance can be maintained even if calculation errors are introduced through approximate operations. The existing squaring operations are mainly implemented through multiplier circuits, which will bring large circuit redundancy, resulting in higher area and power consumption of integrated circuits and causing unnecessary waste. Therefore, designing an approximate squarer circuit with a calculation result that is not completely accurate but does not affect the normal use of the application can greatly reduce the hardware resource consumption of the circuit. In addition, due to the increasing importance of approximate circuit research, how to determine whether the same approximate design is used in other approximate circuits has become a key issue.

[0004] The Chinese patent (publication number CN113778377A) published on December 10, 2021 mentions a squarer structure based on radix-8 Booth folding coding. This squarer uses folding coding to simplify the partial product structure and invents a radix-8 Booth folding squaring algorithm to further reduce the number of partial products and the height of the partial product matrix. Considering the disadvantages of radix-8 Booth coding, an approximate partial product generator is designed to simplify the circuits of the radix-8 Booth encoder and decoder. In addition, two approximate adders are designed, and by introducing approximate adders in the partial product compression module, the hardware resource consumption of the squarer is further reduced. However, this invention requires the aid of signal m and does not involve a method for recognizing approximate circuit features. When the input bit width of the squarer is relatively low, such as 8 bits and 16 bits, the radix-8 Booth encoder and decoder designed in this invention will consume too much hardware resources, and the radix-8 Booth coding method requires additional adders to be used in the partial product generation circuit, which will cause the critical path delay of this operation to become longer and affect the calculation speed. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention provides an approximate squarer and an approximate circuit feature recognition method, which has lower power consumption and area compared with the existing approximate squarer, lower cost, and faster calculation speed, and has more advantages in communication and machine learning applications.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] An approximate squarer, which includes an exact Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an exact partial product compression circuit, an approximate partial product compression circuit, and a ripple-carry adder circuit;

[0008] Let the input bit width of the approximate squarer be n, and the binary representation be a i , n - 1 ≤ i ≤ 0; the exact Booth folding encoder and decoder divide the high n - k bits of the input operand into groups of three bits, generate the exact partial products of part P and the exact partial products of part C, and output them to the exact partial product compression circuit. Both n and k are positive integers; the exact partial product compression circuit uses an exact adder to compress all the exact partial products into two rows and outputs them to the ripple-carry adder;

[0009] The approximate Booth folding encoder and decoder divide the low k bits of the input operand into groups of three bits, generate the approximate partial products of part P and the approximate partial products of part C, and output them to the approximate partial product compression circuit; the approximate partial product compression circuit uses an approximate adder to compress all the approximate partial products into two rows and outputs them to the ripple-carry adder;

[0010] The ripple-carry adder processes the two rows of partial products generated by the exact partial product compression circuit and the approximate partial product compression circuit to generate the product structure of the final squarer;

[0011] The generation process of the exact partial products of part P and the exact partial products of part C includes:

[0012] A1. Use an exact Booth folding encoder to process the high n - k bits of the input operand to generate three output signals, and the expressions are respectively: and represents exclusive OR; represents negation;

[0013] A2. Use an exact Booth folding decoder to output the exact partial products of part P, and the expression of the exact partial products of part P is:

[0014] A3 generates the exact partial product of part C from the output signals x1 and x2. The expression for the exact partial product of part C is: C i,0 = X1, C i,1 = 0 and C i,2 = X2;

[0015] Among them, a 2i+1 、a 2i and a 2i-1 are the (2i + 1)-th, 2i-th, and (2i - 1)-th bits of the input operand respectively; represents the negation operation, represents the exclusive OR operation;

[0016] The generation process of the approximate partial product of part P and the approximate partial product of part C includes:

[0017] B1. Use an approximate Booth folding encoder to process the lower k bits of the input operand to generate two output signals. The expressions are respectively:

[0018] B2. Use an approximate Booth folding decoder to output the approximate partial product of part P. The expression is:

[0019] B3. Generate the approximate partial product of part C from the output signal x1'. The expression is:

[0020] To optimize the above technical solution, the specific measures taken also include:

[0021] Further, the exact partial product compression circuit is composed of exact adders.

[0022] Further, the approximate partial product compression circuit is composed of approximate 3-2 compressors; among them, the inputs of the approximate 3-2 compressor are p1, p2, p3, and the outputs are sum and carry: carry = p1 + p2 · p3.

[0023] Based on the foregoing approximate squarer, the present invention also mentions an approximate circuit feature recognition method. The approximate circuit feature recognition method includes the following steps:

[0024] S1. Compare the maximum error distances of different approximate squarers. If they are different, it is determined that there are different approximate features between the approximate squarers, and the process ends; if they are the same, go to step S2;

[0025] S2. Compare the average error distances of different approximate squarers. If they are different, it is determined that there are different approximate characteristics between the approximate squarers, and the process ends; if they are the same, go to step S3;

[0026] S3. Compare the values of different approximate squarers under all input states. If they are different, there are different approximate characteristics between the approximate squarers; if they are the same, it is determined that there are the same approximate characteristics between the approximate squarers.

[0027] The present invention discloses a high-performance approximate squarer based on Booth folding coding and a method for identifying approximate circuit characteristics thereof. The approximate squarer is composed of an accurate Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an approximate partial product compression circuit, an accurate partial product compression circuit, and a carry-ripple adder circuit. The high-performance approximate squarer based on Booth folding coding uses an approximate Booth folding encoder and decoder and an approximate partial product compression circuit for the low k bits; and uses an accurate Booth folding encoder and decoder and an accurate partial product compression circuit for the high n-k bits.

[0028] In addition, the present invention also discloses a method for identifying approximate characteristics of an approximate squarer circuit. According to the characteristic that an approximate circuit will generate specific errors, two methods are used in combination to identify the approximate squarer circuit. One method is the overall accuracy calculation of the approximate squarer circuit, and the accuracy of the approximate squarer is roughly determined by calculating its maximum error distance and average error distance. And in combination with another method to further lock the specific characteristics of the approximate squarer, by traversing all input cases, calculating the outputs of the approximate squarer under all binary input combinations, to find out all the approximate characteristics of the approximate squarer. Finally, the specific approximate characteristics of the approximate squarer circuit are identified in a low-cost manner.

[0029] The beneficial effects of the present invention are:

[0030] First, the present invention discloses an approximate squarer, which has lower power consumption and area compared with the existing approximate squarers, and lower cost; and has a faster calculation speed, which is more advantageous for communication and machine learning applications.

[0031] Second, the squarer circuit of the present invention has lower power consumption and area at low bit widths, and has fewer intermediate signals in the encoder and decoder circuits, which makes the circuit complexity lower.

[0032] Third, the present invention discloses a method for identifying approximate circuit characteristics, which can quickly identify approximate circuit characteristics, and then judge whether the same approximate design is used in other approximate circuits. Description of the Drawings

[0033] Figure 1Schematic diagram of the partial product processing process of the approximate squarer according to an embodiment of the present invention.

[0034] Figure 2 Truth table of the encoding of the approximate Booth folding encoder.

[0035] Figure 3 Gate-level circuit diagram of the approximate Booth folding encoder.

[0036] Figure 4 Gate-level circuit diagram of the approximate Booth folding decoder.

[0037] Figure 5 Gate-level circuit diagram of the approximate 3-2 compressor.

[0038] Figure 6 Approximate circuit feature recognition method according to an embodiment of the present invention. Detailed implementation mode

[0039] The present invention will now be further described in detail with reference to the accompanying drawings.

[0040] It should be noted that the terms such as "upper", "lower", "left", "right", "front", "rear", etc. cited in the invention are only for the convenience of narration and are not used to limit the scope of implementation of the present invention. The change or adjustment of their relative relationship shall be regarded as the scope of implementation of the present invention when there is no substantial change in the technical content.

[0041] This embodiment discloses an approximate squarer based on Booth folding encoding. The approximate squarer includes an accurate Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an accurate partial product compression circuit, an approximate partial product compression circuit, and a carry-ripple adder circuit.

[0042] Let the input bit width of the approximate squarer be n, and the binary representation be a i , n - 1 ≤ i ≤ 0; the accurate Booth folding encoder and decoder divide the high n - k bits of the input operand into groups of three bits, generate the accurate partial products of part P and the accurate partial products of part C, and output them to the accurate partial product compression circuit. Both n and k are positive integers; the accurate partial product compression circuit uses an accurate adder to compress all the accurate partial products into two rows and outputs them to the carry-ripple adder.

[0043] The approximate Booth folding encoder and decoder divide the low k bits of the input operand into groups of three bits, generate the approximate partial products of part P and the approximate partial products of part C, and output them to the approximate partial product compression circuit; the approximate partial product compression circuit uses an approximate adder to compress all the approximate partial products into two rows and outputs them to the carry-ripple adder.

[0044] The ripple - carry adder processes the two - row partial products generated by the exact partial - product compression circuit and the approximate partial - product compression circuit to generate the product structure of the final squarer.

[0045] The generation process of the exact partial products of the P part and the exact partial products of the C part includes:

[0046] A1, using an exact Booth folding encoder to process the high n - k bits of the input operand, generating three output signals, with expressions respectively as: and represents exclusive - or; represents negation.

[0047] A2, using an exact Booth folding decoder to output the exact partial products of the P part, and the expression of the exact partial products of the P part is:

[0048] A3, generating the exact partial products of the C part by means of the output signals x1 and x2, and the expression of the exact partial products of the C part is: C i,0 = x1, C i,1 = 0 and C i,2 = x2.

[0049] The generation process of the approximate partial products of the P part and the approximate partial products of the C part includes:

[0050] B1, using an approximate Booth folding encoder to process the low k bits of the input operand, generating two output signals, with expressions respectively as:

[0051] B2, using an approximate Booth folding decoder to output the approximate partial products of the P part, and the expression is:

[0052] B3, generating the approximate partial products of the C part by means of the output signal x1′, and the expression is: C i,0 ′ = x1′, Figure 2 is the encoding truth table of the approximate Booth folding encoder, where A i represents the encoded decimal value. Figure 3 and Figure 4 are respectively the approximate Booth folding encoder and the approximate Booth folding decoder

[0053] Figure 1 is the schematic diagram of the partial - product processing process of the approximate squarer in the embodiment of the present invention. Refer to Figure 1, after the input passes through the partial product generation circuit, a partial product array as shown in the first stage is generated, where solid circles represent exact partial products, which are generated by an exact Booth folding encoder and decoder. Hollow circles represent approximate partial products, which are generated by an approximate Booth folding encoder and decoder. In the first stage, the dashed boxes represent approximate 3-2 compressors, which together constitute the approximate partial product compression circuit. Figure 5 is the gate-level circuit diagram of the approximate 3-2 compressor. The solid boxes represent exact adders, which together constitute the exact partial product compression circuit. The exact and approximate partial product compression circuits compress all partial products into two rows and enter the second stage. Subsequently, the carry-ripple adder accumulates the two rows of partial products and enters the third stage to generate the final square product.

[0054] Exemplarily, the exact partial product compression circuit is used in the high n-k bits and is composed of exact adders.

[0055] Exemplarily, the approximate partial product compression circuit is used in the low k bits and is composed of approximate 3-2 compressors; where the inputs of the approximate 3-2 compressor are p1, p2, p3, and the outputs are sum and carry: carry = p1 + p2 · p3.

[0056] See Figure 6 , this embodiment also discloses an approximate feature recognition method for an approximate squarer circuit. In the first step, first compare the maximum error distances of the approximate squarer circuits. If they are different, there are different approximate features between the approximate squarers; if they are the same, then compare the average error distances of the approximate squarers. If they are different, there are different approximate features between the approximate squarers; if they are the same, then compare the values of the approximate squarers in all input states. If they are different, there are different approximate features between the approximate squarers; if they are the same, then there are the same approximate features between the approximate squarers.

[0057] The above are only the preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. An approximate squarer, characterized in that, The approximate squarer includes an exact Booth folding encoder and decoder circuit, an approximate Booth folding encoder and decoder circuit, an exact partial product compression circuit, an approximate partial product compression circuit, and a carry-ripple adder circuit; Let the input bit width of the approximate squarer be n, and its binary representation be a i , where n - 1 ≤ i ≤ 0; the precise Booth folding encoder and decoder divide the high n - k bits of the input operand into groups of three bits, generate the precise partial products of part P and the precise partial products of part C, and output them to the precise partial product compression circuit. Both n and k are positive integers; the precise partial product compression circuit uses precise adders to compress all the precise partial products into two rows and outputs them to the carry - ripple adder; The approximate Booth folding encoder and decoder divides the low k bits of the input operand into groups of three bits, generates the approximate partial products of the P part and the approximate partial products of the C part, and outputs them to the approximate partial product compression circuit; the approximate partial product compression circuit uses an approximate adder to compress all the approximate partial products into two rows and outputs them to the carry-ripple adder; The carry-ripple adder processes the two rows of partial products generated by the exact partial product compression circuit and the approximate partial product compression circuit to generate the product structure of the final squarer; The generation process of the exact partial products of the P part and the exact partial products of the C part includes: A1. The high n - k bits of the input operand are processed by an accurate Booth folding encoder to generate three output signals, and the expressions are respectively: x1 = a 2i ⊕a 2i-1 and A2, using an accurate Booth folding decoder to output the exact partial product of the P part. The expression for the exact partial product of the P part is: P i,j =(a 2i+j+2 ·x1 + a 2i+j+1 ·x2) ⊕ neg; A3 generates the exact partial product of part C through the output signals x1 and x2. The expression for the exact partial product of part C is: C i,0 = x1, C i,1 = 0 and C i,2 = x2; Among them, n - 1 ≤ j ≤ 0; a 2i+1 、a 2i and a 2i-1 are the (2i + 1)-th, 2i-th, and (2i - 1)-th bits of the input operand respectively; represents the negation operation, and ‘⊕’ represents the exclusive OR operation; The generation process of the approximate partial products of the P part and the approximate partial products of the C part includes: B1 processes the lower k bits of the input operand using an approximate Booth folding encoder to generate two output signals, with the expressions being: B2, an approximate Booth folding decoder is used to output an approximate partial product of the P part, and the expression is: P i,j ′ = (a 2i+j+2 ·x1) ⊕ neg′; B3 generates an approximate partial product of the C part by the output signal x1′, and the expression is: C i,0 ′ = x1′, 2. The approximate squarer according to claim 1, wherein The exact partial product compression circuit is composed of exact adders.

3. The approximate squarer according to claim 1, wherein The approximate partial product compression circuit is composed of approximate 3-2 compressors; among them, the inputs of the approximate 3-2 compressor are p1, p2, and p3, and the outputs are sum and carry: carry = p1 + p2·p3.

4. A method for identifying the approximate circuit characteristics of an approximate squarer according to any one of claims 1-3, characterized in that, The approximate circuit feature recognition method includes the following steps: S1. Compare the maximum error distances of different approximate squarers. If they are different, it is determined that there are different approximate features between the approximate squarers, and the process ends; if they are the same, go to step S2; S2. Compare the average error distances of different approximate squarers. If they are different, it is determined that there are different approximate features between the approximate squarers, and the process ends; if they are the same, go to step S3; S3. Compare the values of different approximate squarers in all input states. If they are different, there are different approximate features between the approximate squarers; if they are the same, it is determined that there are the same approximate features between the approximate squarers.

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